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Commit | Line | Data |
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b8842209 GH |
1 | /* |
2 | * QEMU IDE Emulation: MacIO support. | |
3 | * | |
4 | * Copyright (c) 2003 Fabrice Bellard | |
5 | * Copyright (c) 2006 Openedhand Ltd. | |
6 | * | |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
59f2a787 GH |
25 | #include <hw/hw.h> |
26 | #include <hw/ppc_mac.h> | |
27 | #include <hw/mac_dbdma.h> | |
b8842209 | 28 | #include "block.h" |
b8842209 | 29 | #include "dma.h" |
59f2a787 GH |
30 | |
31 | #include <hw/ide/internal.h> | |
b8842209 GH |
32 | |
33 | /***********************************************************/ | |
34 | /* MacIO based PowerPC IDE */ | |
35 | ||
36 | typedef struct MACIOIDEState { | |
23c5e4ca | 37 | MemoryRegion mem; |
b8842209 GH |
38 | IDEBus bus; |
39 | BlockDriverAIOCB *aiocb; | |
40 | } MACIOIDEState; | |
41 | ||
02c7c992 BS |
42 | #define MACIO_PAGE_SIZE 4096 |
43 | ||
b8842209 GH |
44 | static void pmac_ide_atapi_transfer_cb(void *opaque, int ret) |
45 | { | |
46 | DBDMA_io *io = opaque; | |
47 | MACIOIDEState *m = io->opaque; | |
48 | IDEState *s = idebus_active_if(&m->bus); | |
49 | ||
50 | if (ret < 0) { | |
51 | m->aiocb = NULL; | |
52 | qemu_sglist_destroy(&s->sg); | |
53 | ide_atapi_io_error(s, ret); | |
a597e79c | 54 | goto done; |
b8842209 GH |
55 | } |
56 | ||
57 | if (s->io_buffer_size > 0) { | |
58 | m->aiocb = NULL; | |
59 | qemu_sglist_destroy(&s->sg); | |
60 | ||
61 | s->packet_transfer_size -= s->io_buffer_size; | |
62 | ||
63 | s->io_buffer_index += s->io_buffer_size; | |
64 | s->lba += s->io_buffer_index >> 11; | |
65 | s->io_buffer_index &= 0x7ff; | |
66 | } | |
67 | ||
68 | if (s->packet_transfer_size <= 0) | |
69 | ide_atapi_cmd_ok(s); | |
70 | ||
71 | if (io->len == 0) { | |
a597e79c | 72 | goto done; |
b8842209 GH |
73 | } |
74 | ||
75 | /* launch next transfer */ | |
76 | ||
77 | s->io_buffer_size = io->len; | |
78 | ||
02c7c992 | 79 | qemu_sglist_init(&s->sg, io->len / MACIO_PAGE_SIZE + 1); |
b8842209 GH |
80 | qemu_sglist_add(&s->sg, io->addr, io->len); |
81 | io->addr += io->len; | |
82 | io->len = 0; | |
83 | ||
84 | m->aiocb = dma_bdrv_read(s->bs, &s->sg, | |
85 | (int64_t)(s->lba << 2) + (s->io_buffer_index >> 9), | |
86 | pmac_ide_atapi_transfer_cb, io); | |
87 | if (!m->aiocb) { | |
88 | qemu_sglist_destroy(&s->sg); | |
89 | /* Note: media not present is the most likely case */ | |
67cc61e4 | 90 | ide_atapi_cmd_error(s, NOT_READY, |
b8842209 | 91 | ASC_MEDIUM_NOT_PRESENT); |
a597e79c | 92 | goto done; |
b8842209 | 93 | } |
a597e79c CH |
94 | return; |
95 | ||
96 | done: | |
97 | bdrv_acct_done(s->bs, &s->acct); | |
98 | io->dma_end(opaque); | |
99 | return; | |
b8842209 GH |
100 | } |
101 | ||
102 | static void pmac_ide_transfer_cb(void *opaque, int ret) | |
103 | { | |
104 | DBDMA_io *io = opaque; | |
105 | MACIOIDEState *m = io->opaque; | |
106 | IDEState *s = idebus_active_if(&m->bus); | |
107 | int n; | |
108 | int64_t sector_num; | |
109 | ||
110 | if (ret < 0) { | |
111 | m->aiocb = NULL; | |
112 | qemu_sglist_destroy(&s->sg); | |
113 | ide_dma_error(s); | |
a597e79c | 114 | goto done; |
b8842209 GH |
115 | } |
116 | ||
117 | sector_num = ide_get_sector(s); | |
118 | if (s->io_buffer_size > 0) { | |
119 | m->aiocb = NULL; | |
120 | qemu_sglist_destroy(&s->sg); | |
121 | n = (s->io_buffer_size + 0x1ff) >> 9; | |
122 | sector_num += n; | |
123 | ide_set_sector(s, sector_num); | |
124 | s->nsector -= n; | |
125 | } | |
126 | ||
127 | /* end of transfer ? */ | |
128 | if (s->nsector == 0) { | |
129 | s->status = READY_STAT | SEEK_STAT; | |
9cdd03a7 | 130 | ide_set_irq(s->bus); |
b8842209 GH |
131 | } |
132 | ||
133 | /* end of DMA ? */ | |
b8842209 | 134 | if (io->len == 0) { |
a597e79c | 135 | goto done; |
b8842209 GH |
136 | } |
137 | ||
138 | /* launch next transfer */ | |
139 | ||
140 | s->io_buffer_index = 0; | |
141 | s->io_buffer_size = io->len; | |
142 | ||
02c7c992 | 143 | qemu_sglist_init(&s->sg, io->len / MACIO_PAGE_SIZE + 1); |
b8842209 GH |
144 | qemu_sglist_add(&s->sg, io->addr, io->len); |
145 | io->addr += io->len; | |
146 | io->len = 0; | |
147 | ||
4e1e0051 CH |
148 | switch (s->dma_cmd) { |
149 | case IDE_DMA_READ: | |
b8842209 GH |
150 | m->aiocb = dma_bdrv_read(s->bs, &s->sg, sector_num, |
151 | pmac_ide_transfer_cb, io); | |
4e1e0051 CH |
152 | break; |
153 | case IDE_DMA_WRITE: | |
b8842209 GH |
154 | m->aiocb = dma_bdrv_write(s->bs, &s->sg, sector_num, |
155 | pmac_ide_transfer_cb, io); | |
4e1e0051 | 156 | break; |
d353fb72 CH |
157 | case IDE_DMA_TRIM: |
158 | m->aiocb = dma_bdrv_io(s->bs, &s->sg, sector_num, | |
bbca72c6 | 159 | ide_issue_trim, pmac_ide_transfer_cb, s, true); |
d353fb72 | 160 | break; |
4e1e0051 CH |
161 | } |
162 | ||
b8842209 GH |
163 | if (!m->aiocb) |
164 | pmac_ide_transfer_cb(io, -1); | |
a597e79c CH |
165 | return; |
166 | done: | |
167 | if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) { | |
168 | bdrv_acct_done(s->bs, &s->acct); | |
169 | } | |
170 | io->dma_end(io); | |
b8842209 GH |
171 | } |
172 | ||
173 | static void pmac_ide_transfer(DBDMA_io *io) | |
174 | { | |
175 | MACIOIDEState *m = io->opaque; | |
176 | IDEState *s = idebus_active_if(&m->bus); | |
177 | ||
178 | s->io_buffer_size = 0; | |
cd8722bb | 179 | if (s->drive_kind == IDE_CD) { |
a597e79c | 180 | bdrv_acct_start(s->bs, &s->acct, io->len, BDRV_ACCT_READ); |
b8842209 GH |
181 | pmac_ide_atapi_transfer_cb(io, 0); |
182 | return; | |
183 | } | |
184 | ||
a597e79c CH |
185 | switch (s->dma_cmd) { |
186 | case IDE_DMA_READ: | |
187 | bdrv_acct_start(s->bs, &s->acct, io->len, BDRV_ACCT_READ); | |
188 | break; | |
189 | case IDE_DMA_WRITE: | |
190 | bdrv_acct_start(s->bs, &s->acct, io->len, BDRV_ACCT_WRITE); | |
191 | break; | |
192 | default: | |
193 | break; | |
194 | } | |
195 | ||
b8842209 GH |
196 | pmac_ide_transfer_cb(io, 0); |
197 | } | |
198 | ||
199 | static void pmac_ide_flush(DBDMA_io *io) | |
200 | { | |
201 | MACIOIDEState *m = io->opaque; | |
202 | ||
922453bc SH |
203 | if (m->aiocb) { |
204 | bdrv_drain_all(); | |
205 | } | |
b8842209 GH |
206 | } |
207 | ||
208 | /* PowerMac IDE memory IO */ | |
209 | static void pmac_ide_writeb (void *opaque, | |
c227f099 | 210 | target_phys_addr_t addr, uint32_t val) |
b8842209 GH |
211 | { |
212 | MACIOIDEState *d = opaque; | |
213 | ||
214 | addr = (addr & 0xFFF) >> 4; | |
215 | switch (addr) { | |
216 | case 1 ... 7: | |
217 | ide_ioport_write(&d->bus, addr, val); | |
218 | break; | |
219 | case 8: | |
220 | case 22: | |
221 | ide_cmd_write(&d->bus, 0, val); | |
222 | break; | |
223 | default: | |
224 | break; | |
225 | } | |
226 | } | |
227 | ||
c227f099 | 228 | static uint32_t pmac_ide_readb (void *opaque,target_phys_addr_t addr) |
b8842209 GH |
229 | { |
230 | uint8_t retval; | |
231 | MACIOIDEState *d = opaque; | |
232 | ||
233 | addr = (addr & 0xFFF) >> 4; | |
234 | switch (addr) { | |
235 | case 1 ... 7: | |
236 | retval = ide_ioport_read(&d->bus, addr); | |
237 | break; | |
238 | case 8: | |
239 | case 22: | |
240 | retval = ide_status_read(&d->bus, 0); | |
241 | break; | |
242 | default: | |
243 | retval = 0xFF; | |
244 | break; | |
245 | } | |
246 | return retval; | |
247 | } | |
248 | ||
249 | static void pmac_ide_writew (void *opaque, | |
c227f099 | 250 | target_phys_addr_t addr, uint32_t val) |
b8842209 GH |
251 | { |
252 | MACIOIDEState *d = opaque; | |
253 | ||
254 | addr = (addr & 0xFFF) >> 4; | |
b8842209 | 255 | val = bswap16(val); |
b8842209 GH |
256 | if (addr == 0) { |
257 | ide_data_writew(&d->bus, 0, val); | |
258 | } | |
259 | } | |
260 | ||
c227f099 | 261 | static uint32_t pmac_ide_readw (void *opaque,target_phys_addr_t addr) |
b8842209 GH |
262 | { |
263 | uint16_t retval; | |
264 | MACIOIDEState *d = opaque; | |
265 | ||
266 | addr = (addr & 0xFFF) >> 4; | |
267 | if (addr == 0) { | |
268 | retval = ide_data_readw(&d->bus, 0); | |
269 | } else { | |
270 | retval = 0xFFFF; | |
271 | } | |
b8842209 | 272 | retval = bswap16(retval); |
b8842209 GH |
273 | return retval; |
274 | } | |
275 | ||
276 | static void pmac_ide_writel (void *opaque, | |
c227f099 | 277 | target_phys_addr_t addr, uint32_t val) |
b8842209 GH |
278 | { |
279 | MACIOIDEState *d = opaque; | |
280 | ||
281 | addr = (addr & 0xFFF) >> 4; | |
b8842209 | 282 | val = bswap32(val); |
b8842209 GH |
283 | if (addr == 0) { |
284 | ide_data_writel(&d->bus, 0, val); | |
285 | } | |
286 | } | |
287 | ||
c227f099 | 288 | static uint32_t pmac_ide_readl (void *opaque,target_phys_addr_t addr) |
b8842209 GH |
289 | { |
290 | uint32_t retval; | |
291 | MACIOIDEState *d = opaque; | |
292 | ||
293 | addr = (addr & 0xFFF) >> 4; | |
294 | if (addr == 0) { | |
295 | retval = ide_data_readl(&d->bus, 0); | |
296 | } else { | |
297 | retval = 0xFFFFFFFF; | |
298 | } | |
b8842209 | 299 | retval = bswap32(retval); |
b8842209 GH |
300 | return retval; |
301 | } | |
302 | ||
23c5e4ca AK |
303 | static MemoryRegionOps pmac_ide_ops = { |
304 | .old_mmio = { | |
305 | .write = { | |
306 | pmac_ide_writeb, | |
307 | pmac_ide_writew, | |
308 | pmac_ide_writel, | |
309 | }, | |
310 | .read = { | |
311 | pmac_ide_readb, | |
312 | pmac_ide_readw, | |
313 | pmac_ide_readl, | |
314 | }, | |
315 | }, | |
316 | .endianness = DEVICE_NATIVE_ENDIAN, | |
b8842209 GH |
317 | }; |
318 | ||
44bfa332 JQ |
319 | static const VMStateDescription vmstate_pmac = { |
320 | .name = "ide", | |
321 | .version_id = 3, | |
322 | .minimum_version_id = 0, | |
323 | .minimum_version_id_old = 0, | |
324 | .fields = (VMStateField []) { | |
325 | VMSTATE_IDE_BUS(bus, MACIOIDEState), | |
326 | VMSTATE_IDE_DRIVES(bus.ifs, MACIOIDEState), | |
327 | VMSTATE_END_OF_LIST() | |
b8842209 | 328 | } |
44bfa332 | 329 | }; |
b8842209 GH |
330 | |
331 | static void pmac_ide_reset(void *opaque) | |
332 | { | |
333 | MACIOIDEState *d = opaque; | |
334 | ||
4a643563 | 335 | ide_bus_reset(&d->bus); |
b8842209 GH |
336 | } |
337 | ||
338 | /* hd_table must contain 4 block drivers */ | |
339 | /* PowerMac uses memory mapped registers, not I/O. Return the memory | |
340 | I/O index to access the ide. */ | |
23c5e4ca AK |
341 | MemoryRegion *pmac_ide_init (DriveInfo **hd_table, qemu_irq irq, |
342 | void *dbdma, int channel, qemu_irq dma_irq) | |
b8842209 GH |
343 | { |
344 | MACIOIDEState *d; | |
b8842209 | 345 | |
7267c094 | 346 | d = g_malloc0(sizeof(MACIOIDEState)); |
57234ee4 | 347 | ide_init2_with_non_qdev_drives(&d->bus, hd_table[0], hd_table[1], irq); |
b8842209 GH |
348 | |
349 | if (dbdma) | |
350 | DBDMA_register_channel(dbdma, channel, dma_irq, pmac_ide_transfer, pmac_ide_flush, d); | |
351 | ||
23c5e4ca | 352 | memory_region_init_io(&d->mem, &pmac_ide_ops, d, "pmac-ide", 0x1000); |
0be71e32 | 353 | vmstate_register(NULL, 0, &vmstate_pmac, d); |
b8842209 | 354 | qemu_register_reset(pmac_ide_reset, d); |
b8842209 | 355 | |
23c5e4ca | 356 | return &d->mem; |
b8842209 | 357 | } |