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3d2bf4a1 GH |
1 | /* |
2 | * QEMU IDE Emulation: mmio support (for embedded). | |
3 | * | |
4 | * Copyright (c) 2003 Fabrice Bellard | |
5 | * Copyright (c) 2006 Openedhand Ltd. | |
6 | * | |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
0b8fa32f | 25 | |
53239262 | 26 | #include "qemu/osdep.h" |
6b2578d6 | 27 | #include "hw/sysbus.h" |
d6454270 | 28 | #include "migration/vmstate.h" |
0b8fa32f | 29 | #include "qemu/module.h" |
9c17d615 | 30 | #include "sysemu/dma.h" |
59f2a787 | 31 | |
a9c94277 | 32 | #include "hw/ide/internal.h" |
a27bd6c7 | 33 | #include "hw/qdev-properties.h" |
db1015e9 | 34 | #include "qom/object.h" |
3d2bf4a1 GH |
35 | |
36 | /***********************************************************/ | |
37 | /* MMIO based ide port | |
38 | * This emulates IDE device connected directly to the CPU bus without | |
39 | * dedicated ide controller, which is often seen on embedded boards. | |
40 | */ | |
41 | ||
6b2578d6 | 42 | #define TYPE_MMIO_IDE "mmio-ide" |
db1015e9 | 43 | typedef struct MMIOIDEState MMIOState; |
8110fa1d EH |
44 | DECLARE_INSTANCE_CHECKER(MMIOState, MMIO_IDE, |
45 | TYPE_MMIO_IDE) | |
6b2578d6 | 46 | |
db1015e9 | 47 | struct MMIOIDEState { |
6b2578d6 AF |
48 | /*< private >*/ |
49 | SysBusDevice parent_obj; | |
50 | /*< public >*/ | |
51 | ||
0ce51e92 | 52 | IDEBus bus; |
6b2578d6 AF |
53 | |
54 | uint32_t shift; | |
55 | qemu_irq irq; | |
9d7f1b9a | 56 | MemoryRegion iomem1, iomem2; |
db1015e9 | 57 | }; |
3d2bf4a1 | 58 | |
6b2578d6 | 59 | static void mmio_ide_reset(DeviceState *dev) |
4a643563 | 60 | { |
6b2578d6 | 61 | MMIOState *s = MMIO_IDE(dev); |
4a643563 BS |
62 | |
63 | ide_bus_reset(&s->bus); | |
64 | } | |
65 | ||
a8170e5e | 66 | static uint64_t mmio_ide_read(void *opaque, hwaddr addr, |
9d7f1b9a | 67 | unsigned size) |
3d2bf4a1 | 68 | { |
18c0fb30 | 69 | MMIOState *s = opaque; |
3d2bf4a1 GH |
70 | addr >>= s->shift; |
71 | if (addr & 7) | |
0ce51e92 | 72 | return ide_ioport_read(&s->bus, addr); |
3d2bf4a1 | 73 | else |
0ce51e92 | 74 | return ide_data_readw(&s->bus, 0); |
3d2bf4a1 GH |
75 | } |
76 | ||
a8170e5e | 77 | static void mmio_ide_write(void *opaque, hwaddr addr, |
9d7f1b9a | 78 | uint64_t val, unsigned size) |
3d2bf4a1 | 79 | { |
18c0fb30 | 80 | MMIOState *s = opaque; |
3d2bf4a1 GH |
81 | addr >>= s->shift; |
82 | if (addr & 7) | |
0ce51e92 | 83 | ide_ioport_write(&s->bus, addr, val); |
3d2bf4a1 | 84 | else |
0ce51e92 | 85 | ide_data_writew(&s->bus, 0, val); |
3d2bf4a1 GH |
86 | } |
87 | ||
9d7f1b9a AK |
88 | static const MemoryRegionOps mmio_ide_ops = { |
89 | .read = mmio_ide_read, | |
90 | .write = mmio_ide_write, | |
1a7044bb | 91 | .endianness = DEVICE_LITTLE_ENDIAN, |
3d2bf4a1 GH |
92 | }; |
93 | ||
a8170e5e | 94 | static uint64_t mmio_ide_status_read(void *opaque, hwaddr addr, |
9d7f1b9a | 95 | unsigned size) |
3d2bf4a1 | 96 | { |
18c0fb30 | 97 | MMIOState *s= opaque; |
0ce51e92 | 98 | return ide_status_read(&s->bus, 0); |
3d2bf4a1 GH |
99 | } |
100 | ||
98d98912 JS |
101 | static void mmio_ide_ctrl_write(void *opaque, hwaddr addr, |
102 | uint64_t val, unsigned size) | |
3d2bf4a1 | 103 | { |
18c0fb30 | 104 | MMIOState *s = opaque; |
98d98912 | 105 | ide_ctrl_write(&s->bus, 0, val); |
3d2bf4a1 GH |
106 | } |
107 | ||
9d7f1b9a AK |
108 | static const MemoryRegionOps mmio_ide_cs_ops = { |
109 | .read = mmio_ide_status_read, | |
98d98912 | 110 | .write = mmio_ide_ctrl_write, |
1a7044bb | 111 | .endianness = DEVICE_LITTLE_ENDIAN, |
3d2bf4a1 GH |
112 | }; |
113 | ||
24daf35c JQ |
114 | static const VMStateDescription vmstate_ide_mmio = { |
115 | .name = "mmio-ide", | |
116 | .version_id = 3, | |
117 | .minimum_version_id = 0, | |
35d08458 | 118 | .fields = (VMStateField[]) { |
24daf35c JQ |
119 | VMSTATE_IDE_BUS(bus, MMIOState), |
120 | VMSTATE_IDE_DRIVES(bus.ifs, MMIOState), | |
121 | VMSTATE_END_OF_LIST() | |
122 | } | |
123 | }; | |
2bcbf7e4 | 124 | |
6b2578d6 | 125 | static void mmio_ide_realizefn(DeviceState *dev, Error **errp) |
3d2bf4a1 | 126 | { |
6b2578d6 AF |
127 | SysBusDevice *d = SYS_BUS_DEVICE(dev); |
128 | MMIOState *s = MMIO_IDE(dev); | |
3d2bf4a1 | 129 | |
6b2578d6 | 130 | ide_init2(&s->bus, s->irq); |
3d2bf4a1 | 131 | |
1437c94b | 132 | memory_region_init_io(&s->iomem1, OBJECT(s), &mmio_ide_ops, s, |
6b2578d6 | 133 | "ide-mmio.1", 16 << s->shift); |
1437c94b | 134 | memory_region_init_io(&s->iomem2, OBJECT(s), &mmio_ide_cs_ops, s, |
6b2578d6 AF |
135 | "ide-mmio.2", 2 << s->shift); |
136 | sysbus_init_mmio(d, &s->iomem1); | |
137 | sysbus_init_mmio(d, &s->iomem2); | |
138 | } | |
139 | ||
140 | static void mmio_ide_initfn(Object *obj) | |
141 | { | |
142 | SysBusDevice *d = SYS_BUS_DEVICE(obj); | |
143 | MMIOState *s = MMIO_IDE(obj); | |
144 | ||
82c74ac4 | 145 | ide_bus_init(&s->bus, sizeof(s->bus), DEVICE(obj), 0, 2); |
6b2578d6 AF |
146 | sysbus_init_irq(d, &s->irq); |
147 | } | |
148 | ||
149 | static Property mmio_ide_properties[] = { | |
150 | DEFINE_PROP_UINT32("shift", MMIOState, shift, 0), | |
151 | DEFINE_PROP_END_OF_LIST() | |
152 | }; | |
153 | ||
154 | static void mmio_ide_class_init(ObjectClass *oc, void *data) | |
155 | { | |
156 | DeviceClass *dc = DEVICE_CLASS(oc); | |
157 | ||
158 | dc->realize = mmio_ide_realizefn; | |
159 | dc->reset = mmio_ide_reset; | |
4f67d30b | 160 | device_class_set_props(dc, mmio_ide_properties); |
6b2578d6 AF |
161 | dc->vmsd = &vmstate_ide_mmio; |
162 | } | |
163 | ||
164 | static const TypeInfo mmio_ide_type_info = { | |
165 | .name = TYPE_MMIO_IDE, | |
166 | .parent = TYPE_SYS_BUS_DEVICE, | |
167 | .instance_size = sizeof(MMIOState), | |
168 | .instance_init = mmio_ide_initfn, | |
169 | .class_init = mmio_ide_class_init, | |
170 | }; | |
171 | ||
172 | static void mmio_ide_register_types(void) | |
173 | { | |
174 | type_register_static(&mmio_ide_type_info); | |
175 | } | |
176 | ||
177 | void mmio_ide_init_drives(DeviceState *dev, DriveInfo *hd0, DriveInfo *hd1) | |
178 | { | |
179 | MMIOState *s = MMIO_IDE(dev); | |
180 | ||
181 | if (hd0 != NULL) { | |
182 | ide_create_drive(&s->bus, 0, hd0); | |
183 | } | |
184 | if (hd1 != NULL) { | |
185 | ide_create_drive(&s->bus, 1, hd1); | |
186 | } | |
3d2bf4a1 GH |
187 | } |
188 | ||
6b2578d6 | 189 | type_init(mmio_ide_register_types) |