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Commit | Line | Data |
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4c3df0ec JQ |
1 | /* |
2 | * QEMU IDE Emulation: PCI PIIX3/4 support. | |
3 | * | |
4 | * Copyright (c) 2003 Fabrice Bellard | |
5 | * Copyright (c) 2006 Openedhand Ltd. | |
6 | * | |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
dfc65f1f | 25 | |
53239262 | 26 | #include "qemu/osdep.h" |
a9c94277 | 27 | #include "hw/pci/pci.h" |
d6454270 | 28 | #include "migration/vmstate.h" |
0b8fa32f | 29 | #include "qemu/module.h" |
b9fe8a7a | 30 | #include "sysemu/block-backend.h" |
78631611 | 31 | #include "sysemu/blockdev.h" |
9c17d615 | 32 | #include "sysemu/dma.h" |
4c3df0ec | 33 | |
a9c94277 | 34 | #include "hw/ide/pci.h" |
3eee2611 | 35 | #include "trace.h" |
4c3df0ec | 36 | |
a8170e5e | 37 | static uint64_t bmdma_read(void *opaque, hwaddr addr, unsigned size) |
4c3df0ec JQ |
38 | { |
39 | BMDMAState *bm = opaque; | |
40 | uint32_t val; | |
41 | ||
a9deb8c6 AK |
42 | if (size != 1) { |
43 | return ((uint64_t)1 << (size * 8)) - 1; | |
44 | } | |
45 | ||
4c3df0ec JQ |
46 | switch(addr & 3) { |
47 | case 0: | |
48 | val = bm->cmd; | |
49 | break; | |
50 | case 2: | |
51 | val = bm->status; | |
52 | break; | |
53 | default: | |
54 | val = 0xff; | |
55 | break; | |
56 | } | |
3eee2611 JS |
57 | |
58 | trace_bmdma_read(addr, val); | |
4c3df0ec JQ |
59 | return val; |
60 | } | |
61 | ||
a8170e5e | 62 | static void bmdma_write(void *opaque, hwaddr addr, |
a9deb8c6 | 63 | uint64_t val, unsigned size) |
4c3df0ec JQ |
64 | { |
65 | BMDMAState *bm = opaque; | |
a9deb8c6 AK |
66 | |
67 | if (size != 1) { | |
68 | return; | |
69 | } | |
70 | ||
3eee2611 JS |
71 | trace_bmdma_write(addr, val); |
72 | ||
4c3df0ec | 73 | switch(addr & 3) { |
a9deb8c6 | 74 | case 0: |
0ed8b6f6 BS |
75 | bmdma_cmd_writeb(bm, val); |
76 | break; | |
4c3df0ec JQ |
77 | case 2: |
78 | bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06); | |
79 | break; | |
80 | } | |
81 | } | |
82 | ||
a348f108 | 83 | static const MemoryRegionOps piix_bmdma_ops = { |
a9deb8c6 AK |
84 | .read = bmdma_read, |
85 | .write = bmdma_write, | |
86 | }; | |
87 | ||
88 | static void bmdma_setup_bar(PCIIDEState *d) | |
4c3df0ec | 89 | { |
4c3df0ec JQ |
90 | int i; |
91 | ||
1437c94b | 92 | memory_region_init(&d->bmdma_bar, OBJECT(d), "piix-bmdma-container", 16); |
4c3df0ec JQ |
93 | for(i = 0;i < 2; i++) { |
94 | BMDMAState *bm = &d->bmdma[i]; | |
4c3df0ec | 95 | |
1437c94b | 96 | memory_region_init_io(&bm->extra_io, OBJECT(d), &piix_bmdma_ops, bm, |
a9deb8c6 AK |
97 | "piix-bmdma", 4); |
98 | memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io); | |
1437c94b PB |
99 | memory_region_init_io(&bm->addr_ioport, OBJECT(d), |
100 | &bmdma_addr_ioport_ops, bm, "bmdma", 4); | |
a9deb8c6 | 101 | memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport); |
4c3df0ec JQ |
102 | } |
103 | } | |
104 | ||
ee358e91 | 105 | static void piix_ide_reset(DeviceState *dev) |
4c3df0ec | 106 | { |
ee358e91 | 107 | PCIIDEState *d = PCI_IDE(dev); |
f6c11d56 AF |
108 | PCIDevice *pd = PCI_DEVICE(d); |
109 | uint8_t *pci_conf = pd->config; | |
4c3df0ec JQ |
110 | int i; |
111 | ||
4a643563 BS |
112 | for (i = 0; i < 2; i++) { |
113 | ide_bus_reset(&d->bus[i]); | |
4a643563 | 114 | } |
4c3df0ec | 115 | |
1e68f8c4 MT |
116 | /* TODO: this is the default. do not override. */ |
117 | pci_conf[PCI_COMMAND] = 0x00; | |
118 | /* TODO: this is the default. do not override. */ | |
119 | pci_conf[PCI_COMMAND + 1] = 0x00; | |
120 | /* TODO: use pci_set_word */ | |
121 | pci_conf[PCI_STATUS] = PCI_STATUS_FAST_BACK; | |
122 | pci_conf[PCI_STATUS + 1] = PCI_STATUS_DEVSEL_MEDIUM >> 8; | |
4c3df0ec JQ |
123 | pci_conf[0x20] = 0x01; /* BMIBA: 20-23h */ |
124 | } | |
125 | ||
61d9d6b0 | 126 | static void pci_piix_init_ports(PCIIDEState *d) { |
4a91d3b3 | 127 | static const struct { |
61d9d6b0 SH |
128 | int iobase; |
129 | int iobase2; | |
130 | int isairq; | |
131 | } port_info[] = { | |
132 | {0x1f0, 0x3f6, 14}, | |
133 | {0x170, 0x376, 15}, | |
134 | }; | |
4a91d3b3 | 135 | int i; |
61d9d6b0 SH |
136 | |
137 | for (i = 0; i < 2; i++) { | |
c6baf942 | 138 | ide_bus_new(&d->bus[i], sizeof(d->bus[i]), DEVICE(d), i, 2); |
4a91d3b3 RH |
139 | ide_init_ioport(&d->bus[i], NULL, port_info[i].iobase, |
140 | port_info[i].iobase2); | |
48a18b3c | 141 | ide_init2(&d->bus[i], isa_get_irq(NULL, port_info[i].isairq)); |
61d9d6b0 | 142 | |
a9deb8c6 | 143 | bmdma_init(&d->bus[i], &d->bmdma[i], d); |
61d9d6b0 | 144 | d->bmdma[i].bus = &d->bus[i]; |
f878c916 | 145 | ide_register_restart_cb(&d->bus[i]); |
61d9d6b0 SH |
146 | } |
147 | } | |
148 | ||
9af21dbe | 149 | static void pci_piix_ide_realize(PCIDevice *dev, Error **errp) |
4c3df0ec | 150 | { |
f6c11d56 AF |
151 | PCIIDEState *d = PCI_IDE(dev); |
152 | uint8_t *pci_conf = dev->config; | |
4c3df0ec | 153 | |
1e68f8c4 | 154 | pci_conf[PCI_CLASS_PROG] = 0x80; // legacy ATA mode |
4c3df0ec | 155 | |
a9deb8c6 | 156 | bmdma_setup_bar(d); |
f6c11d56 | 157 | pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar); |
4c3df0ec | 158 | |
3cad405b | 159 | vmstate_register(VMSTATE_IF(dev), 0, &vmstate_ide_pci, d); |
4c3df0ec | 160 | |
61d9d6b0 | 161 | pci_piix_init_ports(d); |
4c3df0ec JQ |
162 | } |
163 | ||
ae4d2eb2 | 164 | int pci_piix3_xen_ide_unplug(DeviceState *dev, bool aux) |
679f4f8b | 165 | { |
679f4f8b | 166 | PCIIDEState *pci_ide; |
d4f9e806 | 167 | int i; |
6cd38783 | 168 | IDEDevice *idedev; |
045b1d4d AP |
169 | IDEBus *idebus; |
170 | BlockBackend *blk; | |
679f4f8b | 171 | |
f6c11d56 | 172 | pci_ide = PCI_IDE(dev); |
679f4f8b | 173 | |
ae4d2eb2 | 174 | for (i = aux ? 1 : 0; i < 4; i++) { |
045b1d4d AP |
175 | idebus = &pci_ide->bus[i / 2]; |
176 | blk = idebus->ifs[i % 2].blk; | |
49137bf6 | 177 | |
045b1d4d | 178 | if (blk && idebus->ifs[i % 2].drive_kind != IDE_CD) { |
6cd38783 | 179 | if (!(i % 2)) { |
045b1d4d | 180 | idedev = idebus->master; |
6cd38783 | 181 | } else { |
045b1d4d | 182 | idedev = idebus->slave; |
6cd38783 | 183 | } |
045b1d4d AP |
184 | |
185 | blk_drain(blk); | |
186 | blk_flush(blk); | |
187 | ||
188 | blk_detach_dev(blk, DEVICE(idedev)); | |
189 | idebus->ifs[i % 2].blk = NULL; | |
6cd38783 | 190 | idedev->conf.blk = NULL; |
d1fc684f | 191 | monitor_remove_blk(blk); |
b9fe8a7a | 192 | blk_unref(blk); |
679f4f8b SS |
193 | } |
194 | } | |
8e5c952b | 195 | qdev_reset_all(dev); |
679f4f8b SS |
196 | return 0; |
197 | } | |
198 | ||
f90c2bcd | 199 | static void pci_piix_ide_exitfn(PCIDevice *dev) |
a9deb8c6 | 200 | { |
f6c11d56 | 201 | PCIIDEState *d = PCI_IDE(dev); |
a9deb8c6 AK |
202 | unsigned i; |
203 | ||
204 | for (i = 0; i < 2; ++i) { | |
205 | memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io); | |
a9deb8c6 | 206 | memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport); |
a9deb8c6 | 207 | } |
a9deb8c6 AK |
208 | } |
209 | ||
df45d38f | 210 | /* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */ |
40021f08 AL |
211 | static void piix3_ide_class_init(ObjectClass *klass, void *data) |
212 | { | |
39bffca2 | 213 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
214 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
215 | ||
ee358e91 | 216 | dc->reset = piix_ide_reset; |
9af21dbe | 217 | k->realize = pci_piix_ide_realize; |
40021f08 AL |
218 | k->exit = pci_piix_ide_exitfn; |
219 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
220 | k->device_id = PCI_DEVICE_ID_INTEL_82371SB_1; | |
221 | k->class_id = PCI_CLASS_STORAGE_IDE; | |
125ee0ed | 222 | set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); |
2897ae02 | 223 | dc->hotpluggable = false; |
40021f08 AL |
224 | } |
225 | ||
8c43a6f0 | 226 | static const TypeInfo piix3_ide_info = { |
39bffca2 | 227 | .name = "piix3-ide", |
f6c11d56 | 228 | .parent = TYPE_PCI_IDE, |
39bffca2 | 229 | .class_init = piix3_ide_class_init, |
e855761c AL |
230 | }; |
231 | ||
8c43a6f0 | 232 | static const TypeInfo piix3_ide_xen_info = { |
39bffca2 | 233 | .name = "piix3-ide-xen", |
f6c11d56 | 234 | .parent = TYPE_PCI_IDE, |
0f844582 | 235 | .class_init = piix3_ide_class_init, |
e855761c AL |
236 | }; |
237 | ||
f42b65b8 | 238 | /* NOTE: for the PIIX4, the IRQs and IOports are hardcoded */ |
40021f08 AL |
239 | static void piix4_ide_class_init(ObjectClass *klass, void *data) |
240 | { | |
39bffca2 | 241 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
242 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
243 | ||
ee358e91 | 244 | dc->reset = piix_ide_reset; |
9af21dbe | 245 | k->realize = pci_piix_ide_realize; |
40021f08 AL |
246 | k->exit = pci_piix_ide_exitfn; |
247 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
248 | k->device_id = PCI_DEVICE_ID_INTEL_82371AB; | |
249 | k->class_id = PCI_CLASS_STORAGE_IDE; | |
125ee0ed | 250 | set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); |
2897ae02 | 251 | dc->hotpluggable = false; |
40021f08 AL |
252 | } |
253 | ||
8c43a6f0 | 254 | static const TypeInfo piix4_ide_info = { |
39bffca2 | 255 | .name = "piix4-ide", |
f6c11d56 | 256 | .parent = TYPE_PCI_IDE, |
39bffca2 | 257 | .class_init = piix4_ide_class_init, |
4c3df0ec JQ |
258 | }; |
259 | ||
83f7d43a | 260 | static void piix_ide_register_types(void) |
4c3df0ec | 261 | { |
39bffca2 AL |
262 | type_register_static(&piix3_ide_info); |
263 | type_register_static(&piix3_ide_xen_info); | |
264 | type_register_static(&piix4_ide_info); | |
4c3df0ec | 265 | } |
83f7d43a AF |
266 | |
267 | type_init(piix_ide_register_types) |