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Commit | Line | Data |
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4c3df0ec JQ |
1 | /* |
2 | * QEMU IDE Emulation: PCI PIIX3/4 support. | |
3 | * | |
4 | * Copyright (c) 2003 Fabrice Bellard | |
5 | * Copyright (c) 2006 Openedhand Ltd. | |
6 | * | |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
4851a986 LK |
24 | * |
25 | * References: | |
26 | * [1] 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR, | |
27 | * 290550-002, Intel Corporation, April 1997. | |
4c3df0ec | 28 | */ |
dfc65f1f | 29 | |
53239262 | 30 | #include "qemu/osdep.h" |
9405d87b | 31 | #include "qapi/error.h" |
caa91462 | 32 | #include "hw/pci/pci.h" |
bb2e9b1d | 33 | #include "hw/ide/piix.h" |
a9c94277 | 34 | #include "hw/ide/pci.h" |
3eee2611 | 35 | #include "trace.h" |
4c3df0ec | 36 | |
a8170e5e | 37 | static uint64_t bmdma_read(void *opaque, hwaddr addr, unsigned size) |
4c3df0ec JQ |
38 | { |
39 | BMDMAState *bm = opaque; | |
40 | uint32_t val; | |
41 | ||
a9deb8c6 AK |
42 | if (size != 1) { |
43 | return ((uint64_t)1 << (size * 8)) - 1; | |
44 | } | |
45 | ||
4c3df0ec JQ |
46 | switch(addr & 3) { |
47 | case 0: | |
48 | val = bm->cmd; | |
49 | break; | |
50 | case 2: | |
51 | val = bm->status; | |
52 | break; | |
53 | default: | |
54 | val = 0xff; | |
55 | break; | |
56 | } | |
3eee2611 JS |
57 | |
58 | trace_bmdma_read(addr, val); | |
4c3df0ec JQ |
59 | return val; |
60 | } | |
61 | ||
a8170e5e | 62 | static void bmdma_write(void *opaque, hwaddr addr, |
a9deb8c6 | 63 | uint64_t val, unsigned size) |
4c3df0ec JQ |
64 | { |
65 | BMDMAState *bm = opaque; | |
a9deb8c6 AK |
66 | |
67 | if (size != 1) { | |
68 | return; | |
69 | } | |
70 | ||
3eee2611 JS |
71 | trace_bmdma_write(addr, val); |
72 | ||
4c3df0ec | 73 | switch(addr & 3) { |
a9deb8c6 | 74 | case 0: |
0ed8b6f6 BS |
75 | bmdma_cmd_writeb(bm, val); |
76 | break; | |
4c3df0ec | 77 | case 2: |
5fe24213 | 78 | bmdma_status_writeb(bm, val); |
4c3df0ec JQ |
79 | break; |
80 | } | |
81 | } | |
82 | ||
a348f108 | 83 | static const MemoryRegionOps piix_bmdma_ops = { |
a9deb8c6 AK |
84 | .read = bmdma_read, |
85 | .write = bmdma_write, | |
86 | }; | |
87 | ||
88 | static void bmdma_setup_bar(PCIIDEState *d) | |
4c3df0ec | 89 | { |
4c3df0ec JQ |
90 | int i; |
91 | ||
1437c94b | 92 | memory_region_init(&d->bmdma_bar, OBJECT(d), "piix-bmdma-container", 16); |
4c3df0ec JQ |
93 | for(i = 0;i < 2; i++) { |
94 | BMDMAState *bm = &d->bmdma[i]; | |
4c3df0ec | 95 | |
1437c94b | 96 | memory_region_init_io(&bm->extra_io, OBJECT(d), &piix_bmdma_ops, bm, |
a9deb8c6 AK |
97 | "piix-bmdma", 4); |
98 | memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io); | |
1437c94b PB |
99 | memory_region_init_io(&bm->addr_ioport, OBJECT(d), |
100 | &bmdma_addr_ioport_ops, bm, "bmdma", 4); | |
a9deb8c6 | 101 | memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport); |
4c3df0ec JQ |
102 | } |
103 | } | |
104 | ||
ee358e91 | 105 | static void piix_ide_reset(DeviceState *dev) |
4c3df0ec | 106 | { |
ee358e91 | 107 | PCIIDEState *d = PCI_IDE(dev); |
f6c11d56 AF |
108 | PCIDevice *pd = PCI_DEVICE(d); |
109 | uint8_t *pci_conf = pd->config; | |
4c3df0ec JQ |
110 | int i; |
111 | ||
4a643563 BS |
112 | for (i = 0; i < 2; i++) { |
113 | ide_bus_reset(&d->bus[i]); | |
4a643563 | 114 | } |
4c3df0ec | 115 | |
4851a986 LK |
116 | /* PCI command register default value (0000h) per [1, p.48]. */ |
117 | pci_set_word(pci_conf + PCI_COMMAND, 0x0000); | |
118 | pci_set_word(pci_conf + PCI_STATUS, | |
119 | PCI_STATUS_DEVSEL_MEDIUM | PCI_STATUS_FAST_BACK); | |
230dfd92 | 120 | pci_set_long(pci_conf + 0x20, 0x1); /* BMIBA: 20-23h */ |
4c3df0ec JQ |
121 | } |
122 | ||
533580d7 | 123 | static bool pci_piix_init_bus(PCIIDEState *d, unsigned i, Error **errp) |
9405d87b | 124 | { |
4a91d3b3 | 125 | static const struct { |
61d9d6b0 SH |
126 | int iobase; |
127 | int iobase2; | |
128 | int isairq; | |
129 | } port_info[] = { | |
130 | {0x1f0, 0x3f6, 14}, | |
131 | {0x170, 0x376, 15}, | |
132 | }; | |
533580d7 PMD |
133 | int ret; |
134 | ||
135 | ide_bus_init(&d->bus[i], sizeof(d->bus[i]), DEVICE(d), i, 2); | |
136 | ret = ide_init_ioport(&d->bus[i], NULL, port_info[i].iobase, | |
137 | port_info[i].iobase2); | |
138 | if (ret) { | |
139 | error_setg_errno(errp, -ret, "Failed to realize %s port %u", | |
140 | object_get_typename(OBJECT(d)), i); | |
141 | return false; | |
61d9d6b0 | 142 | } |
533580d7 PMD |
143 | ide_bus_init_output_irq(&d->bus[i], isa_get_irq(NULL, port_info[i].isairq)); |
144 | ||
145 | bmdma_init(&d->bus[i], &d->bmdma[i], d); | |
533580d7 | 146 | ide_bus_register_restart_cb(&d->bus[i]); |
9405d87b | 147 | |
511aa9f9 | 148 | return true; |
61d9d6b0 SH |
149 | } |
150 | ||
9af21dbe | 151 | static void pci_piix_ide_realize(PCIDevice *dev, Error **errp) |
4c3df0ec | 152 | { |
f6c11d56 AF |
153 | PCIIDEState *d = PCI_IDE(dev); |
154 | uint8_t *pci_conf = dev->config; | |
4c3df0ec | 155 | |
1e68f8c4 | 156 | pci_conf[PCI_CLASS_PROG] = 0x80; // legacy ATA mode |
4c3df0ec | 157 | |
a9deb8c6 | 158 | bmdma_setup_bar(d); |
f6c11d56 | 159 | pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar); |
4c3df0ec | 160 | |
533580d7 PMD |
161 | for (unsigned i = 0; i < 2; i++) { |
162 | if (!pci_piix_init_bus(d, i, errp)) { | |
163 | return; | |
164 | } | |
9405d87b | 165 | } |
4c3df0ec JQ |
166 | } |
167 | ||
f90c2bcd | 168 | static void pci_piix_ide_exitfn(PCIDevice *dev) |
a9deb8c6 | 169 | { |
f6c11d56 | 170 | PCIIDEState *d = PCI_IDE(dev); |
a9deb8c6 AK |
171 | unsigned i; |
172 | ||
173 | for (i = 0; i < 2; ++i) { | |
174 | memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io); | |
a9deb8c6 | 175 | memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport); |
a9deb8c6 | 176 | } |
a9deb8c6 AK |
177 | } |
178 | ||
df45d38f | 179 | /* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */ |
40021f08 AL |
180 | static void piix3_ide_class_init(ObjectClass *klass, void *data) |
181 | { | |
39bffca2 | 182 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
183 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
184 | ||
ee358e91 | 185 | dc->reset = piix_ide_reset; |
752dfff5 | 186 | dc->vmsd = &vmstate_ide_pci; |
9af21dbe | 187 | k->realize = pci_piix_ide_realize; |
40021f08 AL |
188 | k->exit = pci_piix_ide_exitfn; |
189 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
190 | k->device_id = PCI_DEVICE_ID_INTEL_82371SB_1; | |
191 | k->class_id = PCI_CLASS_STORAGE_IDE; | |
125ee0ed | 192 | set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); |
2897ae02 | 193 | dc->hotpluggable = false; |
40021f08 AL |
194 | } |
195 | ||
8c43a6f0 | 196 | static const TypeInfo piix3_ide_info = { |
bb2e9b1d | 197 | .name = TYPE_PIIX3_IDE, |
f6c11d56 | 198 | .parent = TYPE_PCI_IDE, |
39bffca2 | 199 | .class_init = piix3_ide_class_init, |
e855761c AL |
200 | }; |
201 | ||
f42b65b8 | 202 | /* NOTE: for the PIIX4, the IRQs and IOports are hardcoded */ |
40021f08 AL |
203 | static void piix4_ide_class_init(ObjectClass *klass, void *data) |
204 | { | |
39bffca2 | 205 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
206 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
207 | ||
ee358e91 | 208 | dc->reset = piix_ide_reset; |
752dfff5 | 209 | dc->vmsd = &vmstate_ide_pci; |
9af21dbe | 210 | k->realize = pci_piix_ide_realize; |
40021f08 AL |
211 | k->exit = pci_piix_ide_exitfn; |
212 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
213 | k->device_id = PCI_DEVICE_ID_INTEL_82371AB; | |
214 | k->class_id = PCI_CLASS_STORAGE_IDE; | |
125ee0ed | 215 | set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); |
2897ae02 | 216 | dc->hotpluggable = false; |
40021f08 AL |
217 | } |
218 | ||
8c43a6f0 | 219 | static const TypeInfo piix4_ide_info = { |
bb2e9b1d | 220 | .name = TYPE_PIIX4_IDE, |
f6c11d56 | 221 | .parent = TYPE_PCI_IDE, |
39bffca2 | 222 | .class_init = piix4_ide_class_init, |
4c3df0ec JQ |
223 | }; |
224 | ||
83f7d43a | 225 | static void piix_ide_register_types(void) |
4c3df0ec | 226 | { |
39bffca2 | 227 | type_register_static(&piix3_ide_info); |
39bffca2 | 228 | type_register_static(&piix4_ide_info); |
4c3df0ec | 229 | } |
83f7d43a AF |
230 | |
231 | type_init(piix_ide_register_types) |