[mirror_qemu.git] / hw / ide / piix.c

/*
 * QEMU IDE Emulation: PCI PIIX3/4 support.
 *
 * Copyright (c) 2003 Fabrice Bellard
 * Copyright (c) 2006 Openedhand Ltd.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include <hw/hw.h>
#include <hw/pc.h>
#include <hw/pci.h>
#include <hw/isa.h>
#include "block.h"
#include "block_int.h"
#include "sysemu.h"
#include "dma.h"

#include <hw/ide/pci.h>

static uint64_t bmdma_read(void *opaque, target_phys_addr_t addr, unsigned size)
{
    BMDMAState *bm = opaque;
    uint32_t val;

    if (size != 1) {
        return ((uint64_t)1 << (size * 8)) - 1;
    }

    switch(addr & 3) {
    case 0:
        val = bm->cmd;
        break;
    case 2:
        val = bm->status;
        break;
    default:
        val = 0xff;
        break;
    }
#ifdef DEBUG_IDE
    printf("bmdma: readb 0x%02x : 0x%02x\n", addr, val);
#endif
    return val;
}

static void bmdma_write(void *opaque, target_phys_addr_t addr,
                        uint64_t val, unsigned size)
{
    BMDMAState *bm = opaque;

    if (size != 1) {
        return;
    }

#ifdef DEBUG_IDE
    printf("bmdma: writeb 0x%02x : 0x%02x\n", addr, val);
#endif
    switch(addr & 3) {
    case 0:
        return bmdma_cmd_writeb(bm, val);
    case 2:
        bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
        break;
    }
}

static MemoryRegionOps piix_bmdma_ops = {
    .read = bmdma_read,
    .write = bmdma_write,
};

static void bmdma_setup_bar(PCIIDEState *d)
{
    int i;

    memory_region_init(&d->bmdma_bar, "piix-bmdma-container", 16);
    for(i = 0;i < 2; i++) {
        BMDMAState *bm = &d->bmdma[i];

        memory_region_init_io(&bm->extra_io, &piix_bmdma_ops, bm,
                              "piix-bmdma", 4);
        memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io);
        memory_region_init_io(&bm->addr_ioport, &bmdma_addr_ioport_ops, bm,
                              "bmdma", 4);
        memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport);
    }
}

static void piix3_reset(void *opaque)
{
    PCIIDEState *d = opaque;
    uint8_t *pci_conf = d->dev.config;
    int i;

    for (i = 0; i < 2; i++) {
        ide_bus_reset(&d->bus[i]);
    }

    /* TODO: this is the default. do not override. */
    pci_conf[PCI_COMMAND] = 0x00;
    /* TODO: this is the default. do not override. */
    pci_conf[PCI_COMMAND + 1] = 0x00;
    /* TODO: use pci_set_word */
    pci_conf[PCI_STATUS] = PCI_STATUS_FAST_BACK;
    pci_conf[PCI_STATUS + 1] = PCI_STATUS_DEVSEL_MEDIUM >> 8;
    pci_conf[0x20] = 0x01; /* BMIBA: 20-23h */
}

static void pci_piix_init_ports(PCIIDEState *d) {
    int i;
    struct {
        int iobase;
        int iobase2;
        int isairq;
    } port_info[] = {
        {0x1f0, 0x3f6, 14},
        {0x170, 0x376, 15},
    };

    for (i = 0; i < 2; i++) {
        ide_bus_new(&d->bus[i], &d->dev.qdev, i);
        ide_init_ioport(&d->bus[i], port_info[i].iobase, port_info[i].iobase2);
        ide_init2(&d->bus[i], isa_get_irq(port_info[i].isairq));

        bmdma_init(&d->bus[i], &d->bmdma[i], d);
        d->bmdma[i].bus = &d->bus[i];
        qemu_add_vm_change_state_handler(d->bus[i].dma->ops->restart_cb,
                                         &d->bmdma[i].dma);
    }
}

static int pci_piix_ide_initfn(PCIDevice *dev)
{
    PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
    uint8_t *pci_conf = d->dev.config;

    pci_conf[PCI_CLASS_PROG] = 0x80; // legacy ATA mode

    qemu_register_reset(piix3_reset, d);

    bmdma_setup_bar(d);
    pci_register_bar(&d->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);

    vmstate_register(&d->dev.qdev, 0, &vmstate_ide_pci, d);

    pci_piix_init_ports(d);

    return 0;
}

static int pci_piix3_xen_ide_unplug(DeviceState *dev)
{
    PCIDevice *pci_dev;
    PCIIDEState *pci_ide;
    DriveInfo *di;
    int i = 0;

    pci_dev = DO_UPCAST(PCIDevice, qdev, dev);
    pci_ide = DO_UPCAST(PCIIDEState, dev, pci_dev);

    for (; i < 3; i++) {
        di = drive_get_by_index(IF_IDE, i);
        if (di != NULL && di->bdrv != NULL && !di->bdrv->removable) {
            DeviceState *ds = bdrv_get_attached(di->bdrv);
            if (ds) {
                bdrv_detach(di->bdrv, ds);
            }
            bdrv_close(di->bdrv);
            pci_ide->bus[di->bus].ifs[di->unit].bs = NULL;
            drive_put_ref(di);
        }
    }
    qdev_reset_all(&(pci_ide->dev.qdev));
    return 0;
}

PCIDevice *pci_piix3_xen_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
{
    PCIDevice *dev;

    dev = pci_create_simple(bus, devfn, "piix3-ide-xen");
    dev->qdev.info->unplug = pci_piix3_xen_ide_unplug;
    pci_ide_create_devs(dev, hd_table);
    return dev;
}

static int pci_piix_ide_exitfn(PCIDevice *dev)
{
    PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
    unsigned i;

    for (i = 0; i < 2; ++i) {
        memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io);
        memory_region_destroy(&d->bmdma[i].extra_io);
        memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport);
        memory_region_destroy(&d->bmdma[i].addr_ioport);
    }
    memory_region_destroy(&d->bmdma_bar);

    return 0;
}

/* hd_table must contain 4 block drivers */
/* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */
PCIDevice *pci_piix3_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
{
    PCIDevice *dev;

    dev = pci_create_simple(bus, devfn, "piix3-ide");
    pci_ide_create_devs(dev, hd_table);
    return dev;
}

/* hd_table must contain 4 block drivers */
/* NOTE: for the PIIX4, the IRQs and IOports are hardcoded */
PCIDevice *pci_piix4_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
{
    PCIDevice *dev;

    dev = pci_create_simple(bus, devfn, "piix4-ide");
    pci_ide_create_devs(dev, hd_table);
    return dev;
}

static PCIDeviceInfo piix_ide_info[] = {
    {
        .qdev.name    = "piix3-ide",
        .qdev.size    = sizeof(PCIIDEState),
        .qdev.no_user = 1,
        .no_hotplug   = 1,
        .init         = pci_piix_ide_initfn,
        .exit         = pci_piix_ide_exitfn,
        .vendor_id    = PCI_VENDOR_ID_INTEL,
        .device_id    = PCI_DEVICE_ID_INTEL_82371SB_1,
        .class_id     = PCI_CLASS_STORAGE_IDE,
    },{
        .qdev.name    = "piix3-ide-xen",
        .qdev.size    = sizeof(PCIIDEState),
        .qdev.no_user = 1,
        .init         = pci_piix_ide_initfn,
        .vendor_id    = PCI_VENDOR_ID_INTEL,
        .device_id    = PCI_DEVICE_ID_INTEL_82371SB_1,
        .class_id     = PCI_CLASS_STORAGE_IDE,
    },{
        .qdev.name    = "piix4-ide",
        .qdev.size    = sizeof(PCIIDEState),
        .qdev.no_user = 1,
        .no_hotplug   = 1,
        .init         = pci_piix_ide_initfn,
        .exit         = pci_piix_ide_exitfn,
        .vendor_id    = PCI_VENDOR_ID_INTEL,
        .device_id    = PCI_DEVICE_ID_INTEL_82371AB,
        .class_id     = PCI_CLASS_STORAGE_IDE,
    },{
        /* end of list */
    }
};

static void piix_ide_register(void)
{
    pci_qdev_register_many(piix_ide_info);
}
device_init(piix_ide_register);
Commit	Line	Data
4c3df0ec JQ	1	/*
	2	* QEMU IDE Emulation: PCI PIIX3/4 support.
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	* Copyright (c) 2006 Openedhand Ltd.
	6	*
	7	* Permission is hereby granted, free of charge, to any person obtaining a copy
	8	* of this software and associated documentation files (the "Software"), to deal
	9	* in the Software without restriction, including without limitation the rights
	10	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	11	* copies of the Software, and to permit persons to whom the Software is
	12	* furnished to do so, subject to the following conditions:
	13	*
	14	* The above copyright notice and this permission notice shall be included in
	15	* all copies or substantial portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	22	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	23	* THE SOFTWARE.
	24	*/
	25	#include <hw/hw.h>
	26	#include <hw/pc.h>
	27	#include <hw/pci.h>
	28	#include <hw/isa.h>
	29	#include "block.h"
	30	#include "block_int.h"
	31	#include "sysemu.h"
	32	#include "dma.h"
	33
	34	#include <hw/ide/pci.h>
	35
a9deb8c6	36	static uint64_t bmdma_read(void *opaque, target_phys_addr_t addr, unsigned size)
4c3df0ec JQ	37	{
	38	BMDMAState *bm = opaque;
	39	uint32_t val;
	40
a9deb8c6 AK	41	if (size != 1) {
	42	return ((uint64_t)1 << (size * 8)) - 1;
	43	}
	44
4c3df0ec JQ	45	switch(addr & 3) {
	46	case 0:
	47	val = bm->cmd;
	48	break;
	49	case 2:
	50	val = bm->status;
	51	break;
	52	default:
	53	val = 0xff;
	54	break;
	55	}
	56	#ifdef DEBUG_IDE
	57	printf("bmdma: readb 0x%02x : 0x%02x\n", addr, val);
	58	#endif
	59	return val;
	60	}
	61
a9deb8c6 AK	62	static void bmdma_write(void *opaque, target_phys_addr_t addr,
a9deb8c6 AK	63	uint64_t val, unsigned size)
4c3df0ec JQ	64	{
4c3df0ec JQ	65	BMDMAState *bm = opaque;
a9deb8c6 AK	66
	67	if (size != 1) {
	68	return;
	69	}
	70
4c3df0ec JQ	71	#ifdef DEBUG_IDE
	72	printf("bmdma: writeb 0x%02x : 0x%02x\n", addr, val);
	73	#endif
	74	switch(addr & 3) {
a9deb8c6 AK	75	case 0:
a9deb8c6 AK	76	return bmdma_cmd_writeb(bm, val);
4c3df0ec JQ	77	case 2:
	78	bm->status = (val & 0x60) \| (bm->status & 1) \| (bm->status & ~val & 0x06);
	79	break;
	80	}
	81	}
	82
a9deb8c6 AK	83	static MemoryRegionOps piix_bmdma_ops = {
	84	.read = bmdma_read,
	85	.write = bmdma_write,
	86	};
	87
	88	static void bmdma_setup_bar(PCIIDEState *d)
4c3df0ec	89	{
4c3df0ec JQ	90	int i;
4c3df0ec JQ	91
a9deb8c6	92	memory_region_init(&d->bmdma_bar, "piix-bmdma-container", 16);
4c3df0ec JQ	93	for(i = 0;i < 2; i++) {
4c3df0ec JQ	94	BMDMAState *bm = &d->bmdma[i];
4c3df0ec	95
a9deb8c6 AK	96	memory_region_init_io(&bm->extra_io, &piix_bmdma_ops, bm,
	97	"piix-bmdma", 4);
	98	memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io);
	99	memory_region_init_io(&bm->addr_ioport, &bmdma_addr_ioport_ops, bm,
	100	"bmdma", 4);
	101	memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport);
4c3df0ec JQ	102	}
	103	}
	104
	105	static void piix3_reset(void *opaque)
	106	{
	107	PCIIDEState *d = opaque;
	108	uint8_t *pci_conf = d->dev.config;
	109	int i;
	110
4a643563 BS	111	for (i = 0; i < 2; i++) {
4a643563 BS	112	ide_bus_reset(&d->bus[i]);
4a643563	113	}
4c3df0ec	114
1e68f8c4 MT	115	/* TODO: this is the default. do not override. */
	116	pci_conf[PCI_COMMAND] = 0x00;
	117	/* TODO: this is the default. do not override. */
	118	pci_conf[PCI_COMMAND + 1] = 0x00;
	119	/* TODO: use pci_set_word */
	120	pci_conf[PCI_STATUS] = PCI_STATUS_FAST_BACK;
	121	pci_conf[PCI_STATUS + 1] = PCI_STATUS_DEVSEL_MEDIUM >> 8;
4c3df0ec JQ	122	pci_conf[0x20] = 0x01; /* BMIBA: 20-23h */
	123	}
	124
61d9d6b0 SH	125	static void pci_piix_init_ports(PCIIDEState *d) {
	126	int i;
	127	struct {
	128	int iobase;
	129	int iobase2;
	130	int isairq;
	131	} port_info[] = {
	132	{0x1f0, 0x3f6, 14},
	133	{0x170, 0x376, 15},
	134	};
	135
	136	for (i = 0; i < 2; i++) {
	137	ide_bus_new(&d->bus[i], &d->dev.qdev, i);
	138	ide_init_ioport(&d->bus[i], port_info[i].iobase, port_info[i].iobase2);
ee951a37	139	ide_init2(&d->bus[i], isa_get_irq(port_info[i].isairq));
61d9d6b0	140
a9deb8c6	141	bmdma_init(&d->bus[i], &d->bmdma[i], d);
61d9d6b0 SH	142	d->bmdma[i].bus = &d->bus[i];
	143	qemu_add_vm_change_state_handler(d->bus[i].dma->ops->restart_cb,
	144	&d->bmdma[i].dma);
	145	}
	146	}
	147
25f8e2f5	148	static int pci_piix_ide_initfn(PCIDevice *dev)
4c3df0ec	149	{
25f8e2f5	150	PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
4c3df0ec JQ	151	uint8_t *pci_conf = d->dev.config;
4c3df0ec JQ	152
1e68f8c4	153	pci_conf[PCI_CLASS_PROG] = 0x80; // legacy ATA mode
4c3df0ec JQ	154
4c3df0ec JQ	155	qemu_register_reset(piix3_reset, d);
4c3df0ec	156
a9deb8c6	157	bmdma_setup_bar(d);
e824b2cc	158	pci_register_bar(&d->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);
4c3df0ec	159
0be71e32	160	vmstate_register(&d->dev.qdev, 0, &vmstate_ide_pci, d);
4c3df0ec	161
61d9d6b0	162	pci_piix_init_ports(d);
4c3df0ec	163
4c3df0ec JQ	164	return 0;
	165	}
	166
679f4f8b SS	167	static int pci_piix3_xen_ide_unplug(DeviceState *dev)
	168	{
	169	PCIDevice *pci_dev;
	170	PCIIDEState *pci_ide;
	171	DriveInfo *di;
	172	int i = 0;
	173
	174	pci_dev = DO_UPCAST(PCIDevice, qdev, dev);
	175	pci_ide = DO_UPCAST(PCIIDEState, dev, pci_dev);
	176
	177	for (; i < 3; i++) {
	178	di = drive_get_by_index(IF_IDE, i);
	179	if (di != NULL && di->bdrv != NULL && !di->bdrv->removable) {
	180	DeviceState *ds = bdrv_get_attached(di->bdrv);
	181	if (ds) {
	182	bdrv_detach(di->bdrv, ds);
	183	}
	184	bdrv_close(di->bdrv);
	185	pci_ide->bus[di->bus].ifs[di->unit].bs = NULL;
	186	drive_put_ref(di);
	187	}
	188	}
	189	qdev_reset_all(&(pci_ide->dev.qdev));
	190	return 0;
	191	}
	192
	193	PCIDevice pci_piix3_xen_ide_init(PCIBus bus, DriveInfo **hd_table, int devfn)
	194	{
	195	PCIDevice *dev;
	196
	197	dev = pci_create_simple(bus, devfn, "piix3-ide-xen");
	198	dev->qdev.info->unplug = pci_piix3_xen_ide_unplug;
	199	pci_ide_create_devs(dev, hd_table);
	200	return dev;
	201	}
	202
a9deb8c6 AK	203	static int pci_piix_ide_exitfn(PCIDevice *dev)
	204	{
	205	PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
	206	unsigned i;
	207
	208	for (i = 0; i < 2; ++i) {
	209	memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io);
	210	memory_region_destroy(&d->bmdma[i].extra_io);
	211	memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport);
	212	memory_region_destroy(&d->bmdma[i].addr_ioport);
	213	}
	214	memory_region_destroy(&d->bmdma_bar);
	215
	216	return 0;
	217	}
	218
4c3df0ec JQ	219	/* hd_table must contain 4 block drivers */
4c3df0ec JQ	220	/* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */
57c88866	221	PCIDevice pci_piix3_ide_init(PCIBus bus, DriveInfo **hd_table, int devfn)
4c3df0ec JQ	222	{
	223	PCIDevice *dev;
	224
556cd098	225	dev = pci_create_simple(bus, devfn, "piix3-ide");
4c3df0ec	226	pci_ide_create_devs(dev, hd_table);
57c88866	227	return dev;
4c3df0ec JQ	228	}
	229
	230	/* hd_table must contain 4 block drivers */
	231	/* NOTE: for the PIIX4, the IRQs and IOports are hardcoded */
57c88866	232	PCIDevice pci_piix4_ide_init(PCIBus bus, DriveInfo **hd_table, int devfn)
4c3df0ec JQ	233	{
	234	PCIDevice *dev;
	235
556cd098	236	dev = pci_create_simple(bus, devfn, "piix4-ide");
4c3df0ec	237	pci_ide_create_devs(dev, hd_table);
57c88866	238	return dev;
4c3df0ec JQ	239	}
	240
	241	static PCIDeviceInfo piix_ide_info[] = {
	242	{
556cd098	243	.qdev.name = "piix3-ide",
4c3df0ec	244	.qdev.size = sizeof(PCIIDEState),
39a51dfd	245	.qdev.no_user = 1,
0965f12d	246	.no_hotplug = 1,
25f8e2f5	247	.init = pci_piix_ide_initfn,
a9deb8c6	248	.exit = pci_piix_ide_exitfn,
25f8e2f5 IY	249	.vendor_id = PCI_VENDOR_ID_INTEL,
	250	.device_id = PCI_DEVICE_ID_INTEL_82371SB_1,
	251	.class_id = PCI_CLASS_STORAGE_IDE,
679f4f8b SS	252	},{
	253	.qdev.name = "piix3-ide-xen",
	254	.qdev.size = sizeof(PCIIDEState),
	255	.qdev.no_user = 1,
	256	.init = pci_piix_ide_initfn,
	257	.vendor_id = PCI_VENDOR_ID_INTEL,
	258	.device_id = PCI_DEVICE_ID_INTEL_82371SB_1,
	259	.class_id = PCI_CLASS_STORAGE_IDE,
4c3df0ec	260	},{
556cd098	261	.qdev.name = "piix4-ide",
4c3df0ec	262	.qdev.size = sizeof(PCIIDEState),
39a51dfd	263	.qdev.no_user = 1,
0965f12d	264	.no_hotplug = 1,
25f8e2f5	265	.init = pci_piix_ide_initfn,
a9deb8c6	266	.exit = pci_piix_ide_exitfn,
25f8e2f5 IY	267	.vendor_id = PCI_VENDOR_ID_INTEL,
	268	.device_id = PCI_DEVICE_ID_INTEL_82371AB,
	269	.class_id = PCI_CLASS_STORAGE_IDE,
4c3df0ec JQ	270	},{
	271	/* end of list */
	272	}
	273	};
	274
	275	static void piix_ide_register(void)
	276	{
	277	pci_qdev_register_many(piix_ide_info);
	278	}
	279	device_init(piix_ide_register);