[mirror_qemu.git] / hw / ide / piix.c

/*
 * QEMU IDE Emulation: PCI PIIX3/4 support.
 *
 * Copyright (c) 2003 Fabrice Bellard
 * Copyright (c) 2006 Openedhand Ltd.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include <hw/hw.h>
#include <hw/pc.h>
#include <hw/pci.h>
#include <hw/isa.h>
#include "block.h"
#include "sysemu.h"
#include "dma.h"

#include <hw/ide/pci.h>

static uint64_t bmdma_read(void *opaque, target_phys_addr_t addr, unsigned size)
{
    BMDMAState *bm = opaque;
    uint32_t val;

    if (size != 1) {
        return ((uint64_t)1 << (size * 8)) - 1;
    }

    switch(addr & 3) {
    case 0:
        val = bm->cmd;
        break;
    case 2:
        val = bm->status;
        break;
    default:
        val = 0xff;
        break;
    }
#ifdef DEBUG_IDE
    printf("bmdma: readb 0x%02x : 0x%02x\n", (uint8_t)addr, val);
#endif
    return val;
}

static void bmdma_write(void *opaque, target_phys_addr_t addr,
                        uint64_t val, unsigned size)
{
    BMDMAState *bm = opaque;

    if (size != 1) {
        return;
    }

#ifdef DEBUG_IDE
    printf("bmdma: writeb 0x%02x : 0x%02x\n", (uint8_t)addr, (uint8_t)val);
#endif
    switch(addr & 3) {
    case 0:
        return bmdma_cmd_writeb(bm, val);
    case 2:
        bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
        break;
    }
}

static const MemoryRegionOps piix_bmdma_ops = {
    .read = bmdma_read,
    .write = bmdma_write,
};

static void bmdma_setup_bar(PCIIDEState *d)
{
    int i;

    memory_region_init(&d->bmdma_bar, "piix-bmdma-container", 16);
    for(i = 0;i < 2; i++) {
        BMDMAState *bm = &d->bmdma[i];

        memory_region_init_io(&bm->extra_io, &piix_bmdma_ops, bm,
                              "piix-bmdma", 4);
        memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io);
        memory_region_init_io(&bm->addr_ioport, &bmdma_addr_ioport_ops, bm,
                              "bmdma", 4);
        memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport);
    }
}

static void piix3_reset(void *opaque)
{
    PCIIDEState *d = opaque;
    uint8_t *pci_conf = d->dev.config;
    int i;

    for (i = 0; i < 2; i++) {
        ide_bus_reset(&d->bus[i]);
    }

    /* TODO: this is the default. do not override. */
    pci_conf[PCI_COMMAND] = 0x00;
    /* TODO: this is the default. do not override. */
    pci_conf[PCI_COMMAND + 1] = 0x00;
    /* TODO: use pci_set_word */
    pci_conf[PCI_STATUS] = PCI_STATUS_FAST_BACK;
    pci_conf[PCI_STATUS + 1] = PCI_STATUS_DEVSEL_MEDIUM >> 8;
    pci_conf[0x20] = 0x01; /* BMIBA: 20-23h */
}

static void pci_piix_init_ports(PCIIDEState *d) {
    static const struct {
        int iobase;
        int iobase2;
        int isairq;
    } port_info[] = {
        {0x1f0, 0x3f6, 14},
        {0x170, 0x376, 15},
    };
    int i;

    for (i = 0; i < 2; i++) {
        ide_bus_new(&d->bus[i], &d->dev.qdev, i);
        ide_init_ioport(&d->bus[i], NULL, port_info[i].iobase,
                        port_info[i].iobase2);
        ide_init2(&d->bus[i], isa_get_irq(NULL, port_info[i].isairq));

        bmdma_init(&d->bus[i], &d->bmdma[i], d);
        d->bmdma[i].bus = &d->bus[i];
        qemu_add_vm_change_state_handler(d->bus[i].dma->ops->restart_cb,
                                         &d->bmdma[i].dma);
    }
}

static int pci_piix_ide_initfn(PCIDevice *dev)
{
    PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
    uint8_t *pci_conf = d->dev.config;

    pci_conf[PCI_CLASS_PROG] = 0x80; // legacy ATA mode

    qemu_register_reset(piix3_reset, d);

    bmdma_setup_bar(d);
    pci_register_bar(&d->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);

    vmstate_register(&d->dev.qdev, 0, &vmstate_ide_pci, d);

    pci_piix_init_ports(d);

    return 0;
}

static int pci_piix3_xen_ide_unplug(DeviceState *dev)
{
    PCIDevice *pci_dev;
    PCIIDEState *pci_ide;
    DriveInfo *di;
    int i = 0;

    pci_dev = DO_UPCAST(PCIDevice, qdev, dev);
    pci_ide = DO_UPCAST(PCIIDEState, dev, pci_dev);

    for (; i < 3; i++) {
        di = drive_get_by_index(IF_IDE, i);
        if (di != NULL && !di->media_cd) {
            DeviceState *ds = bdrv_get_attached_dev(di->bdrv);
            if (ds) {
                bdrv_detach_dev(di->bdrv, ds);
            }
            bdrv_close(di->bdrv);
            pci_ide->bus[di->bus].ifs[di->unit].bs = NULL;
            drive_put_ref(di);
        }
    }
    qdev_reset_all(&(pci_ide->dev.qdev));
    return 0;
}

PCIDevice *pci_piix3_xen_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
{
    PCIDevice *dev;

    dev = pci_create_simple(bus, devfn, "piix3-ide-xen");
    pci_ide_create_devs(dev, hd_table);
    return dev;
}

static void pci_piix_ide_exitfn(PCIDevice *dev)
{
    PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
    unsigned i;

    for (i = 0; i < 2; ++i) {
        memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io);
        memory_region_destroy(&d->bmdma[i].extra_io);
        memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport);
        memory_region_destroy(&d->bmdma[i].addr_ioport);
    }
    memory_region_destroy(&d->bmdma_bar);
}

/* hd_table must contain 4 block drivers */
/* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */
PCIDevice *pci_piix3_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
{
    PCIDevice *dev;

    dev = pci_create_simple(bus, devfn, "piix3-ide");
    pci_ide_create_devs(dev, hd_table);
    return dev;
}

/* hd_table must contain 4 block drivers */
/* NOTE: for the PIIX4, the IRQs and IOports are hardcoded */
PCIDevice *pci_piix4_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
{
    PCIDevice *dev;

    dev = pci_create_simple(bus, devfn, "piix4-ide");
    pci_ide_create_devs(dev, hd_table);
    return dev;
}

static void piix3_ide_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

    k->no_hotplug = 1;
    k->init = pci_piix_ide_initfn;
    k->exit = pci_piix_ide_exitfn;
    k->vendor_id = PCI_VENDOR_ID_INTEL;
    k->device_id = PCI_DEVICE_ID_INTEL_82371SB_1;
    k->class_id = PCI_CLASS_STORAGE_IDE;
    dc->no_user = 1;
}

static TypeInfo piix3_ide_info = {
    .name          = "piix3-ide",
    .parent        = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIIDEState),
    .class_init    = piix3_ide_class_init,
};

static void piix3_ide_xen_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

    k->init = pci_piix_ide_initfn;
    k->vendor_id = PCI_VENDOR_ID_INTEL;
    k->device_id = PCI_DEVICE_ID_INTEL_82371SB_1;
    k->class_id = PCI_CLASS_STORAGE_IDE;
    dc->no_user = 1;
    dc->unplug = pci_piix3_xen_ide_unplug;
}

static TypeInfo piix3_ide_xen_info = {
    .name          = "piix3-ide-xen",
    .parent        = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIIDEState),
    .class_init    = piix3_ide_xen_class_init,
};

static void piix4_ide_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

    k->no_hotplug = 1;
    k->init = pci_piix_ide_initfn;
    k->exit = pci_piix_ide_exitfn;
    k->vendor_id = PCI_VENDOR_ID_INTEL;
    k->device_id = PCI_DEVICE_ID_INTEL_82371AB;
    k->class_id = PCI_CLASS_STORAGE_IDE;
    dc->no_user = 1;
}

static TypeInfo piix4_ide_info = {
    .name          = "piix4-ide",
    .parent        = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIIDEState),
    .class_init    = piix4_ide_class_init,
};

static void piix_ide_register_types(void)
{
    type_register_static(&piix3_ide_info);
    type_register_static(&piix3_ide_xen_info);
    type_register_static(&piix4_ide_info);
}

type_init(piix_ide_register_types)
Commit	Line	Data
4c3df0ec JQ	1	/*
	2	* QEMU IDE Emulation: PCI PIIX3/4 support.
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	* Copyright (c) 2006 Openedhand Ltd.
	6	*
	7	* Permission is hereby granted, free of charge, to any person obtaining a copy
	8	* of this software and associated documentation files (the "Software"), to deal
	9	* in the Software without restriction, including without limitation the rights
	10	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	11	* copies of the Software, and to permit persons to whom the Software is
	12	* furnished to do so, subject to the following conditions:
	13	*
	14	* The above copyright notice and this permission notice shall be included in
	15	* all copies or substantial portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	22	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	23	* THE SOFTWARE.
	24	*/
	25	#include <hw/hw.h>
	26	#include <hw/pc.h>
	27	#include <hw/pci.h>
	28	#include <hw/isa.h>
	29	#include "block.h"
4c3df0ec JQ	30	#include "sysemu.h"
	31	#include "dma.h"
	32
	33	#include <hw/ide/pci.h>
	34
a9deb8c6	35	static uint64_t bmdma_read(void *opaque, target_phys_addr_t addr, unsigned size)
4c3df0ec JQ	36	{
	37	BMDMAState *bm = opaque;
	38	uint32_t val;
	39
a9deb8c6 AK	40	if (size != 1) {
	41	return ((uint64_t)1 << (size * 8)) - 1;
	42	}
	43
4c3df0ec JQ	44	switch(addr & 3) {
	45	case 0:
	46	val = bm->cmd;
	47	break;
	48	case 2:
	49	val = bm->status;
	50	break;
	51	default:
	52	val = 0xff;
	53	break;
	54	}
	55	#ifdef DEBUG_IDE
cb67be85	56	printf("bmdma: readb 0x%02x : 0x%02x\n", (uint8_t)addr, val);
4c3df0ec JQ	57	#endif
	58	return val;
	59	}
	60
a9deb8c6 AK	61	static void bmdma_write(void *opaque, target_phys_addr_t addr,
a9deb8c6 AK	62	uint64_t val, unsigned size)
4c3df0ec JQ	63	{
4c3df0ec JQ	64	BMDMAState *bm = opaque;
a9deb8c6 AK	65
	66	if (size != 1) {
	67	return;
	68	}
	69
4c3df0ec	70	#ifdef DEBUG_IDE
cb67be85	71	printf("bmdma: writeb 0x%02x : 0x%02x\n", (uint8_t)addr, (uint8_t)val);
4c3df0ec JQ	72	#endif
4c3df0ec JQ	73	switch(addr & 3) {
a9deb8c6 AK	74	case 0:
a9deb8c6 AK	75	return bmdma_cmd_writeb(bm, val);
4c3df0ec JQ	76	case 2:
	77	bm->status = (val & 0x60) \| (bm->status & 1) \| (bm->status & ~val & 0x06);
	78	break;
	79	}
	80	}
	81
a348f108	82	static const MemoryRegionOps piix_bmdma_ops = {
a9deb8c6 AK	83	.read = bmdma_read,
	84	.write = bmdma_write,
	85	};
	86
	87	static void bmdma_setup_bar(PCIIDEState *d)
4c3df0ec	88	{
4c3df0ec JQ	89	int i;
4c3df0ec JQ	90
a9deb8c6	91	memory_region_init(&d->bmdma_bar, "piix-bmdma-container", 16);
4c3df0ec JQ	92	for(i = 0;i < 2; i++) {
4c3df0ec JQ	93	BMDMAState *bm = &d->bmdma[i];
4c3df0ec	94
a9deb8c6 AK	95	memory_region_init_io(&bm->extra_io, &piix_bmdma_ops, bm,
	96	"piix-bmdma", 4);
	97	memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io);
	98	memory_region_init_io(&bm->addr_ioport, &bmdma_addr_ioport_ops, bm,
	99	"bmdma", 4);
	100	memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport);
4c3df0ec JQ	101	}
	102	}
	103
	104	static void piix3_reset(void *opaque)
	105	{
	106	PCIIDEState *d = opaque;
	107	uint8_t *pci_conf = d->dev.config;
	108	int i;
	109
4a643563 BS	110	for (i = 0; i < 2; i++) {
4a643563 BS	111	ide_bus_reset(&d->bus[i]);
4a643563	112	}
4c3df0ec	113
1e68f8c4 MT	114	/* TODO: this is the default. do not override. */
	115	pci_conf[PCI_COMMAND] = 0x00;
	116	/* TODO: this is the default. do not override. */
	117	pci_conf[PCI_COMMAND + 1] = 0x00;
	118	/* TODO: use pci_set_word */
	119	pci_conf[PCI_STATUS] = PCI_STATUS_FAST_BACK;
	120	pci_conf[PCI_STATUS + 1] = PCI_STATUS_DEVSEL_MEDIUM >> 8;
4c3df0ec JQ	121	pci_conf[0x20] = 0x01; /* BMIBA: 20-23h */
	122	}
	123
61d9d6b0	124	static void pci_piix_init_ports(PCIIDEState *d) {
4a91d3b3	125	static const struct {
61d9d6b0 SH	126	int iobase;
	127	int iobase2;
	128	int isairq;
	129	} port_info[] = {
	130	{0x1f0, 0x3f6, 14},
	131	{0x170, 0x376, 15},
	132	};
4a91d3b3	133	int i;
61d9d6b0 SH	134
	135	for (i = 0; i < 2; i++) {
	136	ide_bus_new(&d->bus[i], &d->dev.qdev, i);
4a91d3b3 RH	137	ide_init_ioport(&d->bus[i], NULL, port_info[i].iobase,
4a91d3b3 RH	138	port_info[i].iobase2);
48a18b3c	139	ide_init2(&d->bus[i], isa_get_irq(NULL, port_info[i].isairq));
61d9d6b0	140
a9deb8c6	141	bmdma_init(&d->bus[i], &d->bmdma[i], d);
61d9d6b0 SH	142	d->bmdma[i].bus = &d->bus[i];
	143	qemu_add_vm_change_state_handler(d->bus[i].dma->ops->restart_cb,
	144	&d->bmdma[i].dma);
	145	}
	146	}
	147
25f8e2f5	148	static int pci_piix_ide_initfn(PCIDevice *dev)
4c3df0ec	149	{
25f8e2f5	150	PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
4c3df0ec JQ	151	uint8_t *pci_conf = d->dev.config;
4c3df0ec JQ	152
1e68f8c4	153	pci_conf[PCI_CLASS_PROG] = 0x80; // legacy ATA mode
4c3df0ec JQ	154
4c3df0ec JQ	155	qemu_register_reset(piix3_reset, d);
4c3df0ec	156
a9deb8c6	157	bmdma_setup_bar(d);
e824b2cc	158	pci_register_bar(&d->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);
4c3df0ec	159
0be71e32	160	vmstate_register(&d->dev.qdev, 0, &vmstate_ide_pci, d);
4c3df0ec	161
61d9d6b0	162	pci_piix_init_ports(d);
4c3df0ec	163
4c3df0ec JQ	164	return 0;
	165	}
	166
679f4f8b SS	167	static int pci_piix3_xen_ide_unplug(DeviceState *dev)
	168	{
	169	PCIDevice *pci_dev;
	170	PCIIDEState *pci_ide;
	171	DriveInfo *di;
	172	int i = 0;
	173
	174	pci_dev = DO_UPCAST(PCIDevice, qdev, dev);
	175	pci_ide = DO_UPCAST(PCIIDEState, dev, pci_dev);
	176
	177	for (; i < 3; i++) {
	178	di = drive_get_by_index(IF_IDE, i);
f9e8fda4	179	if (di != NULL && !di->media_cd) {
fa879d62	180	DeviceState *ds = bdrv_get_attached_dev(di->bdrv);
679f4f8b	181	if (ds) {
fa879d62	182	bdrv_detach_dev(di->bdrv, ds);
679f4f8b SS	183	}
	184	bdrv_close(di->bdrv);
	185	pci_ide->bus[di->bus].ifs[di->unit].bs = NULL;
	186	drive_put_ref(di);
	187	}
	188	}
	189	qdev_reset_all(&(pci_ide->dev.qdev));
	190	return 0;
	191	}
	192
	193	PCIDevice pci_piix3_xen_ide_init(PCIBus bus, DriveInfo **hd_table, int devfn)
	194	{
	195	PCIDevice *dev;
	196
	197	dev = pci_create_simple(bus, devfn, "piix3-ide-xen");
679f4f8b SS	198	pci_ide_create_devs(dev, hd_table);
	199	return dev;
	200	}
	201
f90c2bcd	202	static void pci_piix_ide_exitfn(PCIDevice *dev)
a9deb8c6 AK	203	{
	204	PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
	205	unsigned i;
	206
	207	for (i = 0; i < 2; ++i) {
	208	memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io);
	209	memory_region_destroy(&d->bmdma[i].extra_io);
	210	memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport);
	211	memory_region_destroy(&d->bmdma[i].addr_ioport);
	212	}
	213	memory_region_destroy(&d->bmdma_bar);
a9deb8c6 AK	214	}
a9deb8c6 AK	215
4c3df0ec JQ	216	/* hd_table must contain 4 block drivers */
4c3df0ec JQ	217	/* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */
57c88866	218	PCIDevice pci_piix3_ide_init(PCIBus bus, DriveInfo **hd_table, int devfn)
4c3df0ec JQ	219	{
	220	PCIDevice *dev;
	221
556cd098	222	dev = pci_create_simple(bus, devfn, "piix3-ide");
4c3df0ec	223	pci_ide_create_devs(dev, hd_table);
57c88866	224	return dev;
4c3df0ec JQ	225	}
	226
	227	/* hd_table must contain 4 block drivers */
	228	/* NOTE: for the PIIX4, the IRQs and IOports are hardcoded */
57c88866	229	PCIDevice pci_piix4_ide_init(PCIBus bus, DriveInfo **hd_table, int devfn)
4c3df0ec JQ	230	{
	231	PCIDevice *dev;
	232
556cd098	233	dev = pci_create_simple(bus, devfn, "piix4-ide");
4c3df0ec	234	pci_ide_create_devs(dev, hd_table);
57c88866	235	return dev;
4c3df0ec JQ	236	}
4c3df0ec JQ	237
40021f08 AL	238	static void piix3_ide_class_init(ObjectClass klass, void data)
40021f08 AL	239	{
39bffca2	240	DeviceClass *dc = DEVICE_CLASS(klass);
40021f08 AL	241	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
	242
	243	k->no_hotplug = 1;
	244	k->init = pci_piix_ide_initfn;
	245	k->exit = pci_piix_ide_exitfn;
	246	k->vendor_id = PCI_VENDOR_ID_INTEL;
	247	k->device_id = PCI_DEVICE_ID_INTEL_82371SB_1;
	248	k->class_id = PCI_CLASS_STORAGE_IDE;
39bffca2	249	dc->no_user = 1;
40021f08 AL	250	}
40021f08 AL	251
39bffca2 AL	252	static TypeInfo piix3_ide_info = {
	253	.name = "piix3-ide",
	254	.parent = TYPE_PCI_DEVICE,
	255	.instance_size = sizeof(PCIIDEState),
	256	.class_init = piix3_ide_class_init,
e855761c AL	257	};
e855761c AL	258
40021f08 AL	259	static void piix3_ide_xen_class_init(ObjectClass klass, void data)
40021f08 AL	260	{
39bffca2	261	DeviceClass *dc = DEVICE_CLASS(klass);
40021f08 AL	262	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
	263
	264	k->init = pci_piix_ide_initfn;
	265	k->vendor_id = PCI_VENDOR_ID_INTEL;
	266	k->device_id = PCI_DEVICE_ID_INTEL_82371SB_1;
	267	k->class_id = PCI_CLASS_STORAGE_IDE;
39bffca2 AL	268	dc->no_user = 1;
39bffca2 AL	269	dc->unplug = pci_piix3_xen_ide_unplug;
40021f08 AL	270	}
40021f08 AL	271
39bffca2 AL	272	static TypeInfo piix3_ide_xen_info = {
	273	.name = "piix3-ide-xen",
	274	.parent = TYPE_PCI_DEVICE,
	275	.instance_size = sizeof(PCIIDEState),
	276	.class_init = piix3_ide_xen_class_init,
e855761c AL	277	};
e855761c AL	278
40021f08 AL	279	static void piix4_ide_class_init(ObjectClass klass, void data)
40021f08 AL	280	{
39bffca2	281	DeviceClass *dc = DEVICE_CLASS(klass);
40021f08 AL	282	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
	283
	284	k->no_hotplug = 1;
	285	k->init = pci_piix_ide_initfn;
	286	k->exit = pci_piix_ide_exitfn;
	287	k->vendor_id = PCI_VENDOR_ID_INTEL;
	288	k->device_id = PCI_DEVICE_ID_INTEL_82371AB;
	289	k->class_id = PCI_CLASS_STORAGE_IDE;
39bffca2	290	dc->no_user = 1;
40021f08 AL	291	}
40021f08 AL	292
39bffca2 AL	293	static TypeInfo piix4_ide_info = {
	294	.name = "piix4-ide",
	295	.parent = TYPE_PCI_DEVICE,
	296	.instance_size = sizeof(PCIIDEState),
	297	.class_init = piix4_ide_class_init,
4c3df0ec JQ	298	};
4c3df0ec JQ	299
83f7d43a	300	static void piix_ide_register_types(void)
4c3df0ec	301	{
39bffca2 AL	302	type_register_static(&piix3_ide_info);
	303	type_register_static(&piix3_ide_xen_info);
	304	type_register_static(&piix4_ide_info);
4c3df0ec	305	}
83f7d43a AF	306
83f7d43a AF	307	type_init(piix_ide_register_types)