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016512f3 HC |
1 | /* |
2 | * QEMU IDE Emulation: PCI VIA82C686B support. | |
3 | * | |
4 | * Copyright (c) 2003 Fabrice Bellard | |
5 | * Copyright (c) 2006 Openedhand Ltd. | |
6 | * Copyright (c) 2010 Huacai Chen <zltjiangshi@gmail.com> | |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
9 | * of this software and associated documentation files (the "Software"), to deal | |
10 | * in the Software without restriction, including without limitation the rights | |
11 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
12 | * copies of the Software, and to permit persons to whom the Software is | |
13 | * furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice shall be included in | |
16 | * all copies or substantial portions of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
22 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
23 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
24 | * THE SOFTWARE. | |
25 | */ | |
0b8fa32f | 26 | |
53239262 | 27 | #include "qemu/osdep.h" |
a9c94277 | 28 | #include "hw/pci/pci.h" |
d6454270 | 29 | #include "migration/vmstate.h" |
0b8fa32f | 30 | #include "qemu/module.h" |
9c17d615 PB |
31 | #include "sysemu/sysemu.h" |
32 | #include "sysemu/dma.h" | |
71e8a915 | 33 | #include "sysemu/reset.h" |
016512f3 | 34 | |
a9c94277 | 35 | #include "hw/ide/pci.h" |
3eee2611 | 36 | #include "trace.h" |
016512f3 | 37 | |
a8170e5e | 38 | static uint64_t bmdma_read(void *opaque, hwaddr addr, |
a9deb8c6 | 39 | unsigned size) |
016512f3 HC |
40 | { |
41 | BMDMAState *bm = opaque; | |
42 | uint32_t val; | |
43 | ||
a9deb8c6 AK |
44 | if (size != 1) { |
45 | return ((uint64_t)1 << (size * 8)) - 1; | |
46 | } | |
47 | ||
016512f3 HC |
48 | switch (addr & 3) { |
49 | case 0: | |
50 | val = bm->cmd; | |
51 | break; | |
52 | case 2: | |
53 | val = bm->status; | |
54 | break; | |
55 | default: | |
56 | val = 0xff; | |
57 | break; | |
58 | } | |
3eee2611 JS |
59 | |
60 | trace_bmdma_read_via(addr, val); | |
016512f3 HC |
61 | return val; |
62 | } | |
63 | ||
a8170e5e | 64 | static void bmdma_write(void *opaque, hwaddr addr, |
a9deb8c6 | 65 | uint64_t val, unsigned size) |
016512f3 HC |
66 | { |
67 | BMDMAState *bm = opaque; | |
a9deb8c6 AK |
68 | |
69 | if (size != 1) { | |
70 | return; | |
71 | } | |
72 | ||
3eee2611 | 73 | trace_bmdma_write_via(addr, val); |
016512f3 | 74 | switch (addr & 3) { |
a9deb8c6 | 75 | case 0: |
0ed8b6f6 BS |
76 | bmdma_cmd_writeb(bm, val); |
77 | break; | |
016512f3 HC |
78 | case 2: |
79 | bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06); | |
80 | break; | |
81 | default:; | |
82 | } | |
83 | } | |
84 | ||
a348f108 | 85 | static const MemoryRegionOps via_bmdma_ops = { |
a9deb8c6 AK |
86 | .read = bmdma_read, |
87 | .write = bmdma_write, | |
88 | }; | |
89 | ||
90 | static void bmdma_setup_bar(PCIIDEState *d) | |
016512f3 | 91 | { |
016512f3 HC |
92 | int i; |
93 | ||
1437c94b | 94 | memory_region_init(&d->bmdma_bar, OBJECT(d), "via-bmdma-container", 16); |
016512f3 HC |
95 | for(i = 0;i < 2; i++) { |
96 | BMDMAState *bm = &d->bmdma[i]; | |
016512f3 | 97 | |
1437c94b | 98 | memory_region_init_io(&bm->extra_io, OBJECT(d), &via_bmdma_ops, bm, |
a9deb8c6 AK |
99 | "via-bmdma", 4); |
100 | memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io); | |
1437c94b PB |
101 | memory_region_init_io(&bm->addr_ioport, OBJECT(d), |
102 | &bmdma_addr_ioport_ops, bm, "bmdma", 4); | |
a9deb8c6 | 103 | memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport); |
016512f3 HC |
104 | } |
105 | } | |
106 | ||
4ea98d31 BZ |
107 | static void via_ide_set_irq(void *opaque, int n, int level) |
108 | { | |
109 | PCIDevice *d = PCI_DEVICE(opaque); | |
110 | ||
111 | if (level) { | |
112 | d->config[0x70 + n * 8] |= 0x80; | |
113 | } else { | |
114 | d->config[0x70 + n * 8] &= ~0x80; | |
115 | } | |
116 | ||
117 | level = (d->config[0x70] & 0x80) || (d->config[0x78] & 0x80); | |
118 | n = pci_get_byte(d->config + PCI_INTERRUPT_LINE); | |
119 | if (n) { | |
120 | qemu_set_irq(isa_get_irq(NULL, n), level); | |
121 | } | |
122 | } | |
123 | ||
7dd687ba | 124 | static void via_ide_reset(void *opaque) |
016512f3 HC |
125 | { |
126 | PCIIDEState *d = opaque; | |
f6c11d56 AF |
127 | PCIDevice *pd = PCI_DEVICE(d); |
128 | uint8_t *pci_conf = pd->config; | |
016512f3 HC |
129 | int i; |
130 | ||
131 | for (i = 0; i < 2; i++) { | |
132 | ide_bus_reset(&d->bus[i]); | |
016512f3 HC |
133 | } |
134 | ||
4ea98d31 | 135 | pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_WAIT); |
016512f3 HC |
136 | pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK | |
137 | PCI_STATUS_DEVSEL_MEDIUM); | |
138 | ||
139 | pci_set_long(pci_conf + PCI_BASE_ADDRESS_0, 0x000001f0); | |
140 | pci_set_long(pci_conf + PCI_BASE_ADDRESS_1, 0x000003f4); | |
141 | pci_set_long(pci_conf + PCI_BASE_ADDRESS_2, 0x00000170); | |
142 | pci_set_long(pci_conf + PCI_BASE_ADDRESS_3, 0x00000374); | |
143 | pci_set_long(pci_conf + PCI_BASE_ADDRESS_4, 0x0000cc01); /* BMIBA: 20-23h */ | |
144 | pci_set_long(pci_conf + PCI_INTERRUPT_LINE, 0x0000010e); | |
145 | ||
146 | /* IDE chip enable, IDE configuration 1/2, IDE FIFO Configuration*/ | |
147 | pci_set_long(pci_conf + 0x40, 0x0a090600); | |
148 | /* IDE misc configuration 1/2/3 */ | |
149 | pci_set_long(pci_conf + 0x44, 0x00c00068); | |
150 | /* IDE Timing control */ | |
151 | pci_set_long(pci_conf + 0x48, 0xa8a8a8a8); | |
152 | /* IDE Address Setup Time */ | |
153 | pci_set_long(pci_conf + 0x4c, 0x000000ff); | |
154 | /* UltraDMA Extended Timing Control*/ | |
155 | pci_set_long(pci_conf + 0x50, 0x07070707); | |
156 | /* UltraDMA FIFO Control */ | |
157 | pci_set_long(pci_conf + 0x54, 0x00000004); | |
158 | /* IDE primary sector size */ | |
159 | pci_set_long(pci_conf + 0x60, 0x00000200); | |
160 | /* IDE secondary sector size */ | |
161 | pci_set_long(pci_conf + 0x68, 0x00000200); | |
162 | /* PCI PM Block */ | |
163 | pci_set_long(pci_conf + 0xc0, 0x00020001); | |
164 | } | |
165 | ||
7dd687ba | 166 | static void via_ide_realize(PCIDevice *dev, Error **errp) |
016512f3 | 167 | { |
f6c11d56 AF |
168 | PCIIDEState *d = PCI_IDE(dev); |
169 | uint8_t *pci_conf = dev->config; | |
0252e66c | 170 | int i; |
016512f3 | 171 | |
4ea98d31 | 172 | pci_config_set_prog_interface(pci_conf, 0x8f); /* native PCI ATA mode */ |
016512f3 | 173 | pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0); |
4ea98d31 | 174 | dev->wmask[PCI_INTERRUPT_LINE] = 0xf; |
016512f3 | 175 | |
7dd687ba | 176 | qemu_register_reset(via_ide_reset, d); |
4ea98d31 BZ |
177 | |
178 | memory_region_init_io(&d->data_bar[0], OBJECT(d), &pci_ide_data_le_ops, | |
179 | &d->bus[0], "via-ide0-data", 8); | |
180 | pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->data_bar[0]); | |
181 | ||
182 | memory_region_init_io(&d->cmd_bar[0], OBJECT(d), &pci_ide_cmd_le_ops, | |
183 | &d->bus[0], "via-ide0-cmd", 4); | |
184 | pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd_bar[0]); | |
185 | ||
186 | memory_region_init_io(&d->data_bar[1], OBJECT(d), &pci_ide_data_le_ops, | |
187 | &d->bus[1], "via-ide1-data", 8); | |
188 | pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, &d->data_bar[1]); | |
189 | ||
190 | memory_region_init_io(&d->cmd_bar[1], OBJECT(d), &pci_ide_cmd_le_ops, | |
191 | &d->bus[1], "via-ide1-cmd", 4); | |
192 | pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd_bar[1]); | |
193 | ||
a9deb8c6 | 194 | bmdma_setup_bar(d); |
f6c11d56 | 195 | pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar); |
016512f3 | 196 | |
f6c11d56 | 197 | vmstate_register(DEVICE(dev), 0, &vmstate_ide_pci, d); |
016512f3 | 198 | |
0252e66c BZ |
199 | for (i = 0; i < 2; i++) { |
200 | ide_bus_new(&d->bus[i], sizeof(d->bus[i]), DEVICE(d), i, 2); | |
4ea98d31 | 201 | ide_init2(&d->bus[i], qemu_allocate_irq(via_ide_set_irq, d, i)); |
0252e66c BZ |
202 | |
203 | bmdma_init(&d->bus[i], &d->bmdma[i], d); | |
204 | d->bmdma[i].bus = &d->bus[i]; | |
205 | ide_register_restart_cb(&d->bus[i]); | |
206 | } | |
016512f3 HC |
207 | } |
208 | ||
7dd687ba | 209 | static void via_ide_exitfn(PCIDevice *dev) |
a9deb8c6 | 210 | { |
f6c11d56 | 211 | PCIIDEState *d = PCI_IDE(dev); |
a9deb8c6 AK |
212 | unsigned i; |
213 | ||
214 | for (i = 0; i < 2; ++i) { | |
215 | memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io); | |
a9deb8c6 | 216 | memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport); |
a9deb8c6 | 217 | } |
a9deb8c6 AK |
218 | } |
219 | ||
7dd687ba | 220 | void via_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn) |
016512f3 HC |
221 | { |
222 | PCIDevice *dev; | |
223 | ||
224 | dev = pci_create_simple(bus, devfn, "via-ide"); | |
225 | pci_ide_create_devs(dev, hd_table); | |
226 | } | |
227 | ||
40021f08 AL |
228 | static void via_ide_class_init(ObjectClass *klass, void *data) |
229 | { | |
39bffca2 | 230 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
231 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
232 | ||
7dd687ba BZ |
233 | k->realize = via_ide_realize; |
234 | k->exit = via_ide_exitfn; | |
40021f08 AL |
235 | k->vendor_id = PCI_VENDOR_ID_VIA; |
236 | k->device_id = PCI_DEVICE_ID_VIA_IDE; | |
237 | k->revision = 0x06; | |
238 | k->class_id = PCI_CLASS_STORAGE_IDE; | |
125ee0ed | 239 | set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); |
40021f08 AL |
240 | } |
241 | ||
8c43a6f0 | 242 | static const TypeInfo via_ide_info = { |
39bffca2 | 243 | .name = "via-ide", |
f6c11d56 | 244 | .parent = TYPE_PCI_IDE, |
39bffca2 | 245 | .class_init = via_ide_class_init, |
016512f3 HC |
246 | }; |
247 | ||
83f7d43a | 248 | static void via_ide_register_types(void) |
016512f3 | 249 | { |
39bffca2 | 250 | type_register_static(&via_ide_info); |
016512f3 | 251 | } |
83f7d43a AF |
252 | |
253 | type_init(via_ide_register_types) |