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977e1244 GH |
1 | /* |
2 | * QEMU IDE Emulation: PCI Bus support. | |
3 | * | |
4 | * Copyright (c) 2003 Fabrice Bellard | |
5 | * Copyright (c) 2006 Openedhand Ltd. | |
6 | * | |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
25 | #include "hw.h" | |
26 | #include "pc.h" | |
27 | #include "block.h" | |
28 | #include "block_int.h" | |
29 | #include "sysemu.h" | |
30 | #include "dma.h" | |
31 | #include "pci.h" | |
32 | #include "ide-internal.h" | |
33 | ||
34 | /***********************************************************/ | |
35 | /* PCI IDE definitions */ | |
36 | ||
37 | /* CMD646 specific */ | |
38 | #define MRDMODE 0x71 | |
39 | #define MRDMODE_INTR_CH0 0x04 | |
40 | #define MRDMODE_INTR_CH1 0x08 | |
41 | #define MRDMODE_BLK_CH0 0x10 | |
42 | #define MRDMODE_BLK_CH1 0x20 | |
43 | #define UDIDETCR0 0x73 | |
44 | #define UDIDETCR1 0x7B | |
45 | ||
46 | #define IDE_TYPE_PIIX3 0 | |
47 | #define IDE_TYPE_CMD646 1 | |
48 | #define IDE_TYPE_PIIX4 2 | |
49 | ||
50 | typedef struct PCIIDEState { | |
51 | PCIDevice dev; | |
52 | IDEBus bus[2]; | |
53 | BMDMAState bmdma[2]; | |
54 | int type; /* see IDE_TYPE_xxx */ | |
55 | } PCIIDEState; | |
56 | ||
57 | static void cmd646_update_irq(PCIIDEState *d); | |
58 | ||
59 | static void ide_map(PCIDevice *pci_dev, int region_num, | |
60 | uint32_t addr, uint32_t size, int type) | |
61 | { | |
62 | PCIIDEState *d = (PCIIDEState *)pci_dev; | |
63 | IDEBus *bus; | |
64 | ||
65 | if (region_num <= 3) { | |
66 | bus = &d->bus[(region_num >> 1)]; | |
67 | if (region_num & 1) { | |
68 | register_ioport_read(addr + 2, 1, 1, ide_status_read, bus); | |
69 | register_ioport_write(addr + 2, 1, 1, ide_cmd_write, bus); | |
70 | } else { | |
71 | register_ioport_write(addr, 8, 1, ide_ioport_write, bus); | |
72 | register_ioport_read(addr, 8, 1, ide_ioport_read, bus); | |
73 | ||
74 | /* data ports */ | |
75 | register_ioport_write(addr, 2, 2, ide_data_writew, bus); | |
76 | register_ioport_read(addr, 2, 2, ide_data_readw, bus); | |
77 | register_ioport_write(addr, 4, 4, ide_data_writel, bus); | |
78 | register_ioport_read(addr, 4, 4, ide_data_readl, bus); | |
79 | } | |
80 | } | |
81 | } | |
82 | ||
83 | static void bmdma_cmd_writeb(void *opaque, uint32_t addr, uint32_t val) | |
84 | { | |
85 | BMDMAState *bm = opaque; | |
86 | #ifdef DEBUG_IDE | |
87 | printf("%s: 0x%08x\n", __func__, val); | |
88 | #endif | |
89 | if (!(val & BM_CMD_START)) { | |
90 | /* XXX: do it better */ | |
91 | ide_dma_cancel(bm); | |
92 | bm->cmd = val & 0x09; | |
93 | } else { | |
94 | if (!(bm->status & BM_STATUS_DMAING)) { | |
95 | bm->status |= BM_STATUS_DMAING; | |
96 | /* start dma transfer if possible */ | |
97 | if (bm->dma_cb) | |
98 | bm->dma_cb(bm, 0); | |
99 | } | |
100 | bm->cmd = val & 0x09; | |
101 | } | |
102 | } | |
103 | ||
104 | static uint32_t bmdma_readb(void *opaque, uint32_t addr) | |
105 | { | |
106 | BMDMAState *bm = opaque; | |
107 | PCIIDEState *pci_dev; | |
108 | uint32_t val; | |
109 | ||
110 | switch(addr & 3) { | |
111 | case 0: | |
112 | val = bm->cmd; | |
113 | break; | |
114 | case 1: | |
115 | pci_dev = bm->pci_dev; | |
116 | if (pci_dev->type == IDE_TYPE_CMD646) { | |
117 | val = pci_dev->dev.config[MRDMODE]; | |
118 | } else { | |
119 | val = 0xff; | |
120 | } | |
121 | break; | |
122 | case 2: | |
123 | val = bm->status; | |
124 | break; | |
125 | case 3: | |
126 | pci_dev = bm->pci_dev; | |
127 | if (pci_dev->type == IDE_TYPE_CMD646) { | |
128 | if (bm == &pci_dev->bmdma[0]) | |
129 | val = pci_dev->dev.config[UDIDETCR0]; | |
130 | else | |
131 | val = pci_dev->dev.config[UDIDETCR1]; | |
132 | } else { | |
133 | val = 0xff; | |
134 | } | |
135 | break; | |
136 | default: | |
137 | val = 0xff; | |
138 | break; | |
139 | } | |
140 | #ifdef DEBUG_IDE | |
141 | printf("bmdma: readb 0x%02x : 0x%02x\n", addr, val); | |
142 | #endif | |
143 | return val; | |
144 | } | |
145 | ||
146 | static void bmdma_writeb(void *opaque, uint32_t addr, uint32_t val) | |
147 | { | |
148 | BMDMAState *bm = opaque; | |
149 | PCIIDEState *pci_dev; | |
150 | #ifdef DEBUG_IDE | |
151 | printf("bmdma: writeb 0x%02x : 0x%02x\n", addr, val); | |
152 | #endif | |
153 | switch(addr & 3) { | |
154 | case 1: | |
155 | pci_dev = bm->pci_dev; | |
156 | if (pci_dev->type == IDE_TYPE_CMD646) { | |
157 | pci_dev->dev.config[MRDMODE] = | |
158 | (pci_dev->dev.config[MRDMODE] & ~0x30) | (val & 0x30); | |
159 | cmd646_update_irq(pci_dev); | |
160 | } | |
161 | break; | |
162 | case 2: | |
163 | bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06); | |
164 | break; | |
165 | case 3: | |
166 | pci_dev = bm->pci_dev; | |
167 | if (pci_dev->type == IDE_TYPE_CMD646) { | |
168 | if (bm == &pci_dev->bmdma[0]) | |
169 | pci_dev->dev.config[UDIDETCR0] = val; | |
170 | else | |
171 | pci_dev->dev.config[UDIDETCR1] = val; | |
172 | } | |
173 | break; | |
174 | } | |
175 | } | |
176 | ||
177 | static uint32_t bmdma_addr_readb(void *opaque, uint32_t addr) | |
178 | { | |
179 | BMDMAState *bm = opaque; | |
180 | uint32_t val; | |
181 | val = (bm->addr >> ((addr & 3) * 8)) & 0xff; | |
182 | #ifdef DEBUG_IDE | |
183 | printf("%s: 0x%08x\n", __func__, val); | |
184 | #endif | |
185 | return val; | |
186 | } | |
187 | ||
188 | static void bmdma_addr_writeb(void *opaque, uint32_t addr, uint32_t val) | |
189 | { | |
190 | BMDMAState *bm = opaque; | |
191 | int shift = (addr & 3) * 8; | |
192 | #ifdef DEBUG_IDE | |
193 | printf("%s: 0x%08x\n", __func__, val); | |
194 | #endif | |
195 | bm->addr &= ~(0xFF << shift); | |
196 | bm->addr |= ((val & 0xFF) << shift) & ~3; | |
197 | bm->cur_addr = bm->addr; | |
198 | } | |
199 | ||
200 | static uint32_t bmdma_addr_readw(void *opaque, uint32_t addr) | |
201 | { | |
202 | BMDMAState *bm = opaque; | |
203 | uint32_t val; | |
204 | val = (bm->addr >> ((addr & 3) * 8)) & 0xffff; | |
205 | #ifdef DEBUG_IDE | |
206 | printf("%s: 0x%08x\n", __func__, val); | |
207 | #endif | |
208 | return val; | |
209 | } | |
210 | ||
211 | static void bmdma_addr_writew(void *opaque, uint32_t addr, uint32_t val) | |
212 | { | |
213 | BMDMAState *bm = opaque; | |
214 | int shift = (addr & 3) * 8; | |
215 | #ifdef DEBUG_IDE | |
216 | printf("%s: 0x%08x\n", __func__, val); | |
217 | #endif | |
218 | bm->addr &= ~(0xFFFF << shift); | |
219 | bm->addr |= ((val & 0xFFFF) << shift) & ~3; | |
220 | bm->cur_addr = bm->addr; | |
221 | } | |
222 | ||
223 | static uint32_t bmdma_addr_readl(void *opaque, uint32_t addr) | |
224 | { | |
225 | BMDMAState *bm = opaque; | |
226 | uint32_t val; | |
227 | val = bm->addr; | |
228 | #ifdef DEBUG_IDE | |
229 | printf("%s: 0x%08x\n", __func__, val); | |
230 | #endif | |
231 | return val; | |
232 | } | |
233 | ||
234 | static void bmdma_addr_writel(void *opaque, uint32_t addr, uint32_t val) | |
235 | { | |
236 | BMDMAState *bm = opaque; | |
237 | #ifdef DEBUG_IDE | |
238 | printf("%s: 0x%08x\n", __func__, val); | |
239 | #endif | |
240 | bm->addr = val & ~3; | |
241 | bm->cur_addr = bm->addr; | |
242 | } | |
243 | ||
244 | static void bmdma_map(PCIDevice *pci_dev, int region_num, | |
245 | uint32_t addr, uint32_t size, int type) | |
246 | { | |
247 | PCIIDEState *d = (PCIIDEState *)pci_dev; | |
248 | int i; | |
249 | ||
250 | for(i = 0;i < 2; i++) { | |
251 | BMDMAState *bm = &d->bmdma[i]; | |
252 | d->bus[i].bmdma = bm; | |
253 | bm->pci_dev = DO_UPCAST(PCIIDEState, dev, pci_dev); | |
254 | bm->bus = d->bus+i; | |
255 | qemu_add_vm_change_state_handler(ide_dma_restart_cb, bm); | |
256 | ||
257 | register_ioport_write(addr, 1, 1, bmdma_cmd_writeb, bm); | |
258 | ||
259 | register_ioport_write(addr + 1, 3, 1, bmdma_writeb, bm); | |
260 | register_ioport_read(addr, 4, 1, bmdma_readb, bm); | |
261 | ||
262 | register_ioport_write(addr + 4, 4, 1, bmdma_addr_writeb, bm); | |
263 | register_ioport_read(addr + 4, 4, 1, bmdma_addr_readb, bm); | |
264 | register_ioport_write(addr + 4, 4, 2, bmdma_addr_writew, bm); | |
265 | register_ioport_read(addr + 4, 4, 2, bmdma_addr_readw, bm); | |
266 | register_ioport_write(addr + 4, 4, 4, bmdma_addr_writel, bm); | |
267 | register_ioport_read(addr + 4, 4, 4, bmdma_addr_readl, bm); | |
268 | addr += 8; | |
269 | } | |
270 | } | |
271 | ||
272 | static void pci_ide_save(QEMUFile* f, void *opaque) | |
273 | { | |
274 | PCIIDEState *d = opaque; | |
275 | int i; | |
276 | ||
277 | pci_device_save(&d->dev, f); | |
278 | ||
279 | for(i = 0; i < 2; i++) { | |
280 | BMDMAState *bm = &d->bmdma[i]; | |
281 | uint8_t ifidx; | |
282 | qemu_put_8s(f, &bm->cmd); | |
283 | qemu_put_8s(f, &bm->status); | |
284 | qemu_put_be32s(f, &bm->addr); | |
285 | qemu_put_sbe64s(f, &bm->sector_num); | |
286 | qemu_put_be32s(f, &bm->nsector); | |
287 | ifidx = bm->unit + 2*i; | |
288 | qemu_put_8s(f, &ifidx); | |
289 | /* XXX: if a transfer is pending, we do not save it yet */ | |
290 | } | |
291 | ||
292 | /* per IDE interface data */ | |
293 | for(i = 0; i < 2; i++) { | |
294 | idebus_save(f, &d->bus[i]); | |
295 | } | |
296 | ||
297 | /* per IDE drive data */ | |
298 | for(i = 0; i < 2; i++) { | |
299 | ide_save(f, &d->bus[i].ifs[0]); | |
300 | ide_save(f, &d->bus[i].ifs[1]); | |
301 | } | |
302 | } | |
303 | ||
304 | static int pci_ide_load(QEMUFile* f, void *opaque, int version_id) | |
305 | { | |
306 | PCIIDEState *d = opaque; | |
307 | int ret, i; | |
308 | ||
309 | if (version_id != 2 && version_id != 3) | |
310 | return -EINVAL; | |
311 | ret = pci_device_load(&d->dev, f); | |
312 | if (ret < 0) | |
313 | return ret; | |
314 | ||
315 | for(i = 0; i < 2; i++) { | |
316 | BMDMAState *bm = &d->bmdma[i]; | |
317 | uint8_t ifidx; | |
318 | qemu_get_8s(f, &bm->cmd); | |
319 | qemu_get_8s(f, &bm->status); | |
320 | qemu_get_be32s(f, &bm->addr); | |
321 | qemu_get_sbe64s(f, &bm->sector_num); | |
322 | qemu_get_be32s(f, &bm->nsector); | |
323 | qemu_get_8s(f, &ifidx); | |
324 | bm->unit = ifidx & 1; | |
325 | /* XXX: if a transfer is pending, we do not save it yet */ | |
326 | } | |
327 | ||
328 | /* per IDE interface data */ | |
329 | for(i = 0; i < 2; i++) { | |
330 | idebus_load(f, &d->bus[i], version_id); | |
331 | } | |
332 | ||
333 | /* per IDE drive data */ | |
334 | for(i = 0; i < 2; i++) { | |
335 | ide_load(f, &d->bus[i].ifs[0], version_id); | |
336 | ide_load(f, &d->bus[i].ifs[1], version_id); | |
337 | } | |
338 | return 0; | |
339 | } | |
340 | ||
341 | /* XXX: call it also when the MRDMODE is changed from the PCI config | |
342 | registers */ | |
343 | static void cmd646_update_irq(PCIIDEState *d) | |
344 | { | |
345 | int pci_level; | |
346 | pci_level = ((d->dev.config[MRDMODE] & MRDMODE_INTR_CH0) && | |
347 | !(d->dev.config[MRDMODE] & MRDMODE_BLK_CH0)) || | |
348 | ((d->dev.config[MRDMODE] & MRDMODE_INTR_CH1) && | |
349 | !(d->dev.config[MRDMODE] & MRDMODE_BLK_CH1)); | |
350 | qemu_set_irq(d->dev.irq[0], pci_level); | |
351 | } | |
352 | ||
353 | /* the PCI irq level is the logical OR of the two channels */ | |
354 | static void cmd646_set_irq(void *opaque, int channel, int level) | |
355 | { | |
356 | PCIIDEState *d = opaque; | |
357 | int irq_mask; | |
358 | ||
359 | irq_mask = MRDMODE_INTR_CH0 << channel; | |
360 | if (level) | |
361 | d->dev.config[MRDMODE] |= irq_mask; | |
362 | else | |
363 | d->dev.config[MRDMODE] &= ~irq_mask; | |
364 | cmd646_update_irq(d); | |
365 | } | |
366 | ||
367 | static void cmd646_reset(void *opaque) | |
368 | { | |
369 | PCIIDEState *d = opaque; | |
370 | unsigned int i; | |
371 | ||
372 | for (i = 0; i < 2; i++) | |
373 | ide_dma_cancel(&d->bmdma[i]); | |
374 | } | |
375 | ||
376 | /* CMD646 PCI IDE controller */ | |
377 | void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table, | |
378 | int secondary_ide_enabled) | |
379 | { | |
380 | PCIIDEState *d; | |
381 | uint8_t *pci_conf; | |
382 | qemu_irq *irq; | |
383 | ||
384 | d = (PCIIDEState *)pci_register_device(bus, "CMD646 IDE", | |
385 | sizeof(PCIIDEState), | |
386 | -1, | |
387 | NULL, NULL); | |
388 | d->type = IDE_TYPE_CMD646; | |
389 | pci_conf = d->dev.config; | |
390 | pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_CMD); | |
391 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_CMD_646); | |
392 | ||
393 | pci_conf[0x08] = 0x07; // IDE controller revision | |
394 | pci_conf[0x09] = 0x8f; | |
395 | ||
396 | pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE); | |
397 | pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type | |
398 | ||
399 | pci_conf[0x51] = 0x04; // enable IDE0 | |
400 | if (secondary_ide_enabled) { | |
401 | /* XXX: if not enabled, really disable the seconday IDE controller */ | |
402 | pci_conf[0x51] |= 0x08; /* enable IDE1 */ | |
403 | } | |
404 | ||
405 | pci_register_bar((PCIDevice *)d, 0, 0x8, | |
406 | PCI_ADDRESS_SPACE_IO, ide_map); | |
407 | pci_register_bar((PCIDevice *)d, 1, 0x4, | |
408 | PCI_ADDRESS_SPACE_IO, ide_map); | |
409 | pci_register_bar((PCIDevice *)d, 2, 0x8, | |
410 | PCI_ADDRESS_SPACE_IO, ide_map); | |
411 | pci_register_bar((PCIDevice *)d, 3, 0x4, | |
412 | PCI_ADDRESS_SPACE_IO, ide_map); | |
413 | pci_register_bar((PCIDevice *)d, 4, 0x10, | |
414 | PCI_ADDRESS_SPACE_IO, bmdma_map); | |
415 | ||
416 | pci_conf[0x3d] = 0x01; // interrupt on pin 1 | |
417 | ||
418 | irq = qemu_allocate_irqs(cmd646_set_irq, d, 2); | |
419 | ide_init2(&d->bus[0], hd_table[0], hd_table[1], irq[0]); | |
420 | ide_init2(&d->bus[1], hd_table[2], hd_table[3], irq[1]); | |
421 | ||
422 | register_savevm("ide", 0, 3, pci_ide_save, pci_ide_load, d); | |
423 | qemu_register_reset(cmd646_reset, d); | |
424 | cmd646_reset(d); | |
425 | } | |
426 | ||
427 | static void piix3_reset(void *opaque) | |
428 | { | |
429 | PCIIDEState *d = opaque; | |
430 | uint8_t *pci_conf = d->dev.config; | |
431 | int i; | |
432 | ||
433 | for (i = 0; i < 2; i++) | |
434 | ide_dma_cancel(&d->bmdma[i]); | |
435 | ||
436 | pci_conf[0x04] = 0x00; | |
437 | pci_conf[0x05] = 0x00; | |
438 | pci_conf[0x06] = 0x80; /* FBC */ | |
439 | pci_conf[0x07] = 0x02; // PCI_status_devsel_medium | |
440 | pci_conf[0x20] = 0x01; /* BMIBA: 20-23h */ | |
441 | } | |
442 | ||
443 | /* hd_table must contain 4 block drivers */ | |
444 | /* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */ | |
445 | void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn, | |
446 | qemu_irq *pic) | |
447 | { | |
448 | PCIIDEState *d; | |
449 | uint8_t *pci_conf; | |
450 | int i; | |
451 | ||
452 | /* register a function 1 of PIIX3 */ | |
453 | d = (PCIIDEState *)pci_register_device(bus, "PIIX3 IDE", | |
454 | sizeof(PCIIDEState), | |
455 | devfn, | |
456 | NULL, NULL); | |
457 | d->type = IDE_TYPE_PIIX3; | |
458 | ||
459 | pci_conf = d->dev.config; | |
460 | pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); | |
461 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_1); | |
462 | pci_conf[0x09] = 0x80; // legacy ATA mode | |
463 | pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE); | |
464 | pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type | |
465 | ||
466 | qemu_register_reset(piix3_reset, d); | |
467 | piix3_reset(d); | |
468 | ||
469 | pci_register_bar((PCIDevice *)d, 4, 0x10, | |
470 | PCI_ADDRESS_SPACE_IO, bmdma_map); | |
471 | ||
472 | ide_init2(&d->bus[0], hd_table[0], hd_table[1], isa_reserve_irq(14)); | |
473 | ide_init2(&d->bus[1], hd_table[2], hd_table[3], isa_reserve_irq(15)); | |
474 | ide_init_ioport(&d->bus[0], 0x1f0, 0x3f6); | |
475 | ide_init_ioport(&d->bus[1], 0x170, 0x376); | |
476 | ||
477 | for (i = 0; i < 4; i++) | |
478 | if (hd_table[i]) | |
479 | hd_table[i]->private = &d->dev; | |
480 | ||
481 | register_savevm("ide", 0, 3, pci_ide_save, pci_ide_load, d); | |
482 | } | |
483 | ||
484 | /* hd_table must contain 4 block drivers */ | |
485 | /* NOTE: for the PIIX4, the IRQs and IOports are hardcoded */ | |
486 | void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn, | |
487 | qemu_irq *pic) | |
488 | { | |
489 | PCIIDEState *d; | |
490 | uint8_t *pci_conf; | |
491 | ||
492 | /* register a function 1 of PIIX4 */ | |
493 | d = (PCIIDEState *)pci_register_device(bus, "PIIX4 IDE", | |
494 | sizeof(PCIIDEState), | |
495 | devfn, | |
496 | NULL, NULL); | |
497 | d->type = IDE_TYPE_PIIX4; | |
498 | ||
499 | pci_conf = d->dev.config; | |
500 | pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); | |
501 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB); | |
502 | pci_conf[0x09] = 0x80; // legacy ATA mode | |
503 | pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE); | |
504 | pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type | |
505 | ||
506 | qemu_register_reset(piix3_reset, d); | |
507 | piix3_reset(d); | |
508 | ||
509 | pci_register_bar((PCIDevice *)d, 4, 0x10, | |
510 | PCI_ADDRESS_SPACE_IO, bmdma_map); | |
511 | ||
512 | /* | |
513 | * These should call isa_reserve_irq() instead when MIPS supports it | |
514 | */ | |
515 | ide_init2(&d->bus[0], hd_table[0], hd_table[1], pic[14]); | |
516 | ide_init2(&d->bus[1], hd_table[2], hd_table[3], pic[15]); | |
517 | ide_init_ioport(&d->bus[0], 0x1f0, 0x3f6); | |
518 | ide_init_ioport(&d->bus[1], 0x170, 0x376); | |
519 | ||
520 | register_savevm("ide", 0, 3, pci_ide_save, pci_ide_load, d); | |
521 | } | |
522 |