[mirror_qemu.git] / hw / input / lm832x.c

/*
 * National Semiconductor LM8322/8323 GPIO keyboard & PWM chips.
 *
 * Copyright (C) 2008 Nokia Corporation
 * Written by Andrzej Zaborowski <andrew@openedhand.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 or
 * (at your option) version 3 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "hw/i2c/i2c.h"
#include "hw/irq.h"
#include "migration/vmstate.h"
#include "qemu/module.h"
#include "qemu/timer.h"
#include "ui/console.h"
#include "qom/object.h"

#define TYPE_LM8323 "lm8323"
OBJECT_DECLARE_SIMPLE_TYPE(LM823KbdState, LM8323)

struct LM823KbdState {
    I2CSlave parent_obj;

    uint8_t i2c_dir;
    uint8_t i2c_cycle;
    uint8_t reg;

    qemu_irq nirq;
    uint16_t model;

    struct {
        qemu_irq out[2];
        int in[2][2];
    } mux;

    uint8_t config;
    uint8_t status;
    uint8_t acttime;
    uint8_t error;
    uint8_t clock;

    struct {
        uint16_t pull;
        uint16_t mask;
        uint16_t dir;
        uint16_t level;
        qemu_irq out[16];
    } gpio;

    struct {
        uint8_t dbnctime;
        uint8_t size;
        uint8_t start;
        uint8_t len;
        uint8_t fifo[16];
    } kbd;

    struct {
        uint16_t file[256];
        uint8_t faddr;
        uint8_t addr[3];
        QEMUTimer *tm[3];
    } pwm;
};

#define INT_KEYPAD		(1 << 0)
#define INT_ERROR		(1 << 3)
#define INT_NOINIT		(1 << 4)
#define INT_PWMEND(n)		(1 << (5 + n))

#define ERR_BADPAR		(1 << 0)
#define ERR_CMDUNK		(1 << 1)
#define ERR_KEYOVR		(1 << 2)
#define ERR_FIFOOVR		(1 << 6)

static void lm_kbd_irq_update(LM823KbdState *s)
{
    qemu_set_irq(s->nirq, !s->status);
}

static void lm_kbd_gpio_update(LM823KbdState *s)
{
}

static void lm_kbd_reset(DeviceState *dev)
{
    LM823KbdState *s = LM8323(dev);

    s->config = 0x80;
    s->status = INT_NOINIT;
    s->acttime = 125;
    s->kbd.dbnctime = 3;
    s->kbd.size = 0x33;
    s->clock = 0x08;

    lm_kbd_irq_update(s);
    lm_kbd_gpio_update(s);
}

static void lm_kbd_error(LM823KbdState *s, int err)
{
    s->error |= err;
    s->status |= INT_ERROR;
    lm_kbd_irq_update(s);
}

static void lm_kbd_pwm_tick(LM823KbdState *s, int line)
{
}

static void lm_kbd_pwm_start(LM823KbdState *s, int line)
{
    lm_kbd_pwm_tick(s, line);
}

static void lm_kbd_pwm0_tick(void *opaque)
{
    lm_kbd_pwm_tick(opaque, 0);
}
static void lm_kbd_pwm1_tick(void *opaque)
{
    lm_kbd_pwm_tick(opaque, 1);
}
static void lm_kbd_pwm2_tick(void *opaque)
{
    lm_kbd_pwm_tick(opaque, 2);
}

enum {
    LM832x_CMD_READ_ID		= 0x80, /* Read chip ID. */
    LM832x_CMD_WRITE_CFG	= 0x81, /* Set configuration item. */
    LM832x_CMD_READ_INT		= 0x82, /* Get interrupt status. */
    LM832x_CMD_RESET		= 0x83, /* Reset, same as external one */
    LM823x_CMD_WRITE_PULL_DOWN	= 0x84, /* Select GPIO pull-up/down. */
    LM832x_CMD_WRITE_PORT_SEL	= 0x85, /* Select GPIO in/out. */
    LM832x_CMD_WRITE_PORT_STATE	= 0x86, /* Set GPIO pull-up/down. */
    LM832x_CMD_READ_PORT_SEL	= 0x87, /* Get GPIO in/out. */
    LM832x_CMD_READ_PORT_STATE	= 0x88, /* Get GPIO pull-up/down. */
    LM832x_CMD_READ_FIFO	= 0x89, /* Read byte from FIFO. */
    LM832x_CMD_RPT_READ_FIFO	= 0x8a, /* Read FIFO (no increment). */
    LM832x_CMD_SET_ACTIVE	= 0x8b, /* Set active time. */
    LM832x_CMD_READ_ERROR	= 0x8c, /* Get error status. */
    LM832x_CMD_READ_ROTATOR	= 0x8e, /* Read rotator status. */
    LM832x_CMD_SET_DEBOUNCE	= 0x8f, /* Set debouncing time. */
    LM832x_CMD_SET_KEY_SIZE	= 0x90, /* Set keypad size. */
    LM832x_CMD_READ_KEY_SIZE	= 0x91, /* Get keypad size. */
    LM832x_CMD_READ_CFG		= 0x92, /* Get configuration item. */
    LM832x_CMD_WRITE_CLOCK	= 0x93, /* Set clock config. */
    LM832x_CMD_READ_CLOCK	= 0x94, /* Get clock config. */
    LM832x_CMD_PWM_WRITE	= 0x95, /* Write PWM script. */
    LM832x_CMD_PWM_START	= 0x96, /* Start PWM engine. */
    LM832x_CMD_PWM_STOP		= 0x97, /* Stop PWM engine. */
    LM832x_GENERAL_ERROR	= 0xff, /* There was one error.
                                           Previously was represented by -1
                                           This is not a command */
};

#define LM832x_MAX_KPX		8
#define LM832x_MAX_KPY		12

static uint8_t lm_kbd_read(LM823KbdState *s, int reg, int byte)
{
    int ret;

    switch (reg) {
    case LM832x_CMD_READ_ID:
        ret = 0x0400;
        break;

    case LM832x_CMD_READ_INT:
        ret = s->status;
        if (!(s->status & INT_NOINIT)) {
            s->status = 0;
            lm_kbd_irq_update(s);
        }
        break;

    case LM832x_CMD_READ_PORT_SEL:
        ret = s->gpio.dir;
        break;
    case LM832x_CMD_READ_PORT_STATE:
        ret = s->gpio.mask;
        break;

    case LM832x_CMD_READ_FIFO:
        if (s->kbd.len <= 1)
            return 0x00;

        /* Example response from the two commands after a INT_KEYPAD
         * interrupt caused by the key 0x3c being pressed:
         * RPT_READ_FIFO: 55 bc 00 4e ff 0a 50 08 00 29 d9 08 01 c9 01
         *     READ_FIFO: bc 00 00 4e ff 0a 50 08 00 29 d9 08 01 c9 01
         * RPT_READ_FIFO: bc 00 00 4e ff 0a 50 08 00 29 d9 08 01 c9 01
         *
         * 55 is the code of the key release event serviced in the previous
         * interrupt handling.
         *
         * TODO: find out whether the FIFO is advanced a single character
         * before reading every byte or the whole size of the FIFO at the
         * last LM832x_CMD_READ_FIFO.  This affects LM832x_CMD_RPT_READ_FIFO
         * output in cases where there are more than one event in the FIFO.
         * Assume 0xbc and 0x3c events are in the FIFO:
         * RPT_READ_FIFO: 55 bc 3c 00 4e ff 0a 50 08 00 29 d9 08 01 c9
         *     READ_FIFO: bc 3c 00 00 4e ff 0a 50 08 00 29 d9 08 01 c9
         * Does RPT_READ_FIFO now return 0xbc and 0x3c or only 0x3c?
         */
        s->kbd.start ++;
        s->kbd.start &= sizeof(s->kbd.fifo) - 1;
        s->kbd.len --;

        return s->kbd.fifo[s->kbd.start];
    case LM832x_CMD_RPT_READ_FIFO:
        if (byte >= s->kbd.len)
            return 0x00;

        return s->kbd.fifo[(s->kbd.start + byte) & (sizeof(s->kbd.fifo) - 1)];

    case LM832x_CMD_READ_ERROR:
        return s->error;

    case LM832x_CMD_READ_ROTATOR:
        return 0;

    case LM832x_CMD_READ_KEY_SIZE:
        return s->kbd.size;

    case LM832x_CMD_READ_CFG:
        return s->config & 0xf;

    case LM832x_CMD_READ_CLOCK:
        return (s->clock & 0xfc) | 2;

    default:
        lm_kbd_error(s, ERR_CMDUNK);
        fprintf(stderr, "%s: unknown command %02x\n", __func__, reg);
        return 0x00;
    }

    return ret >> (byte << 3);
}

static void lm_kbd_write(LM823KbdState *s, int reg, int byte, uint8_t value)
{
    switch (reg) {
    case LM832x_CMD_WRITE_CFG:
        s->config = value;
        /* This must be done whenever s->mux.in is updated (never).  */
        if ((s->config >> 1) & 1)			/* MUX1EN */
            qemu_set_irq(s->mux.out[0], s->mux.in[0][(s->config >> 0) & 1]);
        if ((s->config >> 3) & 1)			/* MUX2EN */
            qemu_set_irq(s->mux.out[0], s->mux.in[0][(s->config >> 2) & 1]);
        /* TODO: check that this is issued only following the chip reset
         * and not in the middle of operation and that it is followed by
         * the GPIO ports re-resablishing through WRITE_PORT_SEL and
         * WRITE_PORT_STATE (using a timer perhaps) and otherwise output
         * warnings.  */
        s->status = 0;
        lm_kbd_irq_update(s);
        s->kbd.len = 0;
        s->kbd.start = 0;
        s->reg = LM832x_GENERAL_ERROR;
        break;

    case LM832x_CMD_RESET:
        if (value == 0xaa)
            lm_kbd_reset(DEVICE(s));
        else
            lm_kbd_error(s, ERR_BADPAR);
        s->reg = LM832x_GENERAL_ERROR;
        break;

    case LM823x_CMD_WRITE_PULL_DOWN:
        if (!byte)
            s->gpio.pull = value;
        else {
            s->gpio.pull |= value << 8;
            lm_kbd_gpio_update(s);
            s->reg = LM832x_GENERAL_ERROR;
        }
        break;
    case LM832x_CMD_WRITE_PORT_SEL:
        if (!byte)
            s->gpio.dir = value;
        else {
            s->gpio.dir |= value << 8;
            lm_kbd_gpio_update(s);
            s->reg = LM832x_GENERAL_ERROR;
        }
        break;
    case LM832x_CMD_WRITE_PORT_STATE:
        if (!byte)
            s->gpio.mask = value;
        else {
            s->gpio.mask |= value << 8;
            lm_kbd_gpio_update(s);
            s->reg = LM832x_GENERAL_ERROR;
        }
        break;

    case LM832x_CMD_SET_ACTIVE:
        s->acttime = value;
        s->reg = LM832x_GENERAL_ERROR;
        break;

    case LM832x_CMD_SET_DEBOUNCE:
        s->kbd.dbnctime = value;
        s->reg = LM832x_GENERAL_ERROR;
        if (!value)
            lm_kbd_error(s, ERR_BADPAR);
        break;

    case LM832x_CMD_SET_KEY_SIZE:
        s->kbd.size = value;
        s->reg = LM832x_GENERAL_ERROR;
        if (
                        (value & 0xf) < 3 || (value & 0xf) > LM832x_MAX_KPY ||
                        (value >> 4) < 3 || (value >> 4) > LM832x_MAX_KPX)
            lm_kbd_error(s, ERR_BADPAR);
        break;

    case LM832x_CMD_WRITE_CLOCK:
        s->clock = value;
        s->reg = LM832x_GENERAL_ERROR;
        if ((value & 3) && (value & 3) != 3) {
            lm_kbd_error(s, ERR_BADPAR);
            fprintf(stderr, "%s: invalid clock setting in RCPWM\n",
                            __func__);
        }
        /* TODO: Validate that the command is only issued once */
        break;

    case LM832x_CMD_PWM_WRITE:
        if (byte == 0) {
            if (!(value & 3) || (value >> 2) > 59) {
                lm_kbd_error(s, ERR_BADPAR);
                s->reg = LM832x_GENERAL_ERROR;
                break;
            }

            s->pwm.faddr = value;
            s->pwm.file[s->pwm.faddr] = 0;
        } else if (byte == 1) {
            s->pwm.file[s->pwm.faddr] |= value << 8;
        } else if (byte == 2) {
            s->pwm.file[s->pwm.faddr] |= value << 0;
            s->reg = LM832x_GENERAL_ERROR;
        }
        break;
    case LM832x_CMD_PWM_START:
        s->reg = LM832x_GENERAL_ERROR;
        if (!(value & 3) || (value >> 2) > 59) {
            lm_kbd_error(s, ERR_BADPAR);
            break;
        }

        s->pwm.addr[(value & 3) - 1] = value >> 2;
        lm_kbd_pwm_start(s, (value & 3) - 1);
        break;
    case LM832x_CMD_PWM_STOP:
        s->reg = LM832x_GENERAL_ERROR;
        if (!(value & 3)) {
            lm_kbd_error(s, ERR_BADPAR);
            break;
        }

        timer_del(s->pwm.tm[(value & 3) - 1]);
        break;

    case LM832x_GENERAL_ERROR:
        lm_kbd_error(s, ERR_BADPAR);
        break;
    default:
        lm_kbd_error(s, ERR_CMDUNK);
        fprintf(stderr, "%s: unknown command %02x\n", __func__, reg);
        break;
    }
}

static int lm_i2c_event(I2CSlave *i2c, enum i2c_event event)
{
    LM823KbdState *s = LM8323(i2c);

    switch (event) {
    case I2C_START_RECV:
    case I2C_START_SEND:
        s->i2c_cycle = 0;
        s->i2c_dir = (event == I2C_START_SEND);
        break;

    default:
        break;
    }

    return 0;
}

static uint8_t lm_i2c_rx(I2CSlave *i2c)
{
    LM823KbdState *s = LM8323(i2c);

    return lm_kbd_read(s, s->reg, s->i2c_cycle ++);
}

static int lm_i2c_tx(I2CSlave *i2c, uint8_t data)
{
    LM823KbdState *s = LM8323(i2c);

    if (!s->i2c_cycle)
        s->reg = data;
    else
        lm_kbd_write(s, s->reg, s->i2c_cycle - 1, data);
    s->i2c_cycle ++;

    return 0;
}

static int lm_kbd_post_load(void *opaque, int version_id)
{
    LM823KbdState *s = opaque;

    lm_kbd_irq_update(s);
    lm_kbd_gpio_update(s);

    return 0;
}

static const VMStateDescription vmstate_lm_kbd = {
    .name = "LM8323",
    .version_id = 0,
    .minimum_version_id = 0,
    .post_load = lm_kbd_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_I2C_SLAVE(parent_obj, LM823KbdState),
        VMSTATE_UINT8(i2c_dir, LM823KbdState),
        VMSTATE_UINT8(i2c_cycle, LM823KbdState),
        VMSTATE_UINT8(reg, LM823KbdState),
        VMSTATE_UINT8(config, LM823KbdState),
        VMSTATE_UINT8(status, LM823KbdState),
        VMSTATE_UINT8(acttime, LM823KbdState),
        VMSTATE_UINT8(error, LM823KbdState),
        VMSTATE_UINT8(clock, LM823KbdState),
        VMSTATE_UINT16(gpio.pull, LM823KbdState),
        VMSTATE_UINT16(gpio.mask, LM823KbdState),
        VMSTATE_UINT16(gpio.dir, LM823KbdState),
        VMSTATE_UINT16(gpio.level, LM823KbdState),
        VMSTATE_UINT8(kbd.dbnctime, LM823KbdState),
        VMSTATE_UINT8(kbd.size, LM823KbdState),
        VMSTATE_UINT8(kbd.start, LM823KbdState),
        VMSTATE_UINT8(kbd.len, LM823KbdState),
        VMSTATE_BUFFER(kbd.fifo, LM823KbdState),
        VMSTATE_UINT16_ARRAY(pwm.file, LM823KbdState, 256),
        VMSTATE_UINT8(pwm.faddr, LM823KbdState),
        VMSTATE_BUFFER(pwm.addr, LM823KbdState),
        VMSTATE_TIMER_PTR_ARRAY(pwm.tm, LM823KbdState, 3),
        VMSTATE_END_OF_LIST()
    }
};


static void lm8323_realize(DeviceState *dev, Error **errp)
{
    LM823KbdState *s = LM8323(dev);

    s->model = 0x8323;
    s->pwm.tm[0] = timer_new_ns(QEMU_CLOCK_VIRTUAL, lm_kbd_pwm0_tick, s);
    s->pwm.tm[1] = timer_new_ns(QEMU_CLOCK_VIRTUAL, lm_kbd_pwm1_tick, s);
    s->pwm.tm[2] = timer_new_ns(QEMU_CLOCK_VIRTUAL, lm_kbd_pwm2_tick, s);
    qdev_init_gpio_out(dev, &s->nirq, 1);
}

void lm832x_key_event(DeviceState *dev, int key, int state)
{
    LM823KbdState *s = LM8323(dev);

    if ((s->status & INT_ERROR) && (s->error & ERR_FIFOOVR))
        return;

    if (s->kbd.len >= sizeof(s->kbd.fifo)) {
        lm_kbd_error(s, ERR_FIFOOVR);
        return;
    }

    s->kbd.fifo[(s->kbd.start + s->kbd.len ++) & (sizeof(s->kbd.fifo) - 1)] =
            key | (state << 7);

    /* We never set ERR_KEYOVR because we support multiple keys fine.  */
    s->status |= INT_KEYPAD;
    lm_kbd_irq_update(s);
}

static void lm8323_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);

    dc->reset = lm_kbd_reset;
    dc->realize = lm8323_realize;
    k->event = lm_i2c_event;
    k->recv = lm_i2c_rx;
    k->send = lm_i2c_tx;
    dc->vmsd = &vmstate_lm_kbd;
}

static const TypeInfo lm8323_info = {
    .name          = TYPE_LM8323,
    .parent        = TYPE_I2C_SLAVE,
    .instance_size = sizeof(LM823KbdState),
    .class_init    = lm8323_class_init,
};

static void lm832x_register_types(void)
{
    type_register_static(&lm8323_info);
}

type_init(lm832x_register_types)
Commit	Line	Data
1d4e547b AZ	1	/*
	2	* National Semiconductor LM8322/8323 GPIO keyboard & PWM chips.
	3	*
	4	* Copyright (C) 2008 Nokia Corporation
	5	* Written by Andrzej Zaborowski <andrew@openedhand.com>
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 or
	10	* (at your option) version 3 of the License.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
fad6cb1a	17	* You should have received a copy of the GNU General Public License along
8167ee88	18	* with this program; if not, see <http://www.gnu.org/licenses/>.
1d4e547b AZ	19	*/
1d4e547b AZ	20
0430891c	21	#include "qemu/osdep.h"
0d09e41a	22	#include "hw/i2c/i2c.h"
64552b6b	23	#include "hw/irq.h"
d6454270	24	#include "migration/vmstate.h"
0b8fa32f	25	#include "qemu/module.h"
1de7afc9	26	#include "qemu/timer.h"
28ecbaee	27	#include "ui/console.h"
db1015e9	28	#include "qom/object.h"
1d4e547b	29
933069eb	30	#define TYPE_LM8323 "lm8323"
8063396b	31	OBJECT_DECLARE_SIMPLE_TYPE(LM823KbdState, LM8323)
933069eb	32
db1015e9	33	struct LM823KbdState {
933069eb AF	34	I2CSlave parent_obj;
933069eb AF	35
e69f0602 JQ	36	uint8_t i2c_dir;
	37	uint8_t i2c_cycle;
	38	uint8_t reg;
1d4e547b AZ	39
	40	qemu_irq nirq;
	41	uint16_t model;
	42
	43	struct {
	44	qemu_irq out[2];
	45	int in[2][2];
	46	} mux;
	47
	48	uint8_t config;
	49	uint8_t status;
	50	uint8_t acttime;
	51	uint8_t error;
	52	uint8_t clock;
	53
	54	struct {
	55	uint16_t pull;
	56	uint16_t mask;
	57	uint16_t dir;
	58	uint16_t level;
	59	qemu_irq out[16];
	60	} gpio;
	61
	62	struct {
	63	uint8_t dbnctime;
	64	uint8_t size;
e69f0602 JQ	65	uint8_t start;
e69f0602 JQ	66	uint8_t len;
1d4e547b AZ	67	uint8_t fifo[16];
	68	} kbd;
	69
	70	struct {
	71	uint16_t file[256];
7d37435b	72	uint8_t faddr;
1d4e547b AZ	73	uint8_t addr[3];
	74	QEMUTimer *tm[3];
	75	} pwm;
db1015e9	76	};
1d4e547b AZ	77
	78	#define INT_KEYPAD (1 << 0)
	79	#define INT_ERROR (1 << 3)
	80	#define INT_NOINIT (1 << 4)
	81	#define INT_PWMEND(n) (1 << (5 + n))
	82
	83	#define ERR_BADPAR (1 << 0)
	84	#define ERR_CMDUNK (1 << 1)
	85	#define ERR_KEYOVR (1 << 2)
	86	#define ERR_FIFOOVR (1 << 6)
	87
bc24a225	88	static void lm_kbd_irq_update(LM823KbdState *s)
1d4e547b AZ	89	{
	90	qemu_set_irq(s->nirq, !s->status);
	91	}
	92
bc24a225	93	static void lm_kbd_gpio_update(LM823KbdState *s)
1d4e547b AZ	94	{
	95	}
	96
f7030d00	97	static void lm_kbd_reset(DeviceState *dev)
1d4e547b	98	{
f7030d00 PMD	99	LM823KbdState *s = LM8323(dev);
f7030d00 PMD	100
1d4e547b AZ	101	s->config = 0x80;
	102	s->status = INT_NOINIT;
	103	s->acttime = 125;
	104	s->kbd.dbnctime = 3;
	105	s->kbd.size = 0x33;
	106	s->clock = 0x08;
	107
	108	lm_kbd_irq_update(s);
	109	lm_kbd_gpio_update(s);
	110	}
	111
bc24a225	112	static void lm_kbd_error(LM823KbdState *s, int err)
1d4e547b AZ	113	{
	114	s->error \|= err;
	115	s->status \|= INT_ERROR;
	116	lm_kbd_irq_update(s);
	117	}
	118
bc24a225	119	static void lm_kbd_pwm_tick(LM823KbdState *s, int line)
1d4e547b AZ	120	{
	121	}
	122
bc24a225	123	static void lm_kbd_pwm_start(LM823KbdState *s, int line)
1d4e547b AZ	124	{
	125	lm_kbd_pwm_tick(s, line);
	126	}
	127
	128	static void lm_kbd_pwm0_tick(void *opaque)
	129	{
	130	lm_kbd_pwm_tick(opaque, 0);
	131	}
	132	static void lm_kbd_pwm1_tick(void *opaque)
	133	{
	134	lm_kbd_pwm_tick(opaque, 1);
	135	}
	136	static void lm_kbd_pwm2_tick(void *opaque)
	137	{
	138	lm_kbd_pwm_tick(opaque, 2);
	139	}
	140
	141	enum {
	142	LM832x_CMD_READ_ID = 0x80, /* Read chip ID. */
	143	LM832x_CMD_WRITE_CFG = 0x81, /* Set configuration item. */
	144	LM832x_CMD_READ_INT = 0x82, /* Get interrupt status. */
	145	LM832x_CMD_RESET = 0x83, /* Reset, same as external one */
	146	LM823x_CMD_WRITE_PULL_DOWN = 0x84, /* Select GPIO pull-up/down. */
	147	LM832x_CMD_WRITE_PORT_SEL = 0x85, /* Select GPIO in/out. */
	148	LM832x_CMD_WRITE_PORT_STATE = 0x86, /* Set GPIO pull-up/down. */
	149	LM832x_CMD_READ_PORT_SEL = 0x87, /* Get GPIO in/out. */
	150	LM832x_CMD_READ_PORT_STATE = 0x88, /* Get GPIO pull-up/down. */
	151	LM832x_CMD_READ_FIFO = 0x89, /* Read byte from FIFO. */
	152	LM832x_CMD_RPT_READ_FIFO = 0x8a, /* Read FIFO (no increment). */
	153	LM832x_CMD_SET_ACTIVE = 0x8b, /* Set active time. */
	154	LM832x_CMD_READ_ERROR = 0x8c, /* Get error status. */
	155	LM832x_CMD_READ_ROTATOR = 0x8e, /* Read rotator status. */
	156	LM832x_CMD_SET_DEBOUNCE = 0x8f, /* Set debouncing time. */
	157	LM832x_CMD_SET_KEY_SIZE = 0x90, /* Set keypad size. */
	158	LM832x_CMD_READ_KEY_SIZE = 0x91, /* Get keypad size. */
	159	LM832x_CMD_READ_CFG = 0x92, /* Get configuration item. */
	160	LM832x_CMD_WRITE_CLOCK = 0x93, /* Set clock config. */
	161	LM832x_CMD_READ_CLOCK = 0x94, /* Get clock config. */
	162	LM832x_CMD_PWM_WRITE = 0x95, /* Write PWM script. */
	163	LM832x_CMD_PWM_START = 0x96, /* Start PWM engine. */
	164	LM832x_CMD_PWM_STOP = 0x97, /* Stop PWM engine. */
e69f0602 JQ	165	LM832x_GENERAL_ERROR = 0xff, /* There was one error.
	166	Previously was represented by -1
	167	This is not a command */
1d4e547b AZ	168	};
	169
	170	#define LM832x_MAX_KPX 8
	171	#define LM832x_MAX_KPY 12
	172
bc24a225	173	static uint8_t lm_kbd_read(LM823KbdState *s, int reg, int byte)
1d4e547b AZ	174	{
	175	int ret;
	176
	177	switch (reg) {
	178	case LM832x_CMD_READ_ID:
	179	ret = 0x0400;
	180	break;
	181
	182	case LM832x_CMD_READ_INT:
	183	ret = s->status;
	184	if (!(s->status & INT_NOINIT)) {
	185	s->status = 0;
	186	lm_kbd_irq_update(s);
	187	}
	188	break;
	189
	190	case LM832x_CMD_READ_PORT_SEL:
	191	ret = s->gpio.dir;
	192	break;
	193	case LM832x_CMD_READ_PORT_STATE:
	194	ret = s->gpio.mask;
	195	break;
	196
	197	case LM832x_CMD_READ_FIFO:
	198	if (s->kbd.len <= 1)
	199	return 0x00;
	200
	201	/* Example response from the two commands after a INT_KEYPAD
	202	* interrupt caused by the key 0x3c being pressed:
	203	* RPT_READ_FIFO: 55 bc 00 4e ff 0a 50 08 00 29 d9 08 01 c9 01
	204	* READ_FIFO: bc 00 00 4e ff 0a 50 08 00 29 d9 08 01 c9 01
	205	* RPT_READ_FIFO: bc 00 00 4e ff 0a 50 08 00 29 d9 08 01 c9 01
	206	*
	207	* 55 is the code of the key release event serviced in the previous
	208	* interrupt handling.
	209	*
	210	* TODO: find out whether the FIFO is advanced a single character
	211	* before reading every byte or the whole size of the FIFO at the
	212	* last LM832x_CMD_READ_FIFO. This affects LM832x_CMD_RPT_READ_FIFO
	213	* output in cases where there are more than one event in the FIFO.
	214	* Assume 0xbc and 0x3c events are in the FIFO:
	215	* RPT_READ_FIFO: 55 bc 3c 00 4e ff 0a 50 08 00 29 d9 08 01 c9
	216	* READ_FIFO: bc 3c 00 00 4e ff 0a 50 08 00 29 d9 08 01 c9
	217	* Does RPT_READ_FIFO now return 0xbc and 0x3c or only 0x3c?
	218	*/
	219	s->kbd.start ++;
	220	s->kbd.start &= sizeof(s->kbd.fifo) - 1;
	221	s->kbd.len --;
	222
	223	return s->kbd.fifo[s->kbd.start];
	224	case LM832x_CMD_RPT_READ_FIFO:
	225	if (byte >= s->kbd.len)
	226	return 0x00;
	227
	228	return s->kbd.fifo[(s->kbd.start + byte) & (sizeof(s->kbd.fifo) - 1)];
	229
	230	case LM832x_CMD_READ_ERROR:
	231	return s->error;
	232
	233	case LM832x_CMD_READ_ROTATOR:
	234	return 0;
	235
	236	case LM832x_CMD_READ_KEY_SIZE:
	237	return s->kbd.size;
238
239	case LM832x_CMD_READ_CFG:
240	return s->config & 0xf;
241
242	case LM832x_CMD_READ_CLOCK:
243	return (s->clock & 0xfc) \| 2;
244
245	default:
246	lm_kbd_error(s, ERR_CMDUNK);
a89f364a	247	fprintf(stderr, "%s: unknown command %02x\n", __func__, reg);
1d4e547b AZ	248	return 0x00;
	249	}
	250
	251	return ret >> (byte << 3);
	252	}
	253
bc24a225	254	static void lm_kbd_write(LM823KbdState *s, int reg, int byte, uint8_t value)
1d4e547b AZ	255	{
	256	switch (reg) {
	257	case LM832x_CMD_WRITE_CFG:
	258	s->config = value;
	259	/* This must be done whenever s->mux.in is updated (never). */
	260	if ((s->config >> 1) & 1) /* MUX1EN */
	261	qemu_set_irq(s->mux.out[0], s->mux.in[0][(s->config >> 0) & 1]);
	262	if ((s->config >> 3) & 1) /* MUX2EN */
	263	qemu_set_irq(s->mux.out[0], s->mux.in[0][(s->config >> 2) & 1]);
	264	/* TODO: check that this is issued only following the chip reset
	265	* and not in the middle of operation and that it is followed by
	266	* the GPIO ports re-resablishing through WRITE_PORT_SEL and
	267	* WRITE_PORT_STATE (using a timer perhaps) and otherwise output
	268	* warnings. */
	269	s->status = 0;
	270	lm_kbd_irq_update(s);
	271	s->kbd.len = 0;
	272	s->kbd.start = 0;
e69f0602	273	s->reg = LM832x_GENERAL_ERROR;
1d4e547b AZ	274	break;
	275
	276	case LM832x_CMD_RESET:
	277	if (value == 0xaa)
f7030d00	278	lm_kbd_reset(DEVICE(s));
1d4e547b AZ	279	else
1d4e547b AZ	280	lm_kbd_error(s, ERR_BADPAR);
e69f0602	281	s->reg = LM832x_GENERAL_ERROR;
1d4e547b AZ	282	break;
	283
	284	case LM823x_CMD_WRITE_PULL_DOWN:
	285	if (!byte)
	286	s->gpio.pull = value;
	287	else {
	288	s->gpio.pull \|= value << 8;
	289	lm_kbd_gpio_update(s);
e69f0602	290	s->reg = LM832x_GENERAL_ERROR;
1d4e547b AZ	291	}
	292	break;
	293	case LM832x_CMD_WRITE_PORT_SEL:
	294	if (!byte)
	295	s->gpio.dir = value;
	296	else {
	297	s->gpio.dir \|= value << 8;
	298	lm_kbd_gpio_update(s);
e69f0602	299	s->reg = LM832x_GENERAL_ERROR;
1d4e547b AZ	300	}
	301	break;
	302	case LM832x_CMD_WRITE_PORT_STATE:
	303	if (!byte)
	304	s->gpio.mask = value;
	305	else {
	306	s->gpio.mask \|= value << 8;
	307	lm_kbd_gpio_update(s);
e69f0602	308	s->reg = LM832x_GENERAL_ERROR;
1d4e547b AZ	309	}
	310	break;
	311
	312	case LM832x_CMD_SET_ACTIVE:
	313	s->acttime = value;
e69f0602	314	s->reg = LM832x_GENERAL_ERROR;
1d4e547b AZ	315	break;
	316
	317	case LM832x_CMD_SET_DEBOUNCE:
	318	s->kbd.dbnctime = value;
e69f0602	319	s->reg = LM832x_GENERAL_ERROR;
1d4e547b AZ	320	if (!value)
	321	lm_kbd_error(s, ERR_BADPAR);
	322	break;
	323
	324	case LM832x_CMD_SET_KEY_SIZE:
	325	s->kbd.size = value;
e69f0602	326	s->reg = LM832x_GENERAL_ERROR;
1d4e547b AZ	327	if (
	328	(value & 0xf) < 3 \|\| (value & 0xf) > LM832x_MAX_KPY \|\|
	329	(value >> 4) < 3 \|\| (value >> 4) > LM832x_MAX_KPX)
	330	lm_kbd_error(s, ERR_BADPAR);
	331	break;
	332
	333	case LM832x_CMD_WRITE_CLOCK:
	334	s->clock = value;
e69f0602	335	s->reg = LM832x_GENERAL_ERROR;
1d4e547b AZ	336	if ((value & 3) && (value & 3) != 3) {
	337	lm_kbd_error(s, ERR_BADPAR);
	338	fprintf(stderr, "%s: invalid clock setting in RCPWM\n",
a89f364a	339	__func__);
1d4e547b AZ	340	}
	341	/* TODO: Validate that the command is only issued once */
	342	break;
	343
	344	case LM832x_CMD_PWM_WRITE:
	345	if (byte == 0) {
	346	if (!(value & 3) \|\| (value >> 2) > 59) {
	347	lm_kbd_error(s, ERR_BADPAR);
e69f0602	348	s->reg = LM832x_GENERAL_ERROR;
1d4e547b AZ	349	break;
	350	}
	351
	352	s->pwm.faddr = value;
	353	s->pwm.file[s->pwm.faddr] = 0;
	354	} else if (byte == 1) {
	355	s->pwm.file[s->pwm.faddr] \|= value << 8;
	356	} else if (byte == 2) {
	357	s->pwm.file[s->pwm.faddr] \|= value << 0;
e69f0602	358	s->reg = LM832x_GENERAL_ERROR;
1d4e547b AZ	359	}
	360	break;
	361	case LM832x_CMD_PWM_START:
e69f0602	362	s->reg = LM832x_GENERAL_ERROR;
1d4e547b AZ	363	if (!(value & 3) \|\| (value >> 2) > 59) {
	364	lm_kbd_error(s, ERR_BADPAR);
	365	break;
	366	}
	367
	368	s->pwm.addr[(value & 3) - 1] = value >> 2;
	369	lm_kbd_pwm_start(s, (value & 3) - 1);
	370	break;
	371	case LM832x_CMD_PWM_STOP:
e69f0602	372	s->reg = LM832x_GENERAL_ERROR;
1d4e547b AZ	373	if (!(value & 3)) {
	374	lm_kbd_error(s, ERR_BADPAR);
	375	break;
	376	}
	377
bc72ad67	378	timer_del(s->pwm.tm[(value & 3) - 1]);
1d4e547b AZ	379	break;
1d4e547b AZ	380
e69f0602	381	case LM832x_GENERAL_ERROR:
1d4e547b AZ	382	lm_kbd_error(s, ERR_BADPAR);
	383	break;
	384	default:
	385	lm_kbd_error(s, ERR_CMDUNK);
a89f364a	386	fprintf(stderr, "%s: unknown command %02x\n", __func__, reg);
1d4e547b AZ	387	break;
	388	}
	389	}
	390
d307c28c	391	static int lm_i2c_event(I2CSlave *i2c, enum i2c_event event)
1d4e547b	392	{
933069eb	393	LM823KbdState *s = LM8323(i2c);
1d4e547b AZ	394
	395	switch (event) {
	396	case I2C_START_RECV:
	397	case I2C_START_SEND:
	398	s->i2c_cycle = 0;
	399	s->i2c_dir = (event == I2C_START_SEND);
	400	break;
	401
	402	default:
	403	break;
	404	}
d307c28c CM	405
d307c28c CM	406	return 0;
1d4e547b AZ	407	}
1d4e547b AZ	408
2ac4c5f4	409	static uint8_t lm_i2c_rx(I2CSlave *i2c)
1d4e547b	410	{
933069eb	411	LM823KbdState *s = LM8323(i2c);
1d4e547b AZ	412
	413	return lm_kbd_read(s, s->reg, s->i2c_cycle ++);
	414	}
	415
9e07bdf8	416	static int lm_i2c_tx(I2CSlave *i2c, uint8_t data)
1d4e547b	417	{
933069eb	418	LM823KbdState *s = LM8323(i2c);
1d4e547b AZ	419
	420	if (!s->i2c_cycle)
	421	s->reg = data;
	422	else
	423	lm_kbd_write(s, s->reg, s->i2c_cycle - 1, data);
	424	s->i2c_cycle ++;
	425
	426	return 0;
	427	}
	428
aa1e3b28	429	static int lm_kbd_post_load(void *opaque, int version_id)
1d4e547b	430	{
aa1e3b28	431	LM823KbdState *s = opaque;
1d4e547b AZ	432
	433	lm_kbd_irq_update(s);
	434	lm_kbd_gpio_update(s);
	435
	436	return 0;
	437	}
	438
aa1e3b28 JQ	439	static const VMStateDescription vmstate_lm_kbd = {
	440	.name = "LM8323",
	441	.version_id = 0,
	442	.minimum_version_id = 0,
aa1e3b28	443	.post_load = lm_kbd_post_load,
8f1e884b	444	.fields = (VMStateField[]) {
933069eb	445	VMSTATE_I2C_SLAVE(parent_obj, LM823KbdState),
aa1e3b28 JQ	446	VMSTATE_UINT8(i2c_dir, LM823KbdState),
	447	VMSTATE_UINT8(i2c_cycle, LM823KbdState),
	448	VMSTATE_UINT8(reg, LM823KbdState),
	449	VMSTATE_UINT8(config, LM823KbdState),
	450	VMSTATE_UINT8(status, LM823KbdState),
	451	VMSTATE_UINT8(acttime, LM823KbdState),
	452	VMSTATE_UINT8(error, LM823KbdState),
	453	VMSTATE_UINT8(clock, LM823KbdState),
	454	VMSTATE_UINT16(gpio.pull, LM823KbdState),
	455	VMSTATE_UINT16(gpio.mask, LM823KbdState),
	456	VMSTATE_UINT16(gpio.dir, LM823KbdState),
	457	VMSTATE_UINT16(gpio.level, LM823KbdState),
	458	VMSTATE_UINT8(kbd.dbnctime, LM823KbdState),
	459	VMSTATE_UINT8(kbd.size, LM823KbdState),
	460	VMSTATE_UINT8(kbd.start, LM823KbdState),
	461	VMSTATE_UINT8(kbd.len, LM823KbdState),
	462	VMSTATE_BUFFER(kbd.fifo, LM823KbdState),
	463	VMSTATE_UINT16_ARRAY(pwm.file, LM823KbdState, 256),
	464	VMSTATE_UINT8(pwm.faddr, LM823KbdState),
	465	VMSTATE_BUFFER(pwm.addr, LM823KbdState),
e720677e	466	VMSTATE_TIMER_PTR_ARRAY(pwm.tm, LM823KbdState, 3),
aa1e3b28 JQ	467	VMSTATE_END_OF_LIST()
	468	}
	469	};
	470
	471
c8c9e103	472	static void lm8323_realize(DeviceState dev, Error *errp)
1d4e547b	473	{
c8c9e103	474	LM823KbdState *s = LM8323(dev);
1d4e547b	475
1d4e547b	476	s->model = 0x8323;
bc72ad67 AB	477	s->pwm.tm[0] = timer_new_ns(QEMU_CLOCK_VIRTUAL, lm_kbd_pwm0_tick, s);
	478	s->pwm.tm[1] = timer_new_ns(QEMU_CLOCK_VIRTUAL, lm_kbd_pwm1_tick, s);
	479	s->pwm.tm[2] = timer_new_ns(QEMU_CLOCK_VIRTUAL, lm_kbd_pwm2_tick, s);
c8c9e103	480	qdev_init_gpio_out(dev, &s->nirq, 1);
1d4e547b AZ	481	}
1d4e547b AZ	482
c4f05c8c	483	void lm832x_key_event(DeviceState *dev, int key, int state)
1d4e547b	484	{
933069eb	485	LM823KbdState *s = LM8323(dev);
1d4e547b AZ	486
	487	if ((s->status & INT_ERROR) && (s->error & ERR_FIFOOVR))
	488	return;
	489
7442511c BS	490	if (s->kbd.len >= sizeof(s->kbd.fifo)) {
	491	lm_kbd_error(s, ERR_FIFOOVR);
	492	return;
	493	}
1d4e547b AZ	494
	495	s->kbd.fifo[(s->kbd.start + s->kbd.len ++) & (sizeof(s->kbd.fifo) - 1)] =
	496	key \| (state << 7);
	497
	498	/* We never set ERR_KEYOVR because we support multiple keys fine. */
	499	s->status \|= INT_KEYPAD;
	500	lm_kbd_irq_update(s);
	501	}
2d9401aa	502
b5ea9327 AL	503	static void lm8323_class_init(ObjectClass klass, void data)
b5ea9327 AL	504	{
39bffca2	505	DeviceClass *dc = DEVICE_CLASS(klass);
b5ea9327 AL	506	I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
b5ea9327 AL	507
f7030d00	508	dc->reset = lm_kbd_reset;
c8c9e103	509	dc->realize = lm8323_realize;
b5ea9327 AL	510	k->event = lm_i2c_event;
	511	k->recv = lm_i2c_rx;
	512	k->send = lm_i2c_tx;
39bffca2	513	dc->vmsd = &vmstate_lm_kbd;
b5ea9327 AL	514	}
b5ea9327 AL	515
8c43a6f0	516	static const TypeInfo lm8323_info = {
933069eb	517	.name = TYPE_LM8323,
39bffca2 AL	518	.parent = TYPE_I2C_SLAVE,
	519	.instance_size = sizeof(LM823KbdState),
	520	.class_init = lm8323_class_init,
2d9401aa PB	521	};
2d9401aa PB	522
83f7d43a	523	static void lm832x_register_types(void)
2d9401aa	524	{
39bffca2	525	type_register_static(&lm8323_info);
2d9401aa PB	526	}
2d9401aa PB	527
83f7d43a	528	type_init(lm832x_register_types)