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5fafdf24 1/*
69db0ac7 2 * Arm PrimeCell PL050 Keyboard / Mouse Interface
cdbdb648 3 *
9e61ec31 4 * Copyright (c) 2006-2007 CodeSourcery.
cdbdb648
PB
5 * Written by Paul Brook
6 *
8e31bf38 7 * This code is licensed under the GPL.
cdbdb648
PB
8 */
9
8ef94f0b 10#include "qemu/osdep.h"
83c9f4ca 11#include "hw/sysbus.h"
0d09e41a 12#include "hw/input/ps2.h"
03dd024f 13#include "qemu/log.h"
0b8fa32f 14#include "qemu/module.h"
cdbdb648 15
3e5dd364
AF
16#define TYPE_PL050 "pl050"
17#define PL050(obj) OBJECT_CHECK(PL050State, (obj), TYPE_PL050)
18
e607f25a 19typedef struct PL050State {
3e5dd364
AF
20 SysBusDevice parent_obj;
21
b8f7a738 22 MemoryRegion iomem;
cdbdb648 23 void *dev;
cdbdb648
PB
24 uint32_t cr;
25 uint32_t clk;
26 uint32_t last;
cdbdb648 27 int pending;
d537cf6c 28 qemu_irq irq;
3e5dd364 29 bool is_mouse;
e607f25a 30} PL050State;
cdbdb648 31
d6ac172a
PM
32static const VMStateDescription vmstate_pl050 = {
33 .name = "pl050",
e8945b4f
PM
34 .version_id = 2,
35 .minimum_version_id = 2,
d6ac172a 36 .fields = (VMStateField[]) {
e607f25a
AF
37 VMSTATE_UINT32(cr, PL050State),
38 VMSTATE_UINT32(clk, PL050State),
39 VMSTATE_UINT32(last, PL050State),
40 VMSTATE_INT32(pending, PL050State),
d6ac172a
PM
41 VMSTATE_END_OF_LIST()
42 }
43};
44
9e61ec31
PB
45#define PL050_TXEMPTY (1 << 6)
46#define PL050_TXBUSY (1 << 5)
47#define PL050_RXFULL (1 << 4)
48#define PL050_RXBUSY (1 << 3)
49#define PL050_RXPARITY (1 << 2)
50#define PL050_KMIC (1 << 1)
51#define PL050_KMID (1 << 0)
52
cdbdb648
PB
53static const unsigned char pl050_id[] =
54{ 0x50, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
55
56static void pl050_update(void *opaque, int level)
57{
e607f25a 58 PL050State *s = (PL050State *)opaque;
cdbdb648
PB
59 int raise;
60
61 s->pending = level;
62 raise = (s->pending && (s->cr & 0x10) != 0)
63 || (s->cr & 0x08) != 0;
d537cf6c 64 qemu_set_irq(s->irq, raise);
cdbdb648
PB
65}
66
a8170e5e 67static uint64_t pl050_read(void *opaque, hwaddr offset,
b8f7a738 68 unsigned size)
cdbdb648 69{
e607f25a 70 PL050State *s = (PL050State *)opaque;
cdbdb648
PB
71 if (offset >= 0xfe0 && offset < 0x1000)
72 return pl050_id[(offset - 0xfe0) >> 2];
73
74 switch (offset >> 2) {
75 case 0: /* KMICR */
76 return s->cr;
77 case 1: /* KMISTAT */
9e61ec31
PB
78 {
79 uint8_t val;
80 uint32_t stat;
81
82 val = s->last;
83 val = val ^ (val >> 4);
84 val = val ^ (val >> 2);
85 val = (val ^ (val >> 1)) & 1;
86
87 stat = PL050_TXEMPTY;
88 if (val)
89 stat |= PL050_RXPARITY;
90 if (s->pending)
91 stat |= PL050_RXFULL;
92
93 return stat;
cdbdb648
PB
94 }
95 case 2: /* KMIDATA */
96 if (s->pending)
97 s->last = ps2_read_data(s->dev);
98 return s->last;
99 case 3: /* KMICLKDIV */
100 return s->clk;
101 case 4: /* KMIIR */
102 return s->pending | 2;
103 default:
fbfecf43
PM
104 qemu_log_mask(LOG_GUEST_ERROR,
105 "pl050_read: Bad offset %x\n", (int)offset);
cdbdb648
PB
106 return 0;
107 }
108}
109
a8170e5e 110static void pl050_write(void *opaque, hwaddr offset,
b8f7a738 111 uint64_t value, unsigned size)
cdbdb648 112{
e607f25a 113 PL050State *s = (PL050State *)opaque;
cdbdb648
PB
114 switch (offset >> 2) {
115 case 0: /* KMICR */
116 s->cr = value;
117 pl050_update(s, s->pending);
118 /* ??? Need to implement the enable/disable bit. */
119 break;
120 case 2: /* KMIDATA */
121 /* ??? This should toggle the TX interrupt line. */
122 /* ??? This means kbd/mouse can block each other. */
123 if (s->is_mouse) {
124 ps2_write_mouse(s->dev, value);
125 } else {
126 ps2_write_keyboard(s->dev, value);
127 }
128 break;
129 case 3: /* KMICLKDIV */
130 s->clk = value;
131 return;
132 default:
fbfecf43
PM
133 qemu_log_mask(LOG_GUEST_ERROR,
134 "pl050_write: Bad offset %x\n", (int)offset);
cdbdb648
PB
135 }
136}
b8f7a738
AK
137static const MemoryRegionOps pl050_ops = {
138 .read = pl050_read,
139 .write = pl050_write,
140 .endianness = DEVICE_NATIVE_ENDIAN,
cdbdb648
PB
141};
142
988e501a 143static void pl050_realize(DeviceState *dev, Error **errp)
cdbdb648 144{
3e5dd364 145 PL050State *s = PL050(dev);
988e501a 146 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
cdbdb648 147
1437c94b 148 memory_region_init_io(&s->iomem, OBJECT(s), &pl050_ops, s, "pl050", 0x1000);
988e501a
MZ
149 sysbus_init_mmio(sbd, &s->iomem);
150 sysbus_init_irq(sbd, &s->irq);
3e5dd364 151 if (s->is_mouse) {
cdbdb648 152 s->dev = ps2_mouse_init(pl050_update, s);
3e5dd364 153 } else {
cdbdb648 154 s->dev = ps2_kbd_init(pl050_update, s);
3e5dd364 155 }
cdbdb648 156}
86394e96 157
3e5dd364 158static void pl050_keyboard_init(Object *obj)
86394e96 159{
3e5dd364 160 PL050State *s = PL050(obj);
86394e96 161
3e5dd364 162 s->is_mouse = false;
86394e96
PB
163}
164
3e5dd364 165static void pl050_mouse_init(Object *obj)
999e12bb 166{
3e5dd364 167 PL050State *s = PL050(obj);
999e12bb 168
3e5dd364 169 s->is_mouse = true;
999e12bb
AL
170}
171
8c43a6f0 172static const TypeInfo pl050_kbd_info = {
39bffca2 173 .name = "pl050_keyboard",
3e5dd364
AF
174 .parent = TYPE_PL050,
175 .instance_init = pl050_keyboard_init,
d6ac172a
PM
176};
177
3e5dd364
AF
178static const TypeInfo pl050_mouse_info = {
179 .name = "pl050_mouse",
180 .parent = TYPE_PL050,
181 .instance_init = pl050_mouse_init,
182};
183
184static void pl050_class_init(ObjectClass *oc, void *data)
999e12bb 185{
3e5dd364 186 DeviceClass *dc = DEVICE_CLASS(oc);
999e12bb 187
988e501a 188 dc->realize = pl050_realize;
39bffca2 189 dc->vmsd = &vmstate_pl050;
999e12bb
AL
190}
191
3e5dd364
AF
192static const TypeInfo pl050_type_info = {
193 .name = TYPE_PL050,
39bffca2 194 .parent = TYPE_SYS_BUS_DEVICE,
e607f25a 195 .instance_size = sizeof(PL050State),
3e5dd364
AF
196 .abstract = true,
197 .class_init = pl050_class_init,
d6ac172a
PM
198};
199
83f7d43a 200static void pl050_register_types(void)
86394e96 201{
3e5dd364 202 type_register_static(&pl050_type_info);
39bffca2
AL
203 type_register_static(&pl050_kbd_info);
204 type_register_static(&pl050_mouse_info);
86394e96
PB
205}
206
83f7d43a 207type_init(pl050_register_types)