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5fafdf24 1/*
69db0ac7 2 * Arm PrimeCell PL050 Keyboard / Mouse Interface
cdbdb648 3 *
9e61ec31 4 * Copyright (c) 2006-2007 CodeSourcery.
cdbdb648
PB
5 * Written by Paul Brook
6 *
8e31bf38 7 * This code is licensed under the GPL.
cdbdb648
PB
8 */
9
8ef94f0b 10#include "qemu/osdep.h"
83c9f4ca 11#include "hw/sysbus.h"
d6454270 12#include "migration/vmstate.h"
0d09e41a 13#include "hw/input/ps2.h"
64552b6b 14#include "hw/irq.h"
03dd024f 15#include "qemu/log.h"
0b8fa32f 16#include "qemu/module.h"
cdbdb648 17
3e5dd364
AF
18#define TYPE_PL050 "pl050"
19#define PL050(obj) OBJECT_CHECK(PL050State, (obj), TYPE_PL050)
20
e607f25a 21typedef struct PL050State {
3e5dd364
AF
22 SysBusDevice parent_obj;
23
b8f7a738 24 MemoryRegion iomem;
cdbdb648 25 void *dev;
cdbdb648
PB
26 uint32_t cr;
27 uint32_t clk;
28 uint32_t last;
cdbdb648 29 int pending;
d537cf6c 30 qemu_irq irq;
3e5dd364 31 bool is_mouse;
e607f25a 32} PL050State;
cdbdb648 33
d6ac172a
PM
34static const VMStateDescription vmstate_pl050 = {
35 .name = "pl050",
e8945b4f
PM
36 .version_id = 2,
37 .minimum_version_id = 2,
d6ac172a 38 .fields = (VMStateField[]) {
e607f25a
AF
39 VMSTATE_UINT32(cr, PL050State),
40 VMSTATE_UINT32(clk, PL050State),
41 VMSTATE_UINT32(last, PL050State),
42 VMSTATE_INT32(pending, PL050State),
d6ac172a
PM
43 VMSTATE_END_OF_LIST()
44 }
45};
46
9e61ec31
PB
47#define PL050_TXEMPTY (1 << 6)
48#define PL050_TXBUSY (1 << 5)
49#define PL050_RXFULL (1 << 4)
50#define PL050_RXBUSY (1 << 3)
51#define PL050_RXPARITY (1 << 2)
52#define PL050_KMIC (1 << 1)
53#define PL050_KMID (1 << 0)
54
cdbdb648
PB
55static const unsigned char pl050_id[] =
56{ 0x50, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
57
58static void pl050_update(void *opaque, int level)
59{
e607f25a 60 PL050State *s = (PL050State *)opaque;
cdbdb648
PB
61 int raise;
62
63 s->pending = level;
64 raise = (s->pending && (s->cr & 0x10) != 0)
65 || (s->cr & 0x08) != 0;
d537cf6c 66 qemu_set_irq(s->irq, raise);
cdbdb648
PB
67}
68
a8170e5e 69static uint64_t pl050_read(void *opaque, hwaddr offset,
b8f7a738 70 unsigned size)
cdbdb648 71{
e607f25a 72 PL050State *s = (PL050State *)opaque;
cdbdb648
PB
73 if (offset >= 0xfe0 && offset < 0x1000)
74 return pl050_id[(offset - 0xfe0) >> 2];
75
76 switch (offset >> 2) {
77 case 0: /* KMICR */
78 return s->cr;
79 case 1: /* KMISTAT */
9e61ec31
PB
80 {
81 uint8_t val;
82 uint32_t stat;
83
84 val = s->last;
85 val = val ^ (val >> 4);
86 val = val ^ (val >> 2);
87 val = (val ^ (val >> 1)) & 1;
88
89 stat = PL050_TXEMPTY;
90 if (val)
91 stat |= PL050_RXPARITY;
92 if (s->pending)
93 stat |= PL050_RXFULL;
94
95 return stat;
cdbdb648
PB
96 }
97 case 2: /* KMIDATA */
98 if (s->pending)
99 s->last = ps2_read_data(s->dev);
100 return s->last;
101 case 3: /* KMICLKDIV */
102 return s->clk;
103 case 4: /* KMIIR */
104 return s->pending | 2;
105 default:
fbfecf43
PM
106 qemu_log_mask(LOG_GUEST_ERROR,
107 "pl050_read: Bad offset %x\n", (int)offset);
cdbdb648
PB
108 return 0;
109 }
110}
111
a8170e5e 112static void pl050_write(void *opaque, hwaddr offset,
b8f7a738 113 uint64_t value, unsigned size)
cdbdb648 114{
e607f25a 115 PL050State *s = (PL050State *)opaque;
cdbdb648
PB
116 switch (offset >> 2) {
117 case 0: /* KMICR */
118 s->cr = value;
119 pl050_update(s, s->pending);
120 /* ??? Need to implement the enable/disable bit. */
121 break;
122 case 2: /* KMIDATA */
123 /* ??? This should toggle the TX interrupt line. */
124 /* ??? This means kbd/mouse can block each other. */
125 if (s->is_mouse) {
126 ps2_write_mouse(s->dev, value);
127 } else {
128 ps2_write_keyboard(s->dev, value);
129 }
130 break;
131 case 3: /* KMICLKDIV */
132 s->clk = value;
133 return;
134 default:
fbfecf43
PM
135 qemu_log_mask(LOG_GUEST_ERROR,
136 "pl050_write: Bad offset %x\n", (int)offset);
cdbdb648
PB
137 }
138}
b8f7a738
AK
139static const MemoryRegionOps pl050_ops = {
140 .read = pl050_read,
141 .write = pl050_write,
142 .endianness = DEVICE_NATIVE_ENDIAN,
cdbdb648
PB
143};
144
988e501a 145static void pl050_realize(DeviceState *dev, Error **errp)
cdbdb648 146{
3e5dd364 147 PL050State *s = PL050(dev);
988e501a 148 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
cdbdb648 149
1437c94b 150 memory_region_init_io(&s->iomem, OBJECT(s), &pl050_ops, s, "pl050", 0x1000);
988e501a
MZ
151 sysbus_init_mmio(sbd, &s->iomem);
152 sysbus_init_irq(sbd, &s->irq);
3e5dd364 153 if (s->is_mouse) {
cdbdb648 154 s->dev = ps2_mouse_init(pl050_update, s);
3e5dd364 155 } else {
cdbdb648 156 s->dev = ps2_kbd_init(pl050_update, s);
3e5dd364 157 }
cdbdb648 158}
86394e96 159
3e5dd364 160static void pl050_keyboard_init(Object *obj)
86394e96 161{
3e5dd364 162 PL050State *s = PL050(obj);
86394e96 163
3e5dd364 164 s->is_mouse = false;
86394e96
PB
165}
166
3e5dd364 167static void pl050_mouse_init(Object *obj)
999e12bb 168{
3e5dd364 169 PL050State *s = PL050(obj);
999e12bb 170
3e5dd364 171 s->is_mouse = true;
999e12bb
AL
172}
173
8c43a6f0 174static const TypeInfo pl050_kbd_info = {
39bffca2 175 .name = "pl050_keyboard",
3e5dd364
AF
176 .parent = TYPE_PL050,
177 .instance_init = pl050_keyboard_init,
d6ac172a
PM
178};
179
3e5dd364
AF
180static const TypeInfo pl050_mouse_info = {
181 .name = "pl050_mouse",
182 .parent = TYPE_PL050,
183 .instance_init = pl050_mouse_init,
184};
185
186static void pl050_class_init(ObjectClass *oc, void *data)
999e12bb 187{
3e5dd364 188 DeviceClass *dc = DEVICE_CLASS(oc);
999e12bb 189
988e501a 190 dc->realize = pl050_realize;
39bffca2 191 dc->vmsd = &vmstate_pl050;
999e12bb
AL
192}
193
3e5dd364
AF
194static const TypeInfo pl050_type_info = {
195 .name = TYPE_PL050,
39bffca2 196 .parent = TYPE_SYS_BUS_DEVICE,
e607f25a 197 .instance_size = sizeof(PL050State),
3e5dd364
AF
198 .abstract = true,
199 .class_init = pl050_class_init,
d6ac172a
PM
200};
201
83f7d43a 202static void pl050_register_types(void)
86394e96 203{
3e5dd364 204 type_register_static(&pl050_type_info);
39bffca2
AL
205 type_register_static(&pl050_kbd_info);
206 type_register_static(&pl050_mouse_info);
86394e96
PB
207}
208
83f7d43a 209type_init(pl050_register_types)