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3efda49d 1/*
7fc42b4b 2 * TI TSC2102 (touchscreen/sensors/audio controller) emulator.
a5d7eb65 3 * TI TSC2301 (touchscreen/sensors/keypad).
3efda49d
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4 *
5 * Copyright (c) 2006 Andrzej Zaborowski <balrog@zabor.org>
a5d7eb65 6 * Copyright (C) 2008 Nokia Corporation
3efda49d
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7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
a5d7eb65
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10 * published by the Free Software Foundation; either version 2 or
11 * (at your option) version 3 of the License.
3efda49d
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12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
fad6cb1a 18 * You should have received a copy of the GNU General Public License along
8167ee88 19 * with this program; if not, see <http://www.gnu.org/licenses/>.
3efda49d
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20 */
21
17b7f2db 22#include "qemu/osdep.h"
83c9f4ca 23#include "hw/hw.h"
87ecb68b 24#include "audio/audio.h"
1de7afc9 25#include "qemu/timer.h"
28ecbaee 26#include "ui/console.h"
0d09e41a 27#include "hw/arm/omap.h" /* For I2SCodec and uWireSlave */
bd2be150 28#include "hw/devices.h"
3efda49d
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29
30#define TSC_DATA_REGISTERS_PAGE 0x0
31#define TSC_CONTROL_REGISTERS_PAGE 0x1
32#define TSC_AUDIO_REGISTERS_PAGE 0x2
33
34#define TSC_VERBOSE
35
36#define TSC_CUT_RESOLUTION(value, p) ((value) >> (16 - resolution[p]))
37
bc24a225 38typedef struct {
3efda49d 39 qemu_irq pint;
a5d7eb65
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40 qemu_irq kbint;
41 qemu_irq davint;
3efda49d 42 QEMUTimer *timer;
d8f699cb 43 QEMUSoundCard card;
bc24a225
PB
44 uWireSlave chip;
45 I2SCodec codec;
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46 uint8_t in_fifo[16384];
47 uint8_t out_fifo[16384];
a5d7eb65 48 uint16_t model;
3efda49d 49
fa53b7f0
DDAG
50 int32_t x, y;
51 bool pressure;
52
53 uint8_t page, offset;
54 uint16_t dav;
55
56 bool state;
57 bool irq;
58 bool command;
59 bool busy;
60 bool enabled;
61 bool host_mode;
62 uint8_t function, nextfunction;
63 uint8_t precision, nextprecision;
64 uint8_t filter;
65 uint8_t pin_func;
66 uint8_t ref;
67 uint8_t timing;
68 uint8_t noise;
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69
70 uint16_t audio_ctrl1;
71 uint16_t audio_ctrl2;
72 uint16_t audio_ctrl3;
a5d7eb65 73 uint16_t pll[3];
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74 uint16_t volume;
75 int64_t volume_change;
fa53b7f0 76 bool softstep;
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77 uint16_t dac_power;
78 int64_t powerdown;
79 uint16_t filter_data[0x14];
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80
81 const char *name;
82 SWVoiceIn *adc_voice[1];
83 SWVoiceOut *dac_voice[1];
84 int i2s_rx_rate;
85 int i2s_tx_rate;
a5d7eb65
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86
87 int tr[8];
88
89 struct {
90 uint16_t down;
91 uint16_t mask;
92 int scan;
93 int debounce;
94 int mode;
95 int intr;
96 } kb;
fa53b7f0 97 int64_t now; /* Time at migration */
bc24a225 98} TSC210xState;
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99
100static const int resolution[4] = { 12, 8, 10, 12 };
101
102#define TSC_MODE_NO_SCAN 0x0
103#define TSC_MODE_XY_SCAN 0x1
104#define TSC_MODE_XYZ_SCAN 0x2
105#define TSC_MODE_X 0x3
106#define TSC_MODE_Y 0x4
107#define TSC_MODE_Z 0x5
108#define TSC_MODE_BAT1 0x6
109#define TSC_MODE_BAT2 0x7
110#define TSC_MODE_AUX 0x8
111#define TSC_MODE_AUX_SCAN 0x9
112#define TSC_MODE_TEMP1 0xa
113#define TSC_MODE_PORT_SCAN 0xb
114#define TSC_MODE_TEMP2 0xc
115#define TSC_MODE_XX_DRV 0xd
116#define TSC_MODE_YY_DRV 0xe
117#define TSC_MODE_YX_DRV 0xf
118
119static const uint16_t mode_regs[16] = {
120 0x0000, /* No scan */
121 0x0600, /* X, Y scan */
122 0x0780, /* X, Y, Z scan */
123 0x0400, /* X */
124 0x0200, /* Y */
125 0x0180, /* Z */
126 0x0040, /* BAT1 */
127 0x0030, /* BAT2 */
128 0x0010, /* AUX */
129 0x0010, /* AUX scan */
130 0x0004, /* TEMP1 */
131 0x0070, /* Port scan */
132 0x0002, /* TEMP2 */
133 0x0000, /* X+, X- drivers */
134 0x0000, /* Y+, Y- drivers */
135 0x0000, /* Y+, X- drivers */
136};
137
a5d7eb65
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138#define X_TRANSFORM(s) \
139 ((s->y * s->tr[0] - s->x * s->tr[1]) / s->tr[2] + s->tr[3])
140#define Y_TRANSFORM(s) \
141 ((s->y * s->tr[4] - s->x * s->tr[5]) / s->tr[6] + s->tr[7])
3efda49d 142#define Z1_TRANSFORM(s) \
8ef6367e 143 ((400 - ((s)->x >> 7) + ((s)->pressure << 10)) << 4)
3efda49d 144#define Z2_TRANSFORM(s) \
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145 ((4000 + ((s)->y >> 7) - ((s)->pressure << 10)) << 4)
146
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147#define BAT1_VAL 0x8660
148#define BAT2_VAL 0x0000
149#define AUX1_VAL 0x35c0
150#define AUX2_VAL 0xffff
151#define TEMP1_VAL 0x8c70
152#define TEMP2_VAL 0xa5b0
153
154#define TSC_POWEROFF_DELAY 50
155#define TSC_SOFTSTEP_DELAY 50
156
bc24a225 157static void tsc210x_reset(TSC210xState *s)
3efda49d 158{
fa53b7f0 159 s->state = false;
3efda49d 160 s->pin_func = 2;
fa53b7f0
DDAG
161 s->enabled = false;
162 s->busy = false;
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163 s->nextfunction = 0;
164 s->ref = 0;
165 s->timing = 0;
fa53b7f0 166 s->irq = false;
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167 s->dav = 0;
168
169 s->audio_ctrl1 = 0x0000;
170 s->audio_ctrl2 = 0x4410;
171 s->audio_ctrl3 = 0x0000;
172 s->pll[0] = 0x1004;
173 s->pll[1] = 0x0000;
a5d7eb65 174 s->pll[2] = 0x1fff;
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175 s->volume = 0xffff;
176 s->dac_power = 0x8540;
fa53b7f0 177 s->softstep = true;
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178 s->volume_change = 0;
179 s->powerdown = 0;
180 s->filter_data[0x00] = 0x6be3;
181 s->filter_data[0x01] = 0x9666;
182 s->filter_data[0x02] = 0x675d;
183 s->filter_data[0x03] = 0x6be3;
184 s->filter_data[0x04] = 0x9666;
185 s->filter_data[0x05] = 0x675d;
186 s->filter_data[0x06] = 0x7d83;
187 s->filter_data[0x07] = 0x84ee;
188 s->filter_data[0x08] = 0x7d83;
189 s->filter_data[0x09] = 0x84ee;
190 s->filter_data[0x0a] = 0x6be3;
191 s->filter_data[0x0b] = 0x9666;
192 s->filter_data[0x0c] = 0x675d;
193 s->filter_data[0x0d] = 0x6be3;
194 s->filter_data[0x0e] = 0x9666;
195 s->filter_data[0x0f] = 0x675d;
196 s->filter_data[0x10] = 0x7d83;
197 s->filter_data[0x11] = 0x84ee;
198 s->filter_data[0x12] = 0x7d83;
199 s->filter_data[0x13] = 0x84ee;
200
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201 s->i2s_tx_rate = 0;
202 s->i2s_rx_rate = 0;
203
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204 s->kb.scan = 1;
205 s->kb.debounce = 0;
206 s->kb.mask = 0x0000;
207 s->kb.mode = 3;
208 s->kb.intr = 0;
209
7fc42b4b 210 qemu_set_irq(s->pint, !s->irq);
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211 qemu_set_irq(s->davint, !s->dav);
212 qemu_irq_raise(s->kbint);
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213}
214
bc24a225 215typedef struct {
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216 int rate;
217 int dsor;
218 int fsref;
bc24a225 219} TSC210xRateInfo;
d8f699cb 220
d8f699cb 221/* { rate, dsor, fsref } */
bc24a225 222static const TSC210xRateInfo tsc2102_rates[] = {
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223 /* Fsref / 6.0 */
224 { 7350, 63, 1 },
225 { 8000, 63, 0 },
226 /* Fsref / 6.0 */
227 { 7350, 54, 1 },
228 { 8000, 54, 0 },
229 /* Fsref / 5.0 */
230 { 8820, 45, 1 },
231 { 9600, 45, 0 },
232 /* Fsref / 4.0 */
233 { 11025, 36, 1 },
234 { 12000, 36, 0 },
235 /* Fsref / 3.0 */
236 { 14700, 27, 1 },
237 { 16000, 27, 0 },
238 /* Fsref / 2.0 */
239 { 22050, 18, 1 },
240 { 24000, 18, 0 },
241 /* Fsref / 1.5 */
242 { 29400, 9, 1 },
243 { 32000, 9, 0 },
244 /* Fsref */
245 { 44100, 0, 1 },
246 { 48000, 0, 0 },
247
248 { 0, 0, 0 },
249};
250
bc24a225 251static inline void tsc210x_out_flush(TSC210xState *s, int len)
d8f699cb
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252{
253 uint8_t *data = s->codec.out.fifo + s->codec.out.start;
254 uint8_t *end = data + len;
255
256 while (data < end)
257 data += AUD_write(s->dac_voice[0], data, end - data) ?: (end - data);
258
259 s->codec.out.len -= len;
260 if (s->codec.out.len)
261 memmove(s->codec.out.fifo, end, s->codec.out.len);
262 s->codec.out.start = 0;
263}
264
bc24a225 265static void tsc210x_audio_out_cb(TSC210xState *s, int free_b)
d8f699cb
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266{
267 if (s->codec.out.len >= free_b) {
268 tsc210x_out_flush(s, free_b);
269 return;
270 }
271
272 s->codec.out.size = MIN(free_b, 16384);
273 qemu_irq_raise(s->codec.tx_start);
274}
275
bc24a225 276static void tsc2102_audio_rate_update(TSC210xState *s)
d8f699cb 277{
bc24a225 278 const TSC210xRateInfo *rate;
73560bc8
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279
280 s->codec.tx_rate = 0;
281 s->codec.rx_rate = 0;
282 if (s->dac_power & (1 << 15)) /* PWDNC */
283 return;
284
285 for (rate = tsc2102_rates; rate->rate; rate ++)
286 if (rate->dsor == (s->audio_ctrl1 & 0x3f) && /* DACFS */
287 rate->fsref == ((s->audio_ctrl3 >> 13) & 1))/* REFFS */
288 break;
289 if (!rate->rate) {
290 printf("%s: unknown sampling rate configured\n", __FUNCTION__);
291 return;
292 }
293
294 s->codec.tx_rate = rate->rate;
295}
296
bc24a225 297static void tsc2102_audio_output_update(TSC210xState *s)
73560bc8
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298{
299 int enable;
1ea879e5 300 struct audsettings fmt;
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301
302 if (s->dac_voice[0]) {
303 tsc210x_out_flush(s, s->codec.out.len);
304 s->codec.out.size = 0;
305 AUD_set_active_out(s->dac_voice[0], 0);
306 AUD_close_out(&s->card, s->dac_voice[0]);
b9d38e95 307 s->dac_voice[0] = NULL;
d8f699cb 308 }
73560bc8 309 s->codec.cts = 0;
d8f699cb
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310
311 enable =
312 (~s->dac_power & (1 << 15)) && /* PWDNC */
313 (~s->dac_power & (1 << 10)); /* DAPWDN */
73560bc8 314 if (!enable || !s->codec.tx_rate)
d8f699cb 315 return;
d8f699cb
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316
317 /* Force our own sampling rate even in slave DAC mode */
318 fmt.endianness = 0;
319 fmt.nchannels = 2;
73560bc8 320 fmt.freq = s->codec.tx_rate;
d8f699cb
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321 fmt.fmt = AUD_FMT_S16;
322
323 s->dac_voice[0] = AUD_open_out(&s->card, s->dac_voice[0],
324 "tsc2102.sink", s, (void *) tsc210x_audio_out_cb, &fmt);
73560bc8
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325 if (s->dac_voice[0]) {
326 s->codec.cts = 1;
d8f699cb 327 AUD_set_active_out(s->dac_voice[0], 1);
73560bc8 328 }
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329}
330
bc24a225 331static uint16_t tsc2102_data_register_read(TSC210xState *s, int reg)
3efda49d
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332{
333 switch (reg) {
334 case 0x00: /* X */
335 s->dav &= 0xfbff;
a5d7eb65 336 return TSC_CUT_RESOLUTION(X_TRANSFORM(s), s->precision) +
3efda49d
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337 (s->noise & 3);
338
339 case 0x01: /* Y */
340 s->noise ++;
341 s->dav &= 0xfdff;
a5d7eb65 342 return TSC_CUT_RESOLUTION(Y_TRANSFORM(s), s->precision) ^
3efda49d
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343 (s->noise & 3);
344
345 case 0x02: /* Z1 */
346 s->dav &= 0xfeff;
347 return TSC_CUT_RESOLUTION(Z1_TRANSFORM(s), s->precision) -
348 (s->noise & 3);
349
350 case 0x03: /* Z2 */
351 s->dav &= 0xff7f;
352 return TSC_CUT_RESOLUTION(Z2_TRANSFORM(s), s->precision) |
353 (s->noise & 3);
354
355 case 0x04: /* KPData */
a5d7eb65
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356 if ((s->model & 0xff00) == 0x2300) {
357 if (s->kb.intr && (s->kb.mode & 2)) {
358 s->kb.intr = 0;
359 qemu_irq_raise(s->kbint);
360 }
361 return s->kb.down;
362 }
363
3efda49d
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364 return 0xffff;
365
366 case 0x05: /* BAT1 */
367 s->dav &= 0xffbf;
8ef6367e
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368 return TSC_CUT_RESOLUTION(BAT1_VAL, s->precision) +
369 (s->noise & 6);
3efda49d
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370
371 case 0x06: /* BAT2 */
372 s->dav &= 0xffdf;
373 return TSC_CUT_RESOLUTION(BAT2_VAL, s->precision);
374
375 case 0x07: /* AUX1 */
376 s->dav &= 0xffef;
377 return TSC_CUT_RESOLUTION(AUX1_VAL, s->precision);
378
379 case 0x08: /* AUX2 */
380 s->dav &= 0xfff7;
381 return 0xffff;
382
383 case 0x09: /* TEMP1 */
384 s->dav &= 0xfffb;
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385 return TSC_CUT_RESOLUTION(TEMP1_VAL, s->precision) -
386 (s->noise & 5);
3efda49d
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387
388 case 0x0a: /* TEMP2 */
389 s->dav &= 0xfffd;
8ef6367e
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390 return TSC_CUT_RESOLUTION(TEMP2_VAL, s->precision) ^
391 (s->noise & 3);
3efda49d
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392
393 case 0x0b: /* DAC */
394 s->dav &= 0xfffe;
395 return 0xffff;
396
397 default:
398#ifdef TSC_VERBOSE
399 fprintf(stderr, "tsc2102_data_register_read: "
400 "no such register: 0x%02x\n", reg);
401#endif
402 return 0xffff;
403 }
404}
405
406static uint16_t tsc2102_control_register_read(
bc24a225 407 TSC210xState *s, int reg)
3efda49d
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408{
409 switch (reg) {
410 case 0x00: /* TSC ADC */
411 return (s->pressure << 15) | ((!s->busy) << 14) |
412 (s->nextfunction << 10) | (s->nextprecision << 8) | s->filter;
413
a5d7eb65
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414 case 0x01: /* Status / Keypad Control */
415 if ((s->model & 0xff00) == 0x2100)
416 return (s->pin_func << 14) | ((!s->enabled) << 13) |
417 (s->host_mode << 12) | ((!!s->dav) << 11) | s->dav;
418 else
419 return (s->kb.intr << 15) | ((s->kb.scan || !s->kb.down) << 14) |
420 (s->kb.debounce << 11);
421
422 case 0x02: /* DAC Control */
423 if ((s->model & 0xff00) == 0x2300)
424 return s->dac_power & 0x8000;
425 else
426 goto bad_reg;
3efda49d
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427
428 case 0x03: /* Reference */
429 return s->ref;
430
431 case 0x04: /* Reset */
432 return 0xffff;
433
434 case 0x05: /* Configuration */
435 return s->timing;
436
a5d7eb65
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437 case 0x06: /* Secondary configuration */
438 if ((s->model & 0xff00) == 0x2100)
439 goto bad_reg;
440 return ((!s->dav) << 15) | ((s->kb.mode & 1) << 14) | s->pll[2];
441
442 case 0x10: /* Keypad Mask */
443 if ((s->model & 0xff00) == 0x2100)
444 goto bad_reg;
445 return s->kb.mask;
446
3efda49d 447 default:
a5d7eb65 448 bad_reg:
3efda49d
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449#ifdef TSC_VERBOSE
450 fprintf(stderr, "tsc2102_control_register_read: "
451 "no such register: 0x%02x\n", reg);
452#endif
453 return 0xffff;
454 }
455}
456
bc24a225 457static uint16_t tsc2102_audio_register_read(TSC210xState *s, int reg)
3efda49d
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458{
459 int l_ch, r_ch;
460 uint16_t val;
461
462 switch (reg) {
463 case 0x00: /* Audio Control 1 */
464 return s->audio_ctrl1;
465
466 case 0x01:
467 return 0xff00;
468
469 case 0x02: /* DAC Volume Control */
470 return s->volume;
471
472 case 0x03:
473 return 0x8b00;
474
475 case 0x04: /* Audio Control 2 */
476 l_ch = 1;
477 r_ch = 1;
478 if (s->softstep && !(s->dac_power & (1 << 10))) {
bc72ad67 479 l_ch = (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) >
3efda49d 480 s->volume_change + TSC_SOFTSTEP_DELAY);
bc72ad67 481 r_ch = (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) >
3efda49d
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482 s->volume_change + TSC_SOFTSTEP_DELAY);
483 }
484
485 return s->audio_ctrl2 | (l_ch << 3) | (r_ch << 2);
486
487 case 0x05: /* Stereo DAC Power Control */
488 return 0x2aa0 | s->dac_power |
489 (((s->dac_power & (1 << 10)) &&
bc72ad67 490 (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) >
3efda49d
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491 s->powerdown + TSC_POWEROFF_DELAY)) << 6);
492
493 case 0x06: /* Audio Control 3 */
494 val = s->audio_ctrl3 | 0x0001;
495 s->audio_ctrl3 &= 0xff3f;
496 return val;
497
498 case 0x07: /* LCH_BASS_BOOST_N0 */
499 case 0x08: /* LCH_BASS_BOOST_N1 */
500 case 0x09: /* LCH_BASS_BOOST_N2 */
501 case 0x0a: /* LCH_BASS_BOOST_N3 */
502 case 0x0b: /* LCH_BASS_BOOST_N4 */
503 case 0x0c: /* LCH_BASS_BOOST_N5 */
504 case 0x0d: /* LCH_BASS_BOOST_D1 */
505 case 0x0e: /* LCH_BASS_BOOST_D2 */
506 case 0x0f: /* LCH_BASS_BOOST_D4 */
507 case 0x10: /* LCH_BASS_BOOST_D5 */
508 case 0x11: /* RCH_BASS_BOOST_N0 */
509 case 0x12: /* RCH_BASS_BOOST_N1 */
510 case 0x13: /* RCH_BASS_BOOST_N2 */
511 case 0x14: /* RCH_BASS_BOOST_N3 */
512 case 0x15: /* RCH_BASS_BOOST_N4 */
513 case 0x16: /* RCH_BASS_BOOST_N5 */
514 case 0x17: /* RCH_BASS_BOOST_D1 */
515 case 0x18: /* RCH_BASS_BOOST_D2 */
516 case 0x19: /* RCH_BASS_BOOST_D4 */
517 case 0x1a: /* RCH_BASS_BOOST_D5 */
518 return s->filter_data[reg - 0x07];
519
520 case 0x1b: /* PLL Programmability 1 */
521 return s->pll[0];
522
523 case 0x1c: /* PLL Programmability 2 */
524 return s->pll[1];
525
526 case 0x1d: /* Audio Control 4 */
527 return (!s->softstep) << 14;
528
529 default:
530#ifdef TSC_VERBOSE
531 fprintf(stderr, "tsc2102_audio_register_read: "
532 "no such register: 0x%02x\n", reg);
533#endif
534 return 0xffff;
535 }
536}
537
538static void tsc2102_data_register_write(
bc24a225 539 TSC210xState *s, int reg, uint16_t value)
3efda49d
AZ
540{
541 switch (reg) {
542 case 0x00: /* X */
543 case 0x01: /* Y */
544 case 0x02: /* Z1 */
545 case 0x03: /* Z2 */
546 case 0x05: /* BAT1 */
547 case 0x06: /* BAT2 */
548 case 0x07: /* AUX1 */
549 case 0x08: /* AUX2 */
550 case 0x09: /* TEMP1 */
551 case 0x0a: /* TEMP2 */
552 return;
553
554 default:
555#ifdef TSC_VERBOSE
556 fprintf(stderr, "tsc2102_data_register_write: "
557 "no such register: 0x%02x\n", reg);
558#endif
559 }
560}
561
562static void tsc2102_control_register_write(
bc24a225 563 TSC210xState *s, int reg, uint16_t value)
3efda49d
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564{
565 switch (reg) {
566 case 0x00: /* TSC ADC */
567 s->host_mode = value >> 15;
568 s->enabled = !(value & 0x4000);
569 if (s->busy && !s->enabled)
bc72ad67 570 timer_del(s->timer);
fa53b7f0 571 s->busy = s->busy && s->enabled;
3efda49d
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572 s->nextfunction = (value >> 10) & 0xf;
573 s->nextprecision = (value >> 8) & 3;
574 s->filter = value & 0xff;
575 return;
576
a5d7eb65
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577 case 0x01: /* Status / Keypad Control */
578 if ((s->model & 0xff00) == 0x2100)
579 s->pin_func = value >> 14;
580 else {
581 s->kb.scan = (value >> 14) & 1;
582 s->kb.debounce = (value >> 11) & 7;
583 if (s->kb.intr && s->kb.scan) {
584 s->kb.intr = 0;
585 qemu_irq_raise(s->kbint);
586 }
587 }
3efda49d
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588 return;
589
a5d7eb65
AZ
590 case 0x02: /* DAC Control */
591 if ((s->model & 0xff00) == 0x2300) {
592 s->dac_power &= 0x7fff;
593 s->dac_power |= 0x8000 & value;
594 } else
595 goto bad_reg;
596 break;
597
3efda49d
AZ
598 case 0x03: /* Reference */
599 s->ref = value & 0x1f;
600 return;
601
602 case 0x04: /* Reset */
603 if (value == 0xbb00) {
604 if (s->busy)
bc72ad67 605 timer_del(s->timer);
3efda49d
AZ
606 tsc210x_reset(s);
607#ifdef TSC_VERBOSE
608 } else {
609 fprintf(stderr, "tsc2102_control_register_write: "
610 "wrong value written into RESET\n");
611#endif
612 }
613 return;
614
615 case 0x05: /* Configuration */
616 s->timing = value & 0x3f;
617#ifdef TSC_VERBOSE
618 if (value & ~0x3f)
619 fprintf(stderr, "tsc2102_control_register_write: "
620 "wrong value written into CONFIG\n");
621#endif
622 return;
623
a5d7eb65
AZ
624 case 0x06: /* Secondary configuration */
625 if ((s->model & 0xff00) == 0x2100)
626 goto bad_reg;
627 s->kb.mode = value >> 14;
628 s->pll[2] = value & 0x3ffff;
629 return;
630
631 case 0x10: /* Keypad Mask */
632 if ((s->model & 0xff00) == 0x2100)
633 goto bad_reg;
634 s->kb.mask = value;
635 return;
636
3efda49d 637 default:
a5d7eb65 638 bad_reg:
3efda49d
AZ
639#ifdef TSC_VERBOSE
640 fprintf(stderr, "tsc2102_control_register_write: "
641 "no such register: 0x%02x\n", reg);
642#endif
643 }
644}
645
646static void tsc2102_audio_register_write(
bc24a225 647 TSC210xState *s, int reg, uint16_t value)
3efda49d
AZ
648{
649 switch (reg) {
650 case 0x00: /* Audio Control 1 */
651 s->audio_ctrl1 = value & 0x0f3f;
652#ifdef TSC_VERBOSE
653 if ((value & ~0x0f3f) || ((value & 7) != ((value >> 3) & 7)))
654 fprintf(stderr, "tsc2102_audio_register_write: "
655 "wrong value written into Audio 1\n");
656#endif
73560bc8 657 tsc2102_audio_rate_update(s);
22d83b14 658 tsc2102_audio_output_update(s);
3efda49d
AZ
659 return;
660
661 case 0x01:
662#ifdef TSC_VERBOSE
663 if (value != 0xff00)
664 fprintf(stderr, "tsc2102_audio_register_write: "
665 "wrong value written into reg 0x01\n");
666#endif
667 return;
668
669 case 0x02: /* DAC Volume Control */
670 s->volume = value;
bc72ad67 671 s->volume_change = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
3efda49d
AZ
672 return;
673
674 case 0x03:
675#ifdef TSC_VERBOSE
676 if (value != 0x8b00)
677 fprintf(stderr, "tsc2102_audio_register_write: "
678 "wrong value written into reg 0x03\n");
679#endif
680 return;
681
682 case 0x04: /* Audio Control 2 */
683 s->audio_ctrl2 = value & 0xf7f2;
684#ifdef TSC_VERBOSE
685 if (value & ~0xf7fd)
686 fprintf(stderr, "tsc2102_audio_register_write: "
687 "wrong value written into Audio 2\n");
688#endif
689 return;
690
691 case 0x05: /* Stereo DAC Power Control */
692 if ((value & ~s->dac_power) & (1 << 10))
bc72ad67 693 s->powerdown = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
3efda49d
AZ
694
695 s->dac_power = value & 0x9543;
696#ifdef TSC_VERBOSE
697 if ((value & ~0x9543) != 0x2aa0)
698 fprintf(stderr, "tsc2102_audio_register_write: "
699 "wrong value written into Power\n");
700#endif
73560bc8 701 tsc2102_audio_rate_update(s);
22d83b14 702 tsc2102_audio_output_update(s);
3efda49d
AZ
703 return;
704
705 case 0x06: /* Audio Control 3 */
706 s->audio_ctrl3 &= 0x00c0;
707 s->audio_ctrl3 |= value & 0xf800;
708#ifdef TSC_VERBOSE
709 if (value & ~0xf8c7)
710 fprintf(stderr, "tsc2102_audio_register_write: "
711 "wrong value written into Audio 3\n");
712#endif
22d83b14 713 tsc2102_audio_output_update(s);
3efda49d
AZ
714 return;
715
716 case 0x07: /* LCH_BASS_BOOST_N0 */
717 case 0x08: /* LCH_BASS_BOOST_N1 */
718 case 0x09: /* LCH_BASS_BOOST_N2 */
719 case 0x0a: /* LCH_BASS_BOOST_N3 */
720 case 0x0b: /* LCH_BASS_BOOST_N4 */
721 case 0x0c: /* LCH_BASS_BOOST_N5 */
722 case 0x0d: /* LCH_BASS_BOOST_D1 */
723 case 0x0e: /* LCH_BASS_BOOST_D2 */
724 case 0x0f: /* LCH_BASS_BOOST_D4 */
725 case 0x10: /* LCH_BASS_BOOST_D5 */
726 case 0x11: /* RCH_BASS_BOOST_N0 */
727 case 0x12: /* RCH_BASS_BOOST_N1 */
728 case 0x13: /* RCH_BASS_BOOST_N2 */
729 case 0x14: /* RCH_BASS_BOOST_N3 */
730 case 0x15: /* RCH_BASS_BOOST_N4 */
731 case 0x16: /* RCH_BASS_BOOST_N5 */
732 case 0x17: /* RCH_BASS_BOOST_D1 */
733 case 0x18: /* RCH_BASS_BOOST_D2 */
734 case 0x19: /* RCH_BASS_BOOST_D4 */
735 case 0x1a: /* RCH_BASS_BOOST_D5 */
736 s->filter_data[reg - 0x07] = value;
737 return;
738
739 case 0x1b: /* PLL Programmability 1 */
740 s->pll[0] = value & 0xfffc;
741#ifdef TSC_VERBOSE
742 if (value & ~0xfffc)
743 fprintf(stderr, "tsc2102_audio_register_write: "
744 "wrong value written into PLL 1\n");
745#endif
746 return;
747
748 case 0x1c: /* PLL Programmability 2 */
749 s->pll[1] = value & 0xfffc;
750#ifdef TSC_VERBOSE
751 if (value & ~0xfffc)
752 fprintf(stderr, "tsc2102_audio_register_write: "
753 "wrong value written into PLL 2\n");
754#endif
755 return;
756
757 case 0x1d: /* Audio Control 4 */
758 s->softstep = !(value & 0x4000);
759#ifdef TSC_VERBOSE
760 if (value & ~0x4000)
761 fprintf(stderr, "tsc2102_audio_register_write: "
762 "wrong value written into Audio 4\n");
763#endif
764 return;
765
766 default:
767#ifdef TSC_VERBOSE
768 fprintf(stderr, "tsc2102_audio_register_write: "
769 "no such register: 0x%02x\n", reg);
770#endif
771 }
772}
773
774/* This handles most of the chip logic. */
bc24a225 775static void tsc210x_pin_update(TSC210xState *s)
3efda49d
AZ
776{
777 int64_t expires;
fa53b7f0 778 bool pin_state;
3efda49d
AZ
779
780 switch (s->pin_func) {
781 case 0:
782 pin_state = s->pressure;
783 break;
784 case 1:
785 pin_state = !!s->dav;
786 break;
787 case 2:
788 default:
789 pin_state = s->pressure && !s->dav;
790 }
791
792 if (!s->enabled)
fa53b7f0 793 pin_state = false;
3efda49d
AZ
794
795 if (pin_state != s->irq) {
796 s->irq = pin_state;
7fc42b4b 797 qemu_set_irq(s->pint, !s->irq);
3efda49d
AZ
798 }
799
800 switch (s->nextfunction) {
801 case TSC_MODE_XY_SCAN:
802 case TSC_MODE_XYZ_SCAN:
803 if (!s->pressure)
804 return;
805 break;
806
807 case TSC_MODE_X:
808 case TSC_MODE_Y:
809 case TSC_MODE_Z:
810 if (!s->pressure)
811 return;
812 /* Fall through */
813 case TSC_MODE_BAT1:
814 case TSC_MODE_BAT2:
815 case TSC_MODE_AUX:
816 case TSC_MODE_TEMP1:
817 case TSC_MODE_TEMP2:
818 if (s->dav)
fa53b7f0 819 s->enabled = false;
3efda49d
AZ
820 break;
821
822 case TSC_MODE_AUX_SCAN:
823 case TSC_MODE_PORT_SCAN:
824 break;
825
826 case TSC_MODE_NO_SCAN:
827 case TSC_MODE_XX_DRV:
828 case TSC_MODE_YY_DRV:
829 case TSC_MODE_YX_DRV:
830 default:
831 return;
832 }
833
a5d7eb65 834 if (!s->enabled || s->busy || s->dav)
3efda49d
AZ
835 return;
836
fa53b7f0 837 s->busy = true;
3efda49d
AZ
838 s->precision = s->nextprecision;
839 s->function = s->nextfunction;
73bcb24d
RS
840 expires = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
841 (NANOSECONDS_PER_SECOND >> 10);
bc72ad67 842 timer_mod(s->timer, expires);
3efda49d
AZ
843}
844
bc24a225 845static uint16_t tsc210x_read(TSC210xState *s)
3efda49d
AZ
846{
847 uint16_t ret = 0x0000;
848
849 if (!s->command)
850 fprintf(stderr, "tsc210x_read: SPI underrun!\n");
851
852 switch (s->page) {
853 case TSC_DATA_REGISTERS_PAGE:
854 ret = tsc2102_data_register_read(s, s->offset);
a5d7eb65
AZ
855 if (!s->dav)
856 qemu_irq_raise(s->davint);
3efda49d
AZ
857 break;
858 case TSC_CONTROL_REGISTERS_PAGE:
859 ret = tsc2102_control_register_read(s, s->offset);
860 break;
861 case TSC_AUDIO_REGISTERS_PAGE:
862 ret = tsc2102_audio_register_read(s, s->offset);
863 break;
864 default:
2ac71179 865 hw_error("tsc210x_read: wrong memory page\n");
3efda49d
AZ
866 }
867
868 tsc210x_pin_update(s);
869
870 /* Allow sequential reads. */
871 s->offset ++;
fa53b7f0 872 s->state = false;
3efda49d
AZ
873 return ret;
874}
875
bc24a225 876static void tsc210x_write(TSC210xState *s, uint16_t value)
3efda49d
AZ
877{
878 /*
879 * This is a two-state state machine for reading
880 * command and data every second time.
881 */
882 if (!s->state) {
fa53b7f0 883 s->command = (value >> 15) != 0;
3efda49d
AZ
884 s->page = (value >> 11) & 0x0f;
885 s->offset = (value >> 5) & 0x3f;
fa53b7f0 886 s->state = true;
3efda49d
AZ
887 } else {
888 if (s->command)
889 fprintf(stderr, "tsc210x_write: SPI overrun!\n");
890 else
891 switch (s->page) {
892 case TSC_DATA_REGISTERS_PAGE:
893 tsc2102_data_register_write(s, s->offset, value);
894 break;
895 case TSC_CONTROL_REGISTERS_PAGE:
896 tsc2102_control_register_write(s, s->offset, value);
897 break;
898 case TSC_AUDIO_REGISTERS_PAGE:
899 tsc2102_audio_register_write(s, s->offset, value);
900 break;
901 default:
2ac71179 902 hw_error("tsc210x_write: wrong memory page\n");
3efda49d
AZ
903 }
904
905 tsc210x_pin_update(s);
fa53b7f0 906 s->state = false;
3efda49d
AZ
907 }
908}
909
e927bb00 910uint32_t tsc210x_txrx(void *opaque, uint32_t value, int len)
a5d7eb65 911{
bc24a225 912 TSC210xState *s = opaque;
a5d7eb65
AZ
913 uint32_t ret = 0;
914
e927bb00 915 if (len != 16)
2ac71179 916 hw_error("%s: FIXME: bad SPI word width %i\n", __FUNCTION__, len);
e927bb00 917
a5d7eb65
AZ
918 /* TODO: sequential reads etc - how do we make sure the host doesn't
919 * unintentionally read out a conversion result from a register while
920 * transmitting the command word of the next command? */
921 if (!value || (s->state && s->command))
922 ret = tsc210x_read(s);
923 if (value || (s->state && !s->command))
924 tsc210x_write(s, value);
925
926 return ret;
927}
928
3efda49d
AZ
929static void tsc210x_timer_tick(void *opaque)
930{
bc24a225 931 TSC210xState *s = opaque;
3efda49d
AZ
932
933 /* Timer ticked -- a set of conversions has been finished. */
934
935 if (!s->busy)
936 return;
937
fa53b7f0 938 s->busy = false;
3efda49d
AZ
939 s->dav |= mode_regs[s->function];
940 tsc210x_pin_update(s);
a5d7eb65 941 qemu_irq_lower(s->davint);
3efda49d
AZ
942}
943
944static void tsc210x_touchscreen_event(void *opaque,
945 int x, int y, int z, int buttons_state)
946{
bc24a225 947 TSC210xState *s = opaque;
3efda49d
AZ
948 int p = s->pressure;
949
950 if (buttons_state) {
951 s->x = x;
952 s->y = y;
953 }
954 s->pressure = !!buttons_state;
955
956 /*
957 * Note: We would get better responsiveness in the guest by
958 * signaling TS events immediately, but for now we simulate
959 * the first conversion delay for sake of correctness.
960 */
961 if (p != s->pressure)
962 tsc210x_pin_update(s);
963}
964
bc24a225 965static void tsc210x_i2s_swallow(TSC210xState *s)
d8f699cb
AZ
966{
967 if (s->dac_voice[0])
968 tsc210x_out_flush(s, s->codec.out.len);
969 else
970 s->codec.out.len = 0;
971}
972
bc24a225 973static void tsc210x_i2s_set_rate(TSC210xState *s, int in, int out)
d8f699cb
AZ
974{
975 s->i2s_tx_rate = out;
976 s->i2s_rx_rate = in;
977}
978
fa53b7f0 979static void tsc210x_pre_save(void *opaque)
3efda49d 980{
bc24a225 981 TSC210xState *s = (TSC210xState *) opaque;
fa53b7f0 982 s->now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
3efda49d
AZ
983}
984
fa53b7f0 985static int tsc210x_post_load(void *opaque, int version_id)
3efda49d 986{
bc24a225 987 TSC210xState *s = (TSC210xState *) opaque;
bc72ad67 988 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
3efda49d 989
fa53b7f0 990 if (s->function >= ARRAY_SIZE(mode_regs)) {
5193be3b
MT
991 return -EINVAL;
992 }
fa53b7f0 993 if (s->nextfunction >= ARRAY_SIZE(mode_regs)) {
5193be3b
MT
994 return -EINVAL;
995 }
fa53b7f0 996 if (s->precision >= ARRAY_SIZE(resolution)) {
5193be3b
MT
997 return -EINVAL;
998 }
fa53b7f0 999 if (s->nextprecision >= ARRAY_SIZE(resolution)) {
5193be3b
MT
1000 return -EINVAL;
1001 }
fa53b7f0
DDAG
1002
1003 s->volume_change -= s->now;
1004 s->volume_change += now;
1005 s->powerdown -= s->now;
1006 s->powerdown += now;
3efda49d 1007
e93379b0 1008 s->busy = timer_pending(s->timer);
7fc42b4b 1009 qemu_set_irq(s->pint, !s->irq);
a5d7eb65 1010 qemu_set_irq(s->davint, !s->dav);
3efda49d
AZ
1011
1012 return 0;
1013}
1014
fa53b7f0
DDAG
1015static VMStateField vmstatefields_tsc210x[] = {
1016 VMSTATE_BOOL(enabled, TSC210xState),
1017 VMSTATE_BOOL(host_mode, TSC210xState),
1018 VMSTATE_BOOL(irq, TSC210xState),
1019 VMSTATE_BOOL(command, TSC210xState),
1020 VMSTATE_BOOL(pressure, TSC210xState),
1021 VMSTATE_BOOL(softstep, TSC210xState),
1022 VMSTATE_BOOL(state, TSC210xState),
1023 VMSTATE_UINT16(dav, TSC210xState),
1024 VMSTATE_INT32(x, TSC210xState),
1025 VMSTATE_INT32(y, TSC210xState),
1026 VMSTATE_UINT8(offset, TSC210xState),
1027 VMSTATE_UINT8(page, TSC210xState),
1028 VMSTATE_UINT8(filter, TSC210xState),
1029 VMSTATE_UINT8(pin_func, TSC210xState),
1030 VMSTATE_UINT8(ref, TSC210xState),
1031 VMSTATE_UINT8(timing, TSC210xState),
1032 VMSTATE_UINT8(noise, TSC210xState),
1033 VMSTATE_UINT8(function, TSC210xState),
1034 VMSTATE_UINT8(nextfunction, TSC210xState),
1035 VMSTATE_UINT8(precision, TSC210xState),
1036 VMSTATE_UINT8(nextprecision, TSC210xState),
1037 VMSTATE_UINT16(audio_ctrl1, TSC210xState),
1038 VMSTATE_UINT16(audio_ctrl2, TSC210xState),
1039 VMSTATE_UINT16(audio_ctrl3, TSC210xState),
1040 VMSTATE_UINT16_ARRAY(pll, TSC210xState, 3),
1041 VMSTATE_UINT16(volume, TSC210xState),
1042 VMSTATE_UINT16(dac_power, TSC210xState),
1043 VMSTATE_INT64(volume_change, TSC210xState),
1044 VMSTATE_INT64(powerdown, TSC210xState),
1045 VMSTATE_INT64(now, TSC210xState),
1046 VMSTATE_UINT16_ARRAY(filter_data, TSC210xState, 0x14),
1047 VMSTATE_TIMER_PTR(timer, TSC210xState),
1048 VMSTATE_END_OF_LIST()
1049};
1050
1051static const VMStateDescription vmstate_tsc2102 = {
1052 .name = "tsc2102",
1053 .version_id = 1,
1054 .minimum_version_id = 1,
1055 .pre_save = tsc210x_pre_save,
1056 .post_load = tsc210x_post_load,
1057 .fields = vmstatefields_tsc210x,
1058};
1059
1060static const VMStateDescription vmstate_tsc2301 = {
1061 .name = "tsc2301",
1062 .version_id = 1,
1063 .minimum_version_id = 1,
1064 .pre_save = tsc210x_pre_save,
1065 .post_load = tsc210x_post_load,
1066 .fields = vmstatefields_tsc210x,
1067};
1068
22d83b14 1069uWireSlave *tsc2102_init(qemu_irq pint)
3efda49d 1070{
bc24a225 1071 TSC210xState *s;
3efda49d 1072
a6c6d827 1073 s = g_new0(TSC210xState, 1);
3efda49d
AZ
1074 s->x = 160;
1075 s->y = 160;
1076 s->pressure = 0;
1077 s->precision = s->nextprecision = 0;
bc72ad67 1078 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, tsc210x_timer_tick, s);
3efda49d 1079 s->pint = pint;
a5d7eb65 1080 s->model = 0x2102;
d8f699cb 1081 s->name = "tsc2102";
3efda49d 1082
a5d7eb65
AZ
1083 s->tr[0] = 0;
1084 s->tr[1] = 1;
e927bb00
AZ
1085 s->tr[2] = 1;
1086 s->tr[3] = 0;
a5d7eb65
AZ
1087 s->tr[4] = 1;
1088 s->tr[5] = 0;
e927bb00
AZ
1089 s->tr[6] = 1;
1090 s->tr[7] = 0;
a5d7eb65 1091
3efda49d
AZ
1092 s->chip.opaque = s;
1093 s->chip.send = (void *) tsc210x_write;
1094 s->chip.receive = (void *) tsc210x_read;
1095
d8f699cb
AZ
1096 s->codec.opaque = s;
1097 s->codec.tx_swallow = (void *) tsc210x_i2s_swallow;
1098 s->codec.set_rate = (void *) tsc210x_i2s_set_rate;
1099 s->codec.in.fifo = s->in_fifo;
1100 s->codec.out.fifo = s->out_fifo;
1101
3efda49d
AZ
1102 tsc210x_reset(s);
1103
1104 qemu_add_mouse_event_handler(tsc210x_touchscreen_event, s, 1,
1105 "QEMU TSC2102-driven Touchscreen");
1106
1a7dafce 1107 AUD_register_card(s->name, &s->card);
d8f699cb 1108
a08d4367 1109 qemu_register_reset((void *) tsc210x_reset, s);
fa53b7f0 1110 vmstate_register(NULL, 0, &vmstate_tsc2102, s);
3efda49d
AZ
1111
1112 return &s->chip;
1113}
d8f699cb 1114
22d83b14 1115uWireSlave *tsc2301_init(qemu_irq penirq, qemu_irq kbirq, qemu_irq dav)
a5d7eb65 1116{
bc24a225 1117 TSC210xState *s;
a5d7eb65 1118
a6c6d827 1119 s = g_new0(TSC210xState, 1);
a5d7eb65
AZ
1120 s->x = 400;
1121 s->y = 240;
1122 s->pressure = 0;
1123 s->precision = s->nextprecision = 0;
bc72ad67 1124 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, tsc210x_timer_tick, s);
a5d7eb65
AZ
1125 s->pint = penirq;
1126 s->kbint = kbirq;
1127 s->davint = dav;
1128 s->model = 0x2301;
1129 s->name = "tsc2301";
a5d7eb65
AZ
1130
1131 s->tr[0] = 0;
1132 s->tr[1] = 1;
e927bb00
AZ
1133 s->tr[2] = 1;
1134 s->tr[3] = 0;
a5d7eb65
AZ
1135 s->tr[4] = 1;
1136 s->tr[5] = 0;
e927bb00
AZ
1137 s->tr[6] = 1;
1138 s->tr[7] = 0;
a5d7eb65
AZ
1139
1140 s->chip.opaque = s;
1141 s->chip.send = (void *) tsc210x_write;
1142 s->chip.receive = (void *) tsc210x_read;
1143
1144 s->codec.opaque = s;
1145 s->codec.tx_swallow = (void *) tsc210x_i2s_swallow;
1146 s->codec.set_rate = (void *) tsc210x_i2s_set_rate;
1147 s->codec.in.fifo = s->in_fifo;
1148 s->codec.out.fifo = s->out_fifo;
1149
1150 tsc210x_reset(s);
1151
1152 qemu_add_mouse_event_handler(tsc210x_touchscreen_event, s, 1,
1153 "QEMU TSC2301-driven Touchscreen");
1154
1a7dafce 1155 AUD_register_card(s->name, &s->card);
a5d7eb65 1156
a08d4367 1157 qemu_register_reset((void *) tsc210x_reset, s);
fa53b7f0 1158 vmstate_register(NULL, 0, &vmstate_tsc2301, s);
a5d7eb65
AZ
1159
1160 return &s->chip;
1161}
1162
bc24a225 1163I2SCodec *tsc210x_codec(uWireSlave *chip)
d8f699cb 1164{
bc24a225 1165 TSC210xState *s = (TSC210xState *) chip->opaque;
d8f699cb
AZ
1166
1167 return &s->codec;
1168}
a5d7eb65
AZ
1169
1170/*
1171 * Use tslib generated calibration data to generate ADC input values
1172 * from the touchscreen. Assuming 12-bit precision was used during
1173 * tslib calibration.
1174 */
bc24a225
PB
1175void tsc210x_set_transform(uWireSlave *chip,
1176 MouseTransformInfo *info)
a5d7eb65 1177{
bc24a225 1178 TSC210xState *s = (TSC210xState *) chip->opaque;
a5d7eb65
AZ
1179#if 0
1180 int64_t ltr[8];
1181
1182 ltr[0] = (int64_t) info->a[1] * info->y;
1183 ltr[1] = (int64_t) info->a[4] * info->x;
1184 ltr[2] = (int64_t) info->a[1] * info->a[3] -
1185 (int64_t) info->a[4] * info->a[0];
1186 ltr[3] = (int64_t) info->a[2] * info->a[4] -
1187 (int64_t) info->a[5] * info->a[1];
1188 ltr[4] = (int64_t) info->a[0] * info->y;
1189 ltr[5] = (int64_t) info->a[3] * info->x;
1190 ltr[6] = (int64_t) info->a[4] * info->a[0] -
1191 (int64_t) info->a[1] * info->a[3];
1192 ltr[7] = (int64_t) info->a[2] * info->a[3] -
1193 (int64_t) info->a[5] * info->a[0];
1194
1195 /* Avoid integer overflow */
1196 s->tr[0] = ltr[0] >> 11;
1197 s->tr[1] = ltr[1] >> 11;
1198 s->tr[2] = muldiv64(ltr[2], 1, info->a[6]);
1199 s->tr[3] = muldiv64(ltr[3], 1 << 4, ltr[2]);
1200 s->tr[4] = ltr[4] >> 11;
1201 s->tr[5] = ltr[5] >> 11;
1202 s->tr[6] = muldiv64(ltr[6], 1, info->a[6]);
1203 s->tr[7] = muldiv64(ltr[7], 1 << 4, ltr[6]);
1204#else
1205
1206 /* This version assumes touchscreen X & Y axis are parallel or
1207 * perpendicular to LCD's X & Y axis in some way. */
1208 if (abs(info->a[0]) > abs(info->a[1])) {
1209 s->tr[0] = 0;
1210 s->tr[1] = -info->a[6] * info->x;
1211 s->tr[2] = info->a[0];
1212 s->tr[3] = -info->a[2] / info->a[0];
1213 s->tr[4] = info->a[6] * info->y;
1214 s->tr[5] = 0;
1215 s->tr[6] = info->a[4];
1216 s->tr[7] = -info->a[5] / info->a[4];
1217 } else {
1218 s->tr[0] = info->a[6] * info->y;
1219 s->tr[1] = 0;
1220 s->tr[2] = info->a[1];
1221 s->tr[3] = -info->a[2] / info->a[1];
1222 s->tr[4] = 0;
1223 s->tr[5] = -info->a[6] * info->x;
1224 s->tr[6] = info->a[3];
1225 s->tr[7] = -info->a[5] / info->a[3];
1226 }
1227
1228 s->tr[0] >>= 11;
1229 s->tr[1] >>= 11;
1230 s->tr[3] <<= 4;
1231 s->tr[4] >>= 11;
1232 s->tr[5] >>= 11;
1233 s->tr[7] <<= 4;
1234#endif
1235}
1236
bc24a225 1237void tsc210x_key_event(uWireSlave *chip, int key, int down)
a5d7eb65 1238{
bc24a225 1239 TSC210xState *s = (TSC210xState *) chip->opaque;
a5d7eb65
AZ
1240
1241 if (down)
1242 s->kb.down |= 1 << key;
1243 else
1244 s->kb.down &= ~(1 << key);
1245
1246 if (down && (s->kb.down & ~s->kb.mask) && !s->kb.intr) {
1247 s->kb.intr = 1;
1248 qemu_irq_lower(s->kbint);
1249 } else if (s->kb.intr && !(s->kb.down & ~s->kb.mask) &&
1250 !(s->kb.mode & 1)) {
1251 s->kb.intr = 0;
1252 qemu_irq_raise(s->kbint);
1253 }
1254}