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dae01685 JK |
1 | /* |
2 | * APIC support - common bits of emulated and KVM kernel model | |
3 | * | |
4 | * Copyright (c) 2004-2005 Fabrice Bellard | |
5 | * Copyright (c) 2011 Jan Kiszka, Siemens AG | |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
18 | * License along with this library; if not, see <http://www.gnu.org/licenses/> | |
19 | */ | |
b6a0aa05 | 20 | #include "qemu/osdep.h" |
2f114315 | 21 | #include "qemu/error-report.h" |
da34e65c | 22 | #include "qapi/error.h" |
33c11879 PB |
23 | #include "qemu-common.h" |
24 | #include "cpu.h" | |
0d09e41a PB |
25 | #include "hw/i386/apic.h" |
26 | #include "hw/i386/apic_internal.h" | |
dae01685 | 27 | #include "trace.h" |
9c17d615 | 28 | #include "sysemu/kvm.h" |
53a89e26 IM |
29 | #include "hw/qdev.h" |
30 | #include "hw/sysbus.h" | |
dae01685 JK |
31 | |
32 | static int apic_irq_delivered; | |
e5ad936b | 33 | bool apic_report_tpr_access; |
dae01685 | 34 | |
d3b0c9e9 | 35 | void cpu_set_apic_base(DeviceState *dev, uint64_t val) |
dae01685 | 36 | { |
dae01685 JK |
37 | trace_cpu_set_apic_base(val); |
38 | ||
d3b0c9e9 XZ |
39 | if (dev) { |
40 | APICCommonState *s = APIC_COMMON(dev); | |
999e12bb | 41 | APICCommonClass *info = APIC_COMMON_GET_CLASS(s); |
dae01685 JK |
42 | info->set_base(s, val); |
43 | } | |
44 | } | |
45 | ||
d3b0c9e9 | 46 | uint64_t cpu_get_apic_base(DeviceState *dev) |
dae01685 | 47 | { |
d3b0c9e9 XZ |
48 | if (dev) { |
49 | APICCommonState *s = APIC_COMMON(dev); | |
999e12bb AL |
50 | trace_cpu_get_apic_base((uint64_t)s->apicbase); |
51 | return s->apicbase; | |
52 | } else { | |
dd673288 IM |
53 | trace_cpu_get_apic_base(MSR_IA32_APICBASE_BSP); |
54 | return MSR_IA32_APICBASE_BSP; | |
999e12bb | 55 | } |
dae01685 JK |
56 | } |
57 | ||
d3b0c9e9 | 58 | void cpu_set_apic_tpr(DeviceState *dev, uint8_t val) |
dae01685 | 59 | { |
999e12bb AL |
60 | APICCommonState *s; |
61 | APICCommonClass *info; | |
dae01685 | 62 | |
d3b0c9e9 | 63 | if (!dev) { |
999e12bb | 64 | return; |
dae01685 | 65 | } |
999e12bb | 66 | |
d3b0c9e9 | 67 | s = APIC_COMMON(dev); |
999e12bb AL |
68 | info = APIC_COMMON_GET_CLASS(s); |
69 | ||
70 | info->set_tpr(s, val); | |
dae01685 JK |
71 | } |
72 | ||
d3b0c9e9 | 73 | uint8_t cpu_get_apic_tpr(DeviceState *dev) |
e5ad936b JK |
74 | { |
75 | APICCommonState *s; | |
76 | APICCommonClass *info; | |
77 | ||
d3b0c9e9 | 78 | if (!dev) { |
e5ad936b JK |
79 | return 0; |
80 | } | |
81 | ||
d3b0c9e9 | 82 | s = APIC_COMMON(dev); |
e5ad936b JK |
83 | info = APIC_COMMON_GET_CLASS(s); |
84 | ||
85 | return info->get_tpr(s); | |
86 | } | |
87 | ||
d3b0c9e9 | 88 | void apic_enable_tpr_access_reporting(DeviceState *dev, bool enable) |
e5ad936b | 89 | { |
d3b0c9e9 | 90 | APICCommonState *s = APIC_COMMON(dev); |
e5ad936b JK |
91 | APICCommonClass *info = APIC_COMMON_GET_CLASS(s); |
92 | ||
93 | apic_report_tpr_access = enable; | |
94 | if (info->enable_tpr_reporting) { | |
95 | info->enable_tpr_reporting(s, enable); | |
96 | } | |
97 | } | |
98 | ||
d3b0c9e9 | 99 | void apic_enable_vapic(DeviceState *dev, hwaddr paddr) |
dae01685 | 100 | { |
d3b0c9e9 | 101 | APICCommonState *s = APIC_COMMON(dev); |
e5ad936b | 102 | APICCommonClass *info = APIC_COMMON_GET_CLASS(s); |
dae01685 | 103 | |
e5ad936b JK |
104 | s->vapic_paddr = paddr; |
105 | info->vapic_base_update(s); | |
dae01685 JK |
106 | } |
107 | ||
d3b0c9e9 | 108 | void apic_handle_tpr_access_report(DeviceState *dev, target_ulong ip, |
d362e757 JK |
109 | TPRAccess access) |
110 | { | |
d3b0c9e9 | 111 | APICCommonState *s = APIC_COMMON(dev); |
e5ad936b | 112 | |
d77953b9 | 113 | vapic_report_tpr_access(s->vapic, CPU(s->cpu), ip, access); |
d362e757 JK |
114 | } |
115 | ||
dae01685 JK |
116 | void apic_report_irq_delivered(int delivered) |
117 | { | |
118 | apic_irq_delivered += delivered; | |
119 | ||
120 | trace_apic_report_irq_delivered(apic_irq_delivered); | |
121 | } | |
122 | ||
123 | void apic_reset_irq_delivered(void) | |
124 | { | |
9bcec938 FCE |
125 | /* Copy this into a local variable to encourage gcc to emit a plain |
126 | * register for a sys/sdt.h marker. For details on this workaround, see: | |
127 | * https://sourceware.org/bugzilla/show_bug.cgi?id=13296 | |
128 | */ | |
129 | volatile int a_i_d = apic_irq_delivered; | |
130 | trace_apic_reset_irq_delivered(a_i_d); | |
dae01685 JK |
131 | |
132 | apic_irq_delivered = 0; | |
133 | } | |
134 | ||
135 | int apic_get_irq_delivered(void) | |
136 | { | |
137 | trace_apic_get_irq_delivered(apic_irq_delivered); | |
138 | ||
139 | return apic_irq_delivered; | |
140 | } | |
141 | ||
d3b0c9e9 | 142 | void apic_deliver_nmi(DeviceState *dev) |
dae01685 | 143 | { |
d3b0c9e9 | 144 | APICCommonState *s = APIC_COMMON(dev); |
999e12bb | 145 | APICCommonClass *info = APIC_COMMON_GET_CLASS(s); |
dae01685 | 146 | |
dae01685 JK |
147 | info->external_nmi(s); |
148 | } | |
149 | ||
7a380ca3 JK |
150 | bool apic_next_timer(APICCommonState *s, int64_t current_time) |
151 | { | |
152 | int64_t d; | |
153 | ||
154 | /* We need to store the timer state separately to support APIC | |
155 | * implementations that maintain a non-QEMU timer, e.g. inside the | |
156 | * host kernel. This open-coded state allows us to migrate between | |
157 | * both models. */ | |
158 | s->timer_expiry = -1; | |
159 | ||
160 | if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED) { | |
161 | return false; | |
162 | } | |
163 | ||
164 | d = (current_time - s->initial_count_load_time) >> s->count_shift; | |
165 | ||
166 | if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) { | |
167 | if (!s->initial_count) { | |
168 | return false; | |
169 | } | |
170 | d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * | |
171 | ((uint64_t)s->initial_count + 1); | |
172 | } else { | |
173 | if (d >= s->initial_count) { | |
174 | return false; | |
175 | } | |
176 | d = (uint64_t)s->initial_count + 1; | |
177 | } | |
178 | s->next_time = s->initial_count_load_time + (d << s->count_shift); | |
179 | s->timer_expiry = s->next_time; | |
180 | return true; | |
181 | } | |
182 | ||
d3b0c9e9 | 183 | void apic_init_reset(DeviceState *dev) |
dae01685 | 184 | { |
927411fa PB |
185 | APICCommonState *s; |
186 | APICCommonClass *info; | |
dae01685 JK |
187 | int i; |
188 | ||
927411fa | 189 | if (!dev) { |
dae01685 JK |
190 | return; |
191 | } | |
927411fa | 192 | s = APIC_COMMON(dev); |
dae01685 JK |
193 | s->tpr = 0; |
194 | s->spurious_vec = 0xff; | |
195 | s->log_dest = 0; | |
196 | s->dest_mode = 0xf; | |
197 | memset(s->isr, 0, sizeof(s->isr)); | |
198 | memset(s->tmr, 0, sizeof(s->tmr)); | |
199 | memset(s->irr, 0, sizeof(s->irr)); | |
200 | for (i = 0; i < APIC_LVT_NB; i++) { | |
201 | s->lvt[i] = APIC_LVT_MASKED; | |
202 | } | |
203 | s->esr = 0; | |
204 | memset(s->icr, 0, sizeof(s->icr)); | |
205 | s->divide_conf = 0; | |
206 | s->count_shift = 0; | |
207 | s->initial_count = 0; | |
208 | s->initial_count_load_time = 0; | |
209 | s->next_time = 0; | |
7b4d915e | 210 | s->wait_for_sipi = !cpu_is_bsp(s->cpu); |
dae01685 | 211 | |
7a380ca3 | 212 | if (s->timer) { |
bc72ad67 | 213 | timer_del(s->timer); |
7a380ca3 JK |
214 | } |
215 | s->timer_expiry = -1; | |
575a6f40 | 216 | |
927411fa | 217 | info = APIC_COMMON_GET_CLASS(s); |
575a6f40 PB |
218 | if (info->reset) { |
219 | info->reset(s); | |
220 | } | |
dae01685 JK |
221 | } |
222 | ||
9cb11fd7 | 223 | void apic_designate_bsp(DeviceState *dev, bool bsp) |
dd673288 | 224 | { |
d3b0c9e9 | 225 | if (dev == NULL) { |
dd673288 IM |
226 | return; |
227 | } | |
228 | ||
d3b0c9e9 | 229 | APICCommonState *s = APIC_COMMON(dev); |
9cb11fd7 NA |
230 | if (bsp) { |
231 | s->apicbase |= MSR_IA32_APICBASE_BSP; | |
232 | } else { | |
233 | s->apicbase &= ~MSR_IA32_APICBASE_BSP; | |
234 | } | |
dd673288 IM |
235 | } |
236 | ||
d3b0c9e9 | 237 | static void apic_reset_common(DeviceState *dev) |
dae01685 | 238 | { |
d3b0c9e9 | 239 | APICCommonState *s = APIC_COMMON(dev); |
e5ad936b | 240 | APICCommonClass *info = APIC_COMMON_GET_CLASS(s); |
81329754 | 241 | uint32_t bsp; |
dae01685 | 242 | |
81329754 DL |
243 | bsp = s->apicbase & MSR_IA32_APICBASE_BSP; |
244 | s->apicbase = APIC_DEFAULT_ADDRESS | bsp | MSR_IA32_APICBASE_ENABLE; | |
dae01685 | 245 | |
e5ad936b JK |
246 | s->vapic_paddr = 0; |
247 | info->vapic_base_update(s); | |
248 | ||
d3b0c9e9 | 249 | apic_init_reset(dev); |
dae01685 JK |
250 | } |
251 | ||
252 | /* This function is only used for old state version 1 and 2 */ | |
253 | static int apic_load_old(QEMUFile *f, void *opaque, int version_id) | |
254 | { | |
255 | APICCommonState *s = opaque; | |
a4aecd28 | 256 | APICCommonClass *info = APIC_COMMON_GET_CLASS(s); |
dae01685 JK |
257 | int i; |
258 | ||
259 | if (version_id > 2) { | |
260 | return -EINVAL; | |
261 | } | |
262 | ||
263 | /* XXX: what if the base changes? (registered memory regions) */ | |
264 | qemu_get_be32s(f, &s->apicbase); | |
265 | qemu_get_8s(f, &s->id); | |
266 | qemu_get_8s(f, &s->arb_id); | |
267 | qemu_get_8s(f, &s->tpr); | |
268 | qemu_get_be32s(f, &s->spurious_vec); | |
269 | qemu_get_8s(f, &s->log_dest); | |
270 | qemu_get_8s(f, &s->dest_mode); | |
271 | for (i = 0; i < 8; i++) { | |
272 | qemu_get_be32s(f, &s->isr[i]); | |
273 | qemu_get_be32s(f, &s->tmr[i]); | |
274 | qemu_get_be32s(f, &s->irr[i]); | |
275 | } | |
276 | for (i = 0; i < APIC_LVT_NB; i++) { | |
277 | qemu_get_be32s(f, &s->lvt[i]); | |
278 | } | |
279 | qemu_get_be32s(f, &s->esr); | |
280 | qemu_get_be32s(f, &s->icr[0]); | |
281 | qemu_get_be32s(f, &s->icr[1]); | |
282 | qemu_get_be32s(f, &s->divide_conf); | |
283 | s->count_shift = qemu_get_be32(f); | |
284 | qemu_get_be32s(f, &s->initial_count); | |
285 | s->initial_count_load_time = qemu_get_be64(f); | |
286 | s->next_time = qemu_get_be64(f); | |
287 | ||
288 | if (version_id >= 2) { | |
a4aecd28 JK |
289 | s->timer_expiry = qemu_get_be64(f); |
290 | } | |
291 | ||
292 | if (info->post_load) { | |
293 | info->post_load(s); | |
dae01685 JK |
294 | } |
295 | return 0; | |
296 | } | |
297 | ||
f6e98444 IM |
298 | static const VMStateDescription vmstate_apic_common; |
299 | ||
494c2717 | 300 | static void apic_common_realize(DeviceState *dev, Error **errp) |
dae01685 | 301 | { |
999e12bb AL |
302 | APICCommonState *s = APIC_COMMON(dev); |
303 | APICCommonClass *info; | |
e5ad936b | 304 | static DeviceState *vapic; |
f6e98444 | 305 | int instance_id = s->id; |
dae01685 | 306 | |
999e12bb | 307 | info = APIC_COMMON_GET_CLASS(s); |
494c2717 | 308 | info->realize(dev, errp); |
e5ad936b | 309 | |
a9605e03 JK |
310 | /* Note: We need at least 1M to map the VAPIC option ROM */ |
311 | if (!vapic && s->vapic_control & VAPIC_ENABLE_MASK && | |
312 | ram_size >= 1024 * 1024) { | |
e5ad936b JK |
313 | vapic = sysbus_create_simple("kvmvapic", -1, NULL); |
314 | } | |
315 | s->vapic = vapic; | |
316 | if (apic_report_tpr_access && info->enable_tpr_reporting) { | |
317 | info->enable_tpr_reporting(s, true); | |
318 | } | |
319 | ||
f6e98444 IM |
320 | if (s->legacy_instance_id) { |
321 | instance_id = -1; | |
322 | } | |
323 | vmstate_register_with_alias_id(NULL, instance_id, &vmstate_apic_common, | |
324 | s, -1, 0); | |
dae01685 JK |
325 | } |
326 | ||
9c156f9d IM |
327 | static void apic_common_unrealize(DeviceState *dev, Error **errp) |
328 | { | |
329 | APICCommonState *s = APIC_COMMON(dev); | |
330 | APICCommonClass *info = APIC_COMMON_GET_CLASS(s); | |
331 | ||
f6e98444 | 332 | vmstate_unregister(NULL, &vmstate_apic_common, s); |
9c156f9d IM |
333 | info->unrealize(dev, errp); |
334 | ||
335 | if (apic_report_tpr_access && info->enable_tpr_reporting) { | |
336 | info->enable_tpr_reporting(s, false); | |
337 | } | |
338 | } | |
339 | ||
c2c00148 PD |
340 | static int apic_pre_load(void *opaque) |
341 | { | |
342 | APICCommonState *s = APIC_COMMON(opaque); | |
343 | ||
344 | /* The default is !cpu_is_bsp(s->cpu), but the common value is 0 | |
345 | * so that's what apic_common_sipi_needed checks for. Reset to | |
346 | * the value that is assumed when the apic_sipi subsection is | |
347 | * absent. | |
348 | */ | |
349 | s->wait_for_sipi = 0; | |
350 | return 0; | |
351 | } | |
352 | ||
e5ad936b JK |
353 | static void apic_dispatch_pre_save(void *opaque) |
354 | { | |
355 | APICCommonState *s = APIC_COMMON(opaque); | |
356 | APICCommonClass *info = APIC_COMMON_GET_CLASS(s); | |
357 | ||
358 | if (info->pre_save) { | |
359 | info->pre_save(s); | |
360 | } | |
361 | } | |
362 | ||
7a380ca3 JK |
363 | static int apic_dispatch_post_load(void *opaque, int version_id) |
364 | { | |
999e12bb AL |
365 | APICCommonState *s = APIC_COMMON(opaque); |
366 | APICCommonClass *info = APIC_COMMON_GET_CLASS(s); | |
7a380ca3 JK |
367 | |
368 | if (info->post_load) { | |
369 | info->post_load(s); | |
370 | } | |
371 | return 0; | |
372 | } | |
373 | ||
c2c00148 PD |
374 | static bool apic_common_sipi_needed(void *opaque) |
375 | { | |
376 | APICCommonState *s = APIC_COMMON(opaque); | |
377 | return s->wait_for_sipi != 0; | |
378 | } | |
379 | ||
380 | static const VMStateDescription vmstate_apic_common_sipi = { | |
381 | .name = "apic_sipi", | |
382 | .version_id = 1, | |
383 | .minimum_version_id = 1, | |
5cd8cada | 384 | .needed = apic_common_sipi_needed, |
c2c00148 PD |
385 | .fields = (VMStateField[]) { |
386 | VMSTATE_INT32(sipi_vector, APICCommonState), | |
387 | VMSTATE_INT32(wait_for_sipi, APICCommonState), | |
388 | VMSTATE_END_OF_LIST() | |
389 | } | |
390 | }; | |
391 | ||
dae01685 JK |
392 | static const VMStateDescription vmstate_apic_common = { |
393 | .name = "apic", | |
394 | .version_id = 3, | |
395 | .minimum_version_id = 3, | |
396 | .minimum_version_id_old = 1, | |
397 | .load_state_old = apic_load_old, | |
c2c00148 | 398 | .pre_load = apic_pre_load, |
e5ad936b | 399 | .pre_save = apic_dispatch_pre_save, |
7a380ca3 | 400 | .post_load = apic_dispatch_post_load, |
dae01685 JK |
401 | .fields = (VMStateField[]) { |
402 | VMSTATE_UINT32(apicbase, APICCommonState), | |
403 | VMSTATE_UINT8(id, APICCommonState), | |
404 | VMSTATE_UINT8(arb_id, APICCommonState), | |
405 | VMSTATE_UINT8(tpr, APICCommonState), | |
406 | VMSTATE_UINT32(spurious_vec, APICCommonState), | |
407 | VMSTATE_UINT8(log_dest, APICCommonState), | |
408 | VMSTATE_UINT8(dest_mode, APICCommonState), | |
409 | VMSTATE_UINT32_ARRAY(isr, APICCommonState, 8), | |
410 | VMSTATE_UINT32_ARRAY(tmr, APICCommonState, 8), | |
411 | VMSTATE_UINT32_ARRAY(irr, APICCommonState, 8), | |
412 | VMSTATE_UINT32_ARRAY(lvt, APICCommonState, APIC_LVT_NB), | |
413 | VMSTATE_UINT32(esr, APICCommonState), | |
414 | VMSTATE_UINT32_ARRAY(icr, APICCommonState, 2), | |
415 | VMSTATE_UINT32(divide_conf, APICCommonState), | |
416 | VMSTATE_INT32(count_shift, APICCommonState), | |
417 | VMSTATE_UINT32(initial_count, APICCommonState), | |
418 | VMSTATE_INT64(initial_count_load_time, APICCommonState), | |
419 | VMSTATE_INT64(next_time, APICCommonState), | |
7a380ca3 JK |
420 | VMSTATE_INT64(timer_expiry, |
421 | APICCommonState), /* open-coded timer state */ | |
dae01685 | 422 | VMSTATE_END_OF_LIST() |
c2c00148 | 423 | }, |
5cd8cada JQ |
424 | .subsections = (const VMStateDescription*[]) { |
425 | &vmstate_apic_common_sipi, | |
426 | NULL | |
dae01685 JK |
427 | } |
428 | }; | |
429 | ||
430 | static Property apic_properties_common[] = { | |
431 | DEFINE_PROP_UINT8("id", APICCommonState, id, -1), | |
aa93200b | 432 | DEFINE_PROP_UINT8("version", APICCommonState, version, 0x14), |
e5ad936b JK |
433 | DEFINE_PROP_BIT("vapic", APICCommonState, vapic_control, VAPIC_ENABLE_BIT, |
434 | true), | |
f6e98444 IM |
435 | DEFINE_PROP_BOOL("legacy-instance-id", APICCommonState, legacy_instance_id, |
436 | false), | |
dae01685 JK |
437 | DEFINE_PROP_END_OF_LIST(), |
438 | }; | |
439 | ||
999e12bb AL |
440 | static void apic_common_class_init(ObjectClass *klass, void *data) |
441 | { | |
39bffca2 | 442 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 443 | |
39bffca2 | 444 | dc->reset = apic_reset_common; |
39bffca2 | 445 | dc->props = apic_properties_common; |
46232aaa | 446 | dc->realize = apic_common_realize; |
9c156f9d | 447 | dc->unrealize = apic_common_unrealize; |
f37a4374 MA |
448 | /* |
449 | * Reason: APIC and CPU need to be wired up by | |
450 | * x86_cpu_apic_create() | |
451 | */ | |
452 | dc->cannot_instantiate_with_device_add_yet = true; | |
999e12bb | 453 | } |
dae01685 | 454 | |
8c43a6f0 | 455 | static const TypeInfo apic_common_type = { |
999e12bb | 456 | .name = TYPE_APIC_COMMON, |
46232aaa | 457 | .parent = TYPE_DEVICE, |
999e12bb AL |
458 | .instance_size = sizeof(APICCommonState), |
459 | .class_size = sizeof(APICCommonClass), | |
460 | .class_init = apic_common_class_init, | |
461 | .abstract = true, | |
462 | }; | |
463 | ||
d3b0c9e9 | 464 | static void apic_common_register_types(void) |
999e12bb AL |
465 | { |
466 | type_register_static(&apic_common_type); | |
467 | } | |
468 | ||
d3b0c9e9 | 469 | type_init(apic_common_register_types) |