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dae01685 JK |
1 | /* |
2 | * APIC support - common bits of emulated and KVM kernel model | |
3 | * | |
4 | * Copyright (c) 2004-2005 Fabrice Bellard | |
5 | * Copyright (c) 2011 Jan Kiszka, Siemens AG | |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
18 | * License along with this library; if not, see <http://www.gnu.org/licenses/> | |
19 | */ | |
0b8fa32f | 20 | |
b6a0aa05 | 21 | #include "qemu/osdep.h" |
2f114315 | 22 | #include "qemu/error-report.h" |
0b8fa32f | 23 | #include "qemu/module.h" |
da34e65c | 24 | #include "qapi/error.h" |
33c11879 | 25 | #include "cpu.h" |
33d7a288 | 26 | #include "qapi/visitor.h" |
0d09e41a PB |
27 | #include "hw/i386/apic.h" |
28 | #include "hw/i386/apic_internal.h" | |
dae01685 | 29 | #include "trace.h" |
b0cb0a66 | 30 | #include "sysemu/hax.h" |
9c17d615 | 31 | #include "sysemu/kvm.h" |
a27bd6c7 | 32 | #include "hw/qdev-properties.h" |
53a89e26 | 33 | #include "hw/sysbus.h" |
d6454270 | 34 | #include "migration/vmstate.h" |
dae01685 JK |
35 | |
36 | static int apic_irq_delivered; | |
e5ad936b | 37 | bool apic_report_tpr_access; |
dae01685 | 38 | |
d3b0c9e9 | 39 | void cpu_set_apic_base(DeviceState *dev, uint64_t val) |
dae01685 | 40 | { |
dae01685 JK |
41 | trace_cpu_set_apic_base(val); |
42 | ||
d3b0c9e9 XZ |
43 | if (dev) { |
44 | APICCommonState *s = APIC_COMMON(dev); | |
999e12bb | 45 | APICCommonClass *info = APIC_COMMON_GET_CLASS(s); |
facb07cd IM |
46 | /* switching to x2APIC, reset possibly modified xAPIC ID */ |
47 | if (!(s->apicbase & MSR_IA32_APICBASE_EXTD) && | |
48 | (val & MSR_IA32_APICBASE_EXTD)) { | |
49 | s->id = s->initial_apic_id; | |
50 | } | |
dae01685 JK |
51 | info->set_base(s, val); |
52 | } | |
53 | } | |
54 | ||
d3b0c9e9 | 55 | uint64_t cpu_get_apic_base(DeviceState *dev) |
dae01685 | 56 | { |
d3b0c9e9 XZ |
57 | if (dev) { |
58 | APICCommonState *s = APIC_COMMON(dev); | |
999e12bb AL |
59 | trace_cpu_get_apic_base((uint64_t)s->apicbase); |
60 | return s->apicbase; | |
61 | } else { | |
dd673288 IM |
62 | trace_cpu_get_apic_base(MSR_IA32_APICBASE_BSP); |
63 | return MSR_IA32_APICBASE_BSP; | |
999e12bb | 64 | } |
dae01685 JK |
65 | } |
66 | ||
d3b0c9e9 | 67 | void cpu_set_apic_tpr(DeviceState *dev, uint8_t val) |
dae01685 | 68 | { |
999e12bb AL |
69 | APICCommonState *s; |
70 | APICCommonClass *info; | |
dae01685 | 71 | |
d3b0c9e9 | 72 | if (!dev) { |
999e12bb | 73 | return; |
dae01685 | 74 | } |
999e12bb | 75 | |
d3b0c9e9 | 76 | s = APIC_COMMON(dev); |
999e12bb AL |
77 | info = APIC_COMMON_GET_CLASS(s); |
78 | ||
79 | info->set_tpr(s, val); | |
dae01685 JK |
80 | } |
81 | ||
d3b0c9e9 | 82 | uint8_t cpu_get_apic_tpr(DeviceState *dev) |
e5ad936b JK |
83 | { |
84 | APICCommonState *s; | |
85 | APICCommonClass *info; | |
86 | ||
d3b0c9e9 | 87 | if (!dev) { |
e5ad936b JK |
88 | return 0; |
89 | } | |
90 | ||
d3b0c9e9 | 91 | s = APIC_COMMON(dev); |
e5ad936b JK |
92 | info = APIC_COMMON_GET_CLASS(s); |
93 | ||
94 | return info->get_tpr(s); | |
95 | } | |
96 | ||
d3b0c9e9 | 97 | void apic_enable_tpr_access_reporting(DeviceState *dev, bool enable) |
e5ad936b | 98 | { |
d3b0c9e9 | 99 | APICCommonState *s = APIC_COMMON(dev); |
e5ad936b JK |
100 | APICCommonClass *info = APIC_COMMON_GET_CLASS(s); |
101 | ||
102 | apic_report_tpr_access = enable; | |
103 | if (info->enable_tpr_reporting) { | |
104 | info->enable_tpr_reporting(s, enable); | |
105 | } | |
106 | } | |
107 | ||
d3b0c9e9 | 108 | void apic_enable_vapic(DeviceState *dev, hwaddr paddr) |
dae01685 | 109 | { |
d3b0c9e9 | 110 | APICCommonState *s = APIC_COMMON(dev); |
e5ad936b | 111 | APICCommonClass *info = APIC_COMMON_GET_CLASS(s); |
dae01685 | 112 | |
e5ad936b JK |
113 | s->vapic_paddr = paddr; |
114 | info->vapic_base_update(s); | |
dae01685 JK |
115 | } |
116 | ||
d3b0c9e9 | 117 | void apic_handle_tpr_access_report(DeviceState *dev, target_ulong ip, |
d362e757 JK |
118 | TPRAccess access) |
119 | { | |
d3b0c9e9 | 120 | APICCommonState *s = APIC_COMMON(dev); |
e5ad936b | 121 | |
d77953b9 | 122 | vapic_report_tpr_access(s->vapic, CPU(s->cpu), ip, access); |
d362e757 JK |
123 | } |
124 | ||
dae01685 JK |
125 | void apic_report_irq_delivered(int delivered) |
126 | { | |
127 | apic_irq_delivered += delivered; | |
128 | ||
129 | trace_apic_report_irq_delivered(apic_irq_delivered); | |
130 | } | |
131 | ||
132 | void apic_reset_irq_delivered(void) | |
133 | { | |
9bcec938 FCE |
134 | /* Copy this into a local variable to encourage gcc to emit a plain |
135 | * register for a sys/sdt.h marker. For details on this workaround, see: | |
136 | * https://sourceware.org/bugzilla/show_bug.cgi?id=13296 | |
137 | */ | |
138 | volatile int a_i_d = apic_irq_delivered; | |
139 | trace_apic_reset_irq_delivered(a_i_d); | |
dae01685 JK |
140 | |
141 | apic_irq_delivered = 0; | |
142 | } | |
143 | ||
144 | int apic_get_irq_delivered(void) | |
145 | { | |
146 | trace_apic_get_irq_delivered(apic_irq_delivered); | |
147 | ||
148 | return apic_irq_delivered; | |
149 | } | |
150 | ||
d3b0c9e9 | 151 | void apic_deliver_nmi(DeviceState *dev) |
dae01685 | 152 | { |
d3b0c9e9 | 153 | APICCommonState *s = APIC_COMMON(dev); |
999e12bb | 154 | APICCommonClass *info = APIC_COMMON_GET_CLASS(s); |
dae01685 | 155 | |
dae01685 JK |
156 | info->external_nmi(s); |
157 | } | |
158 | ||
7a380ca3 JK |
159 | bool apic_next_timer(APICCommonState *s, int64_t current_time) |
160 | { | |
161 | int64_t d; | |
162 | ||
163 | /* We need to store the timer state separately to support APIC | |
164 | * implementations that maintain a non-QEMU timer, e.g. inside the | |
165 | * host kernel. This open-coded state allows us to migrate between | |
166 | * both models. */ | |
167 | s->timer_expiry = -1; | |
168 | ||
169 | if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED) { | |
170 | return false; | |
171 | } | |
172 | ||
173 | d = (current_time - s->initial_count_load_time) >> s->count_shift; | |
174 | ||
175 | if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) { | |
176 | if (!s->initial_count) { | |
177 | return false; | |
178 | } | |
179 | d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * | |
180 | ((uint64_t)s->initial_count + 1); | |
181 | } else { | |
182 | if (d >= s->initial_count) { | |
183 | return false; | |
184 | } | |
185 | d = (uint64_t)s->initial_count + 1; | |
186 | } | |
187 | s->next_time = s->initial_count_load_time + (d << s->count_shift); | |
188 | s->timer_expiry = s->next_time; | |
189 | return true; | |
190 | } | |
191 | ||
d3b0c9e9 | 192 | void apic_init_reset(DeviceState *dev) |
dae01685 | 193 | { |
927411fa PB |
194 | APICCommonState *s; |
195 | APICCommonClass *info; | |
dae01685 JK |
196 | int i; |
197 | ||
927411fa | 198 | if (!dev) { |
dae01685 JK |
199 | return; |
200 | } | |
927411fa | 201 | s = APIC_COMMON(dev); |
dae01685 JK |
202 | s->tpr = 0; |
203 | s->spurious_vec = 0xff; | |
204 | s->log_dest = 0; | |
205 | s->dest_mode = 0xf; | |
206 | memset(s->isr, 0, sizeof(s->isr)); | |
207 | memset(s->tmr, 0, sizeof(s->tmr)); | |
208 | memset(s->irr, 0, sizeof(s->irr)); | |
209 | for (i = 0; i < APIC_LVT_NB; i++) { | |
210 | s->lvt[i] = APIC_LVT_MASKED; | |
211 | } | |
212 | s->esr = 0; | |
213 | memset(s->icr, 0, sizeof(s->icr)); | |
214 | s->divide_conf = 0; | |
215 | s->count_shift = 0; | |
216 | s->initial_count = 0; | |
217 | s->initial_count_load_time = 0; | |
218 | s->next_time = 0; | |
7b4d915e | 219 | s->wait_for_sipi = !cpu_is_bsp(s->cpu); |
dae01685 | 220 | |
7a380ca3 | 221 | if (s->timer) { |
bc72ad67 | 222 | timer_del(s->timer); |
7a380ca3 JK |
223 | } |
224 | s->timer_expiry = -1; | |
575a6f40 | 225 | |
927411fa | 226 | info = APIC_COMMON_GET_CLASS(s); |
575a6f40 PB |
227 | if (info->reset) { |
228 | info->reset(s); | |
229 | } | |
dae01685 JK |
230 | } |
231 | ||
9cb11fd7 | 232 | void apic_designate_bsp(DeviceState *dev, bool bsp) |
dd673288 | 233 | { |
d3b0c9e9 | 234 | if (dev == NULL) { |
dd673288 IM |
235 | return; |
236 | } | |
237 | ||
d3b0c9e9 | 238 | APICCommonState *s = APIC_COMMON(dev); |
9cb11fd7 NA |
239 | if (bsp) { |
240 | s->apicbase |= MSR_IA32_APICBASE_BSP; | |
241 | } else { | |
242 | s->apicbase &= ~MSR_IA32_APICBASE_BSP; | |
243 | } | |
dd673288 IM |
244 | } |
245 | ||
d3b0c9e9 | 246 | static void apic_reset_common(DeviceState *dev) |
dae01685 | 247 | { |
d3b0c9e9 | 248 | APICCommonState *s = APIC_COMMON(dev); |
e5ad936b | 249 | APICCommonClass *info = APIC_COMMON_GET_CLASS(s); |
81329754 | 250 | uint32_t bsp; |
dae01685 | 251 | |
81329754 DL |
252 | bsp = s->apicbase & MSR_IA32_APICBASE_BSP; |
253 | s->apicbase = APIC_DEFAULT_ADDRESS | bsp | MSR_IA32_APICBASE_ENABLE; | |
4c34897a | 254 | s->id = s->initial_apic_id; |
dae01685 | 255 | |
f65e8212 PD |
256 | apic_reset_irq_delivered(); |
257 | ||
e5ad936b JK |
258 | s->vapic_paddr = 0; |
259 | info->vapic_base_update(s); | |
260 | ||
d3b0c9e9 | 261 | apic_init_reset(dev); |
dae01685 JK |
262 | } |
263 | ||
f6e98444 IM |
264 | static const VMStateDescription vmstate_apic_common; |
265 | ||
494c2717 | 266 | static void apic_common_realize(DeviceState *dev, Error **errp) |
dae01685 | 267 | { |
999e12bb AL |
268 | APICCommonState *s = APIC_COMMON(dev); |
269 | APICCommonClass *info; | |
e5ad936b | 270 | static DeviceState *vapic; |
0ab99486 PX |
271 | uint32_t instance_id = s->initial_apic_id; |
272 | ||
273 | /* Normally initial APIC ID should be no more than hundreds */ | |
274 | assert(instance_id != VMSTATE_INSTANCE_ID_ANY); | |
dae01685 | 275 | |
999e12bb | 276 | info = APIC_COMMON_GET_CLASS(s); |
494c2717 | 277 | info->realize(dev, errp); |
e5ad936b | 278 | |
a9605e03 JK |
279 | /* Note: We need at least 1M to map the VAPIC option ROM */ |
280 | if (!vapic && s->vapic_control & VAPIC_ENABLE_MASK && | |
b0cb0a66 | 281 | !hax_enabled() && ram_size >= 1024 * 1024) { |
e5ad936b JK |
282 | vapic = sysbus_create_simple("kvmvapic", -1, NULL); |
283 | } | |
284 | s->vapic = vapic; | |
285 | if (apic_report_tpr_access && info->enable_tpr_reporting) { | |
286 | info->enable_tpr_reporting(s, true); | |
287 | } | |
288 | ||
f6e98444 | 289 | if (s->legacy_instance_id) { |
1df2c9a2 | 290 | instance_id = VMSTATE_INSTANCE_ID_ANY; |
f6e98444 IM |
291 | } |
292 | vmstate_register_with_alias_id(NULL, instance_id, &vmstate_apic_common, | |
bc5c4f21 | 293 | s, -1, 0, NULL); |
dae01685 JK |
294 | } |
295 | ||
b69c3c21 | 296 | static void apic_common_unrealize(DeviceState *dev) |
9c156f9d IM |
297 | { |
298 | APICCommonState *s = APIC_COMMON(dev); | |
299 | APICCommonClass *info = APIC_COMMON_GET_CLASS(s); | |
300 | ||
f6e98444 | 301 | vmstate_unregister(NULL, &vmstate_apic_common, s); |
b69c3c21 | 302 | info->unrealize(dev); |
9c156f9d IM |
303 | |
304 | if (apic_report_tpr_access && info->enable_tpr_reporting) { | |
305 | info->enable_tpr_reporting(s, false); | |
306 | } | |
307 | } | |
308 | ||
c2c00148 PD |
309 | static int apic_pre_load(void *opaque) |
310 | { | |
311 | APICCommonState *s = APIC_COMMON(opaque); | |
312 | ||
313 | /* The default is !cpu_is_bsp(s->cpu), but the common value is 0 | |
314 | * so that's what apic_common_sipi_needed checks for. Reset to | |
315 | * the value that is assumed when the apic_sipi subsection is | |
316 | * absent. | |
317 | */ | |
318 | s->wait_for_sipi = 0; | |
319 | return 0; | |
320 | } | |
321 | ||
44b1ff31 | 322 | static int apic_dispatch_pre_save(void *opaque) |
e5ad936b JK |
323 | { |
324 | APICCommonState *s = APIC_COMMON(opaque); | |
325 | APICCommonClass *info = APIC_COMMON_GET_CLASS(s); | |
326 | ||
327 | if (info->pre_save) { | |
328 | info->pre_save(s); | |
329 | } | |
44b1ff31 DDAG |
330 | |
331 | return 0; | |
e5ad936b JK |
332 | } |
333 | ||
7a380ca3 JK |
334 | static int apic_dispatch_post_load(void *opaque, int version_id) |
335 | { | |
999e12bb AL |
336 | APICCommonState *s = APIC_COMMON(opaque); |
337 | APICCommonClass *info = APIC_COMMON_GET_CLASS(s); | |
7a380ca3 JK |
338 | |
339 | if (info->post_load) { | |
340 | info->post_load(s); | |
341 | } | |
342 | return 0; | |
343 | } | |
344 | ||
c2c00148 PD |
345 | static bool apic_common_sipi_needed(void *opaque) |
346 | { | |
347 | APICCommonState *s = APIC_COMMON(opaque); | |
348 | return s->wait_for_sipi != 0; | |
349 | } | |
350 | ||
351 | static const VMStateDescription vmstate_apic_common_sipi = { | |
352 | .name = "apic_sipi", | |
353 | .version_id = 1, | |
354 | .minimum_version_id = 1, | |
5cd8cada | 355 | .needed = apic_common_sipi_needed, |
c2c00148 PD |
356 | .fields = (VMStateField[]) { |
357 | VMSTATE_INT32(sipi_vector, APICCommonState), | |
358 | VMSTATE_INT32(wait_for_sipi, APICCommonState), | |
359 | VMSTATE_END_OF_LIST() | |
360 | } | |
361 | }; | |
362 | ||
dae01685 JK |
363 | static const VMStateDescription vmstate_apic_common = { |
364 | .name = "apic", | |
365 | .version_id = 3, | |
366 | .minimum_version_id = 3, | |
c2c00148 | 367 | .pre_load = apic_pre_load, |
e5ad936b | 368 | .pre_save = apic_dispatch_pre_save, |
7a380ca3 | 369 | .post_load = apic_dispatch_post_load, |
dae01685 JK |
370 | .fields = (VMStateField[]) { |
371 | VMSTATE_UINT32(apicbase, APICCommonState), | |
372 | VMSTATE_UINT8(id, APICCommonState), | |
373 | VMSTATE_UINT8(arb_id, APICCommonState), | |
374 | VMSTATE_UINT8(tpr, APICCommonState), | |
375 | VMSTATE_UINT32(spurious_vec, APICCommonState), | |
376 | VMSTATE_UINT8(log_dest, APICCommonState), | |
377 | VMSTATE_UINT8(dest_mode, APICCommonState), | |
378 | VMSTATE_UINT32_ARRAY(isr, APICCommonState, 8), | |
379 | VMSTATE_UINT32_ARRAY(tmr, APICCommonState, 8), | |
380 | VMSTATE_UINT32_ARRAY(irr, APICCommonState, 8), | |
381 | VMSTATE_UINT32_ARRAY(lvt, APICCommonState, APIC_LVT_NB), | |
382 | VMSTATE_UINT32(esr, APICCommonState), | |
383 | VMSTATE_UINT32_ARRAY(icr, APICCommonState, 2), | |
384 | VMSTATE_UINT32(divide_conf, APICCommonState), | |
385 | VMSTATE_INT32(count_shift, APICCommonState), | |
386 | VMSTATE_UINT32(initial_count, APICCommonState), | |
387 | VMSTATE_INT64(initial_count_load_time, APICCommonState), | |
388 | VMSTATE_INT64(next_time, APICCommonState), | |
7a380ca3 JK |
389 | VMSTATE_INT64(timer_expiry, |
390 | APICCommonState), /* open-coded timer state */ | |
dae01685 | 391 | VMSTATE_END_OF_LIST() |
c2c00148 | 392 | }, |
5cd8cada JQ |
393 | .subsections = (const VMStateDescription*[]) { |
394 | &vmstate_apic_common_sipi, | |
395 | NULL | |
dae01685 JK |
396 | } |
397 | }; | |
398 | ||
399 | static Property apic_properties_common[] = { | |
aa93200b | 400 | DEFINE_PROP_UINT8("version", APICCommonState, version, 0x14), |
e5ad936b JK |
401 | DEFINE_PROP_BIT("vapic", APICCommonState, vapic_control, VAPIC_ENABLE_BIT, |
402 | true), | |
f6e98444 IM |
403 | DEFINE_PROP_BOOL("legacy-instance-id", APICCommonState, legacy_instance_id, |
404 | false), | |
dae01685 JK |
405 | DEFINE_PROP_END_OF_LIST(), |
406 | }; | |
407 | ||
33d7a288 IM |
408 | static void apic_common_get_id(Object *obj, Visitor *v, const char *name, |
409 | void *opaque, Error **errp) | |
410 | { | |
411 | APICCommonState *s = APIC_COMMON(obj); | |
d528227d | 412 | uint32_t value; |
33d7a288 IM |
413 | |
414 | value = s->apicbase & MSR_IA32_APICBASE_EXTD ? s->initial_apic_id : s->id; | |
d528227d | 415 | visit_type_uint32(v, name, &value, errp); |
33d7a288 IM |
416 | } |
417 | ||
418 | static void apic_common_set_id(Object *obj, Visitor *v, const char *name, | |
419 | void *opaque, Error **errp) | |
420 | { | |
421 | APICCommonState *s = APIC_COMMON(obj); | |
422 | DeviceState *dev = DEVICE(obj); | |
d528227d | 423 | uint32_t value; |
33d7a288 IM |
424 | |
425 | if (dev->realized) { | |
426 | qdev_prop_set_after_realize(dev, name, errp); | |
427 | return; | |
428 | } | |
429 | ||
668f62ec | 430 | if (!visit_type_uint32(v, name, &value, errp)) { |
33d7a288 IM |
431 | return; |
432 | } | |
433 | ||
434 | s->initial_apic_id = value; | |
435 | s->id = (uint8_t)value; | |
436 | } | |
437 | ||
438 | static void apic_common_initfn(Object *obj) | |
439 | { | |
440 | APICCommonState *s = APIC_COMMON(obj); | |
441 | ||
442 | s->id = s->initial_apic_id = -1; | |
d528227d | 443 | object_property_add(obj, "id", "uint32", |
33d7a288 | 444 | apic_common_get_id, |
d2623129 | 445 | apic_common_set_id, NULL, NULL); |
33d7a288 IM |
446 | } |
447 | ||
999e12bb AL |
448 | static void apic_common_class_init(ObjectClass *klass, void *data) |
449 | { | |
39bffca2 | 450 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 451 | |
39bffca2 | 452 | dc->reset = apic_reset_common; |
4f67d30b | 453 | device_class_set_props(dc, apic_properties_common); |
46232aaa | 454 | dc->realize = apic_common_realize; |
9c156f9d | 455 | dc->unrealize = apic_common_unrealize; |
f37a4374 MA |
456 | /* |
457 | * Reason: APIC and CPU need to be wired up by | |
458 | * x86_cpu_apic_create() | |
459 | */ | |
e90f2a8c | 460 | dc->user_creatable = false; |
999e12bb | 461 | } |
dae01685 | 462 | |
8c43a6f0 | 463 | static const TypeInfo apic_common_type = { |
999e12bb | 464 | .name = TYPE_APIC_COMMON, |
46232aaa | 465 | .parent = TYPE_DEVICE, |
999e12bb | 466 | .instance_size = sizeof(APICCommonState), |
33d7a288 | 467 | .instance_init = apic_common_initfn, |
999e12bb AL |
468 | .class_size = sizeof(APICCommonClass), |
469 | .class_init = apic_common_class_init, | |
470 | .abstract = true, | |
471 | }; | |
472 | ||
d3b0c9e9 | 473 | static void apic_common_register_types(void) |
999e12bb AL |
474 | { |
475 | type_register_static(&apic_common_type); | |
476 | } | |
477 | ||
d3b0c9e9 | 478 | type_init(apic_common_register_types) |