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5fafdf24 | 1 | /* |
9ee6e8bb | 2 | * ARM Generic/Distributed Interrupt Controller |
e69954b9 | 3 | * |
9ee6e8bb | 4 | * Copyright (c) 2006-2007 CodeSourcery. |
e69954b9 PB |
5 | * Written by Paul Brook |
6 | * | |
8e31bf38 | 7 | * This code is licensed under the GPL. |
e69954b9 PB |
8 | */ |
9 | ||
9ee6e8bb | 10 | /* This file contains implementation code for the RealView EB interrupt |
0d256bdc PM |
11 | * controller, MPCore distributed interrupt controller and ARMv7-M |
12 | * Nested Vectored Interrupt Controller. | |
13 | * It is compiled in two ways: | |
14 | * (1) as a standalone file to produce a sysbus device which is a GIC | |
15 | * that can be used on the realview board and as one of the builtin | |
16 | * private peripherals for the ARM MP CPUs (11MPCore, A9, etc) | |
17 | * (2) by being directly #included into armv7m_nvic.c to produce the | |
18 | * armv7m_nvic device. | |
19 | */ | |
e69954b9 | 20 | |
8ef94f0b | 21 | #include "qemu/osdep.h" |
64552b6b | 22 | #include "hw/irq.h" |
83c9f4ca | 23 | #include "hw/sysbus.h" |
47b43a1f | 24 | #include "gic_internal.h" |
da34e65c | 25 | #include "qapi/error.h" |
2e5b09fd | 26 | #include "hw/core/cpu.h" |
03dd024f | 27 | #include "qemu/log.h" |
0b8fa32f | 28 | #include "qemu/module.h" |
2531088f | 29 | #include "trace.h" |
5d721b78 | 30 | #include "sysemu/kvm.h" |
09bbdb89 | 31 | #include "sysemu/qtest.h" |
386e2955 | 32 | |
68bf93ce | 33 | /* #define DEBUG_GIC */ |
e69954b9 PB |
34 | |
35 | #ifdef DEBUG_GIC | |
68bf93ce | 36 | #define DEBUG_GIC_GATE 1 |
e69954b9 | 37 | #else |
68bf93ce | 38 | #define DEBUG_GIC_GATE 0 |
e69954b9 PB |
39 | #endif |
40 | ||
68bf93ce AB |
41 | #define DPRINTF(fmt, ...) do { \ |
42 | if (DEBUG_GIC_GATE) { \ | |
43 | fprintf(stderr, "%s: " fmt, __func__, ## __VA_ARGS__); \ | |
44 | } \ | |
45 | } while (0) | |
46 | ||
3355c360 AF |
47 | static const uint8_t gic_id_11mpcore[] = { |
48 | 0x00, 0x00, 0x00, 0x00, 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 | |
49 | }; | |
50 | ||
51 | static const uint8_t gic_id_gicv1[] = { | |
52 | 0x04, 0x00, 0x00, 0x00, 0x90, 0xb3, 0x1b, 0x00, 0x0d, 0xf0, 0x05, 0xb1 | |
53 | }; | |
54 | ||
55 | static const uint8_t gic_id_gicv2[] = { | |
56 | 0x04, 0x00, 0x00, 0x00, 0x90, 0xb4, 0x2b, 0x00, 0x0d, 0xf0, 0x05, 0xb1 | |
2a29ddee PM |
57 | }; |
58 | ||
fae15286 | 59 | static inline int gic_get_current_cpu(GICState *s) |
926c4aff | 60 | { |
09bbdb89 | 61 | if (!qtest_enabled() && s->num_cpu > 1) { |
4917cf44 | 62 | return current_cpu->cpu_index; |
926c4aff | 63 | } |
926c4aff PM |
64 | return 0; |
65 | } | |
66 | ||
4a37e0e4 LM |
67 | static inline int gic_get_current_vcpu(GICState *s) |
68 | { | |
69 | return gic_get_current_cpu(s) + GIC_NCPU; | |
70 | } | |
71 | ||
c27a5ba9 FA |
72 | /* Return true if this GIC config has interrupt groups, which is |
73 | * true if we're a GICv2, or a GICv1 with the security extensions. | |
74 | */ | |
75 | static inline bool gic_has_groups(GICState *s) | |
76 | { | |
77 | return s->revision == 2 || s->security_extn; | |
78 | } | |
79 | ||
3dd0471b LM |
80 | static inline bool gic_cpu_ns_access(GICState *s, int cpu, MemTxAttrs attrs) |
81 | { | |
82 | return !gic_is_vcpu(cpu) && s->security_extn && !attrs.secure; | |
83 | } | |
84 | ||
cbe1282b LM |
85 | static inline void gic_get_best_irq(GICState *s, int cpu, |
86 | int *best_irq, int *best_prio, int *group) | |
87 | { | |
88 | int irq; | |
89 | int cm = 1 << cpu; | |
90 | ||
91 | *best_irq = 1023; | |
92 | *best_prio = 0x100; | |
93 | ||
94 | for (irq = 0; irq < s->num_irq; irq++) { | |
95 | if (GIC_DIST_TEST_ENABLED(irq, cm) && gic_test_pending(s, irq, cm) && | |
96 | (!GIC_DIST_TEST_ACTIVE(irq, cm)) && | |
97 | (irq < GIC_INTERNAL || GIC_DIST_TARGET(irq) & cm)) { | |
98 | if (GIC_DIST_GET_PRIORITY(irq, cpu) < *best_prio) { | |
99 | *best_prio = GIC_DIST_GET_PRIORITY(irq, cpu); | |
100 | *best_irq = irq; | |
101 | } | |
102 | } | |
103 | } | |
104 | ||
105 | if (*best_irq < 1023) { | |
106 | *group = GIC_DIST_TEST_GROUP(*best_irq, cm); | |
107 | } | |
108 | } | |
109 | ||
110 | static inline void gic_get_best_virq(GICState *s, int cpu, | |
111 | int *best_irq, int *best_prio, int *group) | |
112 | { | |
113 | int lr_idx = 0; | |
114 | ||
115 | *best_irq = 1023; | |
116 | *best_prio = 0x100; | |
117 | ||
118 | for (lr_idx = 0; lr_idx < s->num_lrs; lr_idx++) { | |
119 | uint32_t lr_entry = s->h_lr[lr_idx][cpu]; | |
120 | int state = GICH_LR_STATE(lr_entry); | |
121 | ||
122 | if (state == GICH_LR_STATE_PENDING) { | |
123 | int prio = GICH_LR_PRIORITY(lr_entry); | |
124 | ||
125 | if (prio < *best_prio) { | |
126 | *best_prio = prio; | |
127 | *best_irq = GICH_LR_VIRT_ID(lr_entry); | |
128 | *group = GICH_LR_GROUP(lr_entry); | |
129 | } | |
130 | } | |
131 | } | |
132 | } | |
133 | ||
134 | /* Return true if IRQ signaling is enabled for the given cpu and at least one | |
135 | * of the given groups: | |
136 | * - in the non-virt case, the distributor must be enabled for one of the | |
137 | * given groups | |
138 | * - in the virt case, the virtual interface must be enabled. | |
139 | * - in all cases, the (v)CPU interface must be enabled for one of the given | |
140 | * groups. | |
141 | */ | |
142 | static inline bool gic_irq_signaling_enabled(GICState *s, int cpu, bool virt, | |
143 | int group_mask) | |
144 | { | |
4663b72a EI |
145 | int cpu_iface = virt ? (cpu + GIC_NCPU) : cpu; |
146 | ||
cbe1282b LM |
147 | if (!virt && !(s->ctlr & group_mask)) { |
148 | return false; | |
149 | } | |
150 | ||
151 | if (virt && !(s->h_hcr[cpu] & R_GICH_HCR_EN_MASK)) { | |
152 | return false; | |
153 | } | |
154 | ||
4663b72a | 155 | if (!(s->cpu_ctlr[cpu_iface] & group_mask)) { |
cbe1282b LM |
156 | return false; |
157 | } | |
158 | ||
159 | return true; | |
160 | } | |
161 | ||
e69954b9 PB |
162 | /* TODO: Many places that call this routine could be optimized. */ |
163 | /* Update interrupt status after enabled or pending bits have been changed. */ | |
cbe1282b | 164 | static inline void gic_update_internal(GICState *s, bool virt) |
e69954b9 PB |
165 | { |
166 | int best_irq; | |
167 | int best_prio; | |
dadbb58f | 168 | int irq_level, fiq_level; |
cbe1282b LM |
169 | int cpu, cpu_iface; |
170 | int group = 0; | |
171 | qemu_irq *irq_lines = virt ? s->parent_virq : s->parent_irq; | |
172 | qemu_irq *fiq_lines = virt ? s->parent_vfiq : s->parent_fiq; | |
9ee6e8bb | 173 | |
b95690c9 | 174 | for (cpu = 0; cpu < s->num_cpu; cpu++) { |
cbe1282b LM |
175 | cpu_iface = virt ? (cpu + GIC_NCPU) : cpu; |
176 | ||
177 | s->current_pending[cpu_iface] = 1023; | |
178 | if (!gic_irq_signaling_enabled(s, cpu, virt, | |
179 | GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1)) { | |
180 | qemu_irq_lower(irq_lines[cpu]); | |
181 | qemu_irq_lower(fiq_lines[cpu]); | |
235069a3 | 182 | continue; |
9ee6e8bb | 183 | } |
cbe1282b LM |
184 | |
185 | if (virt) { | |
186 | gic_get_best_virq(s, cpu, &best_irq, &best_prio, &group); | |
187 | } else { | |
188 | gic_get_best_irq(s, cpu, &best_irq, &best_prio, &group); | |
e69954b9 | 189 | } |
dadbb58f | 190 | |
2531088f | 191 | if (best_irq != 1023) { |
067a2b9c LM |
192 | trace_gic_update_bestirq(virt ? "vcpu" : "cpu", cpu, |
193 | best_irq, best_prio, | |
194 | s->priority_mask[cpu_iface], | |
195 | s->running_priority[cpu_iface]); | |
2531088f HB |
196 | } |
197 | ||
dadbb58f PM |
198 | irq_level = fiq_level = 0; |
199 | ||
cbe1282b LM |
200 | if (best_prio < s->priority_mask[cpu_iface]) { |
201 | s->current_pending[cpu_iface] = best_irq; | |
202 | if (best_prio < s->running_priority[cpu_iface]) { | |
203 | if (gic_irq_signaling_enabled(s, cpu, virt, 1 << group)) { | |
204 | if (group == 0 && | |
205 | s->cpu_ctlr[cpu_iface] & GICC_CTLR_FIQ_EN) { | |
dadbb58f | 206 | DPRINTF("Raised pending FIQ %d (cpu %d)\n", |
cbe1282b | 207 | best_irq, cpu_iface); |
dadbb58f | 208 | fiq_level = 1; |
cbe1282b LM |
209 | trace_gic_update_set_irq(cpu, virt ? "vfiq" : "fiq", |
210 | fiq_level); | |
dadbb58f PM |
211 | } else { |
212 | DPRINTF("Raised pending IRQ %d (cpu %d)\n", | |
cbe1282b | 213 | best_irq, cpu_iface); |
dadbb58f | 214 | irq_level = 1; |
cbe1282b LM |
215 | trace_gic_update_set_irq(cpu, virt ? "virq" : "irq", |
216 | irq_level); | |
dadbb58f PM |
217 | } |
218 | } | |
9ee6e8bb | 219 | } |
e69954b9 | 220 | } |
dadbb58f | 221 | |
cbe1282b LM |
222 | qemu_set_irq(irq_lines[cpu], irq_level); |
223 | qemu_set_irq(fiq_lines[cpu], fiq_level); | |
e69954b9 PB |
224 | } |
225 | } | |
226 | ||
cbe1282b LM |
227 | static void gic_update(GICState *s) |
228 | { | |
229 | gic_update_internal(s, false); | |
230 | } | |
231 | ||
527d296f LM |
232 | /* Return true if this LR is empty, i.e. the corresponding bit |
233 | * in ELRSR is set. | |
234 | */ | |
235 | static inline bool gic_lr_entry_is_free(uint32_t entry) | |
236 | { | |
237 | return (GICH_LR_STATE(entry) == GICH_LR_STATE_INVALID) | |
238 | && (GICH_LR_HW(entry) || !GICH_LR_EOI(entry)); | |
239 | } | |
240 | ||
241 | /* Return true if this LR should trigger an EOI maintenance interrupt, i.e. the | |
242 | * corrsponding bit in EISR is set. | |
243 | */ | |
244 | static inline bool gic_lr_entry_is_eoi(uint32_t entry) | |
245 | { | |
246 | return (GICH_LR_STATE(entry) == GICH_LR_STATE_INVALID) | |
247 | && !GICH_LR_HW(entry) && GICH_LR_EOI(entry); | |
248 | } | |
249 | ||
50e57926 LM |
250 | static inline void gic_extract_lr_info(GICState *s, int cpu, |
251 | int *num_eoi, int *num_valid, int *num_pending) | |
252 | { | |
253 | int lr_idx; | |
254 | ||
255 | *num_eoi = 0; | |
256 | *num_valid = 0; | |
257 | *num_pending = 0; | |
258 | ||
259 | for (lr_idx = 0; lr_idx < s->num_lrs; lr_idx++) { | |
260 | uint32_t *entry = &s->h_lr[lr_idx][cpu]; | |
261 | ||
262 | if (gic_lr_entry_is_eoi(*entry)) { | |
263 | (*num_eoi)++; | |
264 | } | |
265 | ||
266 | if (GICH_LR_STATE(*entry) != GICH_LR_STATE_INVALID) { | |
267 | (*num_valid)++; | |
268 | } | |
269 | ||
270 | if (GICH_LR_STATE(*entry) == GICH_LR_STATE_PENDING) { | |
271 | (*num_pending)++; | |
272 | } | |
273 | } | |
274 | } | |
275 | ||
276 | static void gic_compute_misr(GICState *s, int cpu) | |
277 | { | |
278 | uint32_t value = 0; | |
279 | int vcpu = cpu + GIC_NCPU; | |
280 | ||
281 | int num_eoi, num_valid, num_pending; | |
282 | ||
283 | gic_extract_lr_info(s, cpu, &num_eoi, &num_valid, &num_pending); | |
284 | ||
285 | /* EOI */ | |
286 | if (num_eoi) { | |
287 | value |= R_GICH_MISR_EOI_MASK; | |
288 | } | |
289 | ||
290 | /* U: true if only 0 or 1 LR entry is valid */ | |
291 | if ((s->h_hcr[cpu] & R_GICH_HCR_UIE_MASK) && (num_valid < 2)) { | |
292 | value |= R_GICH_MISR_U_MASK; | |
293 | } | |
294 | ||
295 | /* LRENP: EOICount is not 0 */ | |
296 | if ((s->h_hcr[cpu] & R_GICH_HCR_LRENPIE_MASK) && | |
297 | ((s->h_hcr[cpu] & R_GICH_HCR_EOICount_MASK) != 0)) { | |
298 | value |= R_GICH_MISR_LRENP_MASK; | |
299 | } | |
300 | ||
301 | /* NP: no pending interrupts */ | |
302 | if ((s->h_hcr[cpu] & R_GICH_HCR_NPIE_MASK) && (num_pending == 0)) { | |
303 | value |= R_GICH_MISR_NP_MASK; | |
304 | } | |
305 | ||
306 | /* VGrp0E: group0 virq signaling enabled */ | |
307 | if ((s->h_hcr[cpu] & R_GICH_HCR_VGRP0EIE_MASK) && | |
308 | (s->cpu_ctlr[vcpu] & GICC_CTLR_EN_GRP0)) { | |
309 | value |= R_GICH_MISR_VGrp0E_MASK; | |
310 | } | |
311 | ||
312 | /* VGrp0D: group0 virq signaling disabled */ | |
313 | if ((s->h_hcr[cpu] & R_GICH_HCR_VGRP0DIE_MASK) && | |
314 | !(s->cpu_ctlr[vcpu] & GICC_CTLR_EN_GRP0)) { | |
315 | value |= R_GICH_MISR_VGrp0D_MASK; | |
316 | } | |
317 | ||
318 | /* VGrp1E: group1 virq signaling enabled */ | |
319 | if ((s->h_hcr[cpu] & R_GICH_HCR_VGRP1EIE_MASK) && | |
320 | (s->cpu_ctlr[vcpu] & GICC_CTLR_EN_GRP1)) { | |
321 | value |= R_GICH_MISR_VGrp1E_MASK; | |
322 | } | |
323 | ||
324 | /* VGrp1D: group1 virq signaling disabled */ | |
325 | if ((s->h_hcr[cpu] & R_GICH_HCR_VGRP1DIE_MASK) && | |
326 | !(s->cpu_ctlr[vcpu] & GICC_CTLR_EN_GRP1)) { | |
327 | value |= R_GICH_MISR_VGrp1D_MASK; | |
328 | } | |
329 | ||
330 | s->h_misr[cpu] = value; | |
331 | } | |
332 | ||
333 | static void gic_update_maintenance(GICState *s) | |
334 | { | |
335 | int cpu = 0; | |
336 | int maint_level; | |
337 | ||
338 | for (cpu = 0; cpu < s->num_cpu; cpu++) { | |
339 | gic_compute_misr(s, cpu); | |
340 | maint_level = (s->h_hcr[cpu] & R_GICH_HCR_EN_MASK) && s->h_misr[cpu]; | |
341 | ||
067a2b9c | 342 | trace_gic_update_maintenance_irq(cpu, maint_level); |
50e57926 LM |
343 | qemu_set_irq(s->maintenance_irq[cpu], maint_level); |
344 | } | |
345 | } | |
346 | ||
cbe1282b LM |
347 | static void gic_update_virt(GICState *s) |
348 | { | |
349 | gic_update_internal(s, true); | |
50e57926 | 350 | gic_update_maintenance(s); |
cbe1282b LM |
351 | } |
352 | ||
8d999995 CD |
353 | static void gic_set_irq_11mpcore(GICState *s, int irq, int level, |
354 | int cm, int target) | |
355 | { | |
356 | if (level) { | |
67ce697a LM |
357 | GIC_DIST_SET_LEVEL(irq, cm); |
358 | if (GIC_DIST_TEST_EDGE_TRIGGER(irq) || GIC_DIST_TEST_ENABLED(irq, cm)) { | |
8d999995 | 359 | DPRINTF("Set %d pending mask %x\n", irq, target); |
67ce697a | 360 | GIC_DIST_SET_PENDING(irq, target); |
8d999995 CD |
361 | } |
362 | } else { | |
67ce697a | 363 | GIC_DIST_CLEAR_LEVEL(irq, cm); |
8d999995 CD |
364 | } |
365 | } | |
366 | ||
367 | static void gic_set_irq_generic(GICState *s, int irq, int level, | |
368 | int cm, int target) | |
369 | { | |
370 | if (level) { | |
67ce697a | 371 | GIC_DIST_SET_LEVEL(irq, cm); |
8d999995 | 372 | DPRINTF("Set %d pending mask %x\n", irq, target); |
67ce697a LM |
373 | if (GIC_DIST_TEST_EDGE_TRIGGER(irq)) { |
374 | GIC_DIST_SET_PENDING(irq, target); | |
8d999995 CD |
375 | } |
376 | } else { | |
67ce697a | 377 | GIC_DIST_CLEAR_LEVEL(irq, cm); |
8d999995 CD |
378 | } |
379 | } | |
380 | ||
9ee6e8bb | 381 | /* Process a change in an external IRQ input. */ |
e69954b9 PB |
382 | static void gic_set_irq(void *opaque, int irq, int level) |
383 | { | |
544d1afa PM |
384 | /* Meaning of the 'irq' parameter: |
385 | * [0..N-1] : external interrupts | |
386 | * [N..N+31] : PPI (internal) interrupts for CPU 0 | |
387 | * [N+32..N+63] : PPI (internal interrupts for CPU 1 | |
388 | * ... | |
389 | */ | |
fae15286 | 390 | GICState *s = (GICState *)opaque; |
544d1afa PM |
391 | int cm, target; |
392 | if (irq < (s->num_irq - GIC_INTERNAL)) { | |
393 | /* The first external input line is internal interrupt 32. */ | |
394 | cm = ALL_CPU_MASK; | |
395 | irq += GIC_INTERNAL; | |
67ce697a | 396 | target = GIC_DIST_TARGET(irq); |
544d1afa PM |
397 | } else { |
398 | int cpu; | |
399 | irq -= (s->num_irq - GIC_INTERNAL); | |
400 | cpu = irq / GIC_INTERNAL; | |
401 | irq %= GIC_INTERNAL; | |
402 | cm = 1 << cpu; | |
403 | target = cm; | |
404 | } | |
405 | ||
40d22500 CD |
406 | assert(irq >= GIC_NR_SGIS); |
407 | ||
67ce697a | 408 | if (level == GIC_DIST_TEST_LEVEL(irq, cm)) { |
e69954b9 | 409 | return; |
544d1afa | 410 | } |
e69954b9 | 411 | |
3bc4b52c | 412 | if (s->revision == REV_11MPCORE) { |
8d999995 | 413 | gic_set_irq_11mpcore(s, irq, level, cm, target); |
e69954b9 | 414 | } else { |
8d999995 | 415 | gic_set_irq_generic(s, irq, level, cm, target); |
e69954b9 | 416 | } |
2531088f | 417 | trace_gic_set_irq(irq, level, cm, target); |
8d999995 | 418 | |
e69954b9 PB |
419 | gic_update(s); |
420 | } | |
421 | ||
7c0fa108 FA |
422 | static uint16_t gic_get_current_pending_irq(GICState *s, int cpu, |
423 | MemTxAttrs attrs) | |
424 | { | |
425 | uint16_t pending_irq = s->current_pending[cpu]; | |
426 | ||
427 | if (pending_irq < GIC_MAXIRQ && gic_has_groups(s)) { | |
86b350f0 LM |
428 | int group = gic_test_group(s, pending_irq, cpu); |
429 | ||
7c0fa108 FA |
430 | /* On a GIC without the security extensions, reading this register |
431 | * behaves in the same way as a secure access to a GIC with them. | |
432 | */ | |
3dd0471b | 433 | bool secure = !gic_cpu_ns_access(s, cpu, attrs); |
7c0fa108 FA |
434 | |
435 | if (group == 0 && !secure) { | |
436 | /* Group0 interrupts hidden from Non-secure access */ | |
437 | return 1023; | |
438 | } | |
439 | if (group == 1 && secure && !(s->cpu_ctlr[cpu] & GICC_CTLR_ACK_CTL)) { | |
440 | /* Group1 interrupts only seen by Secure access if | |
441 | * AckCtl bit set. | |
442 | */ | |
443 | return 1022; | |
444 | } | |
445 | } | |
446 | return pending_irq; | |
447 | } | |
448 | ||
df92cfa6 PM |
449 | static int gic_get_group_priority(GICState *s, int cpu, int irq) |
450 | { | |
451 | /* Return the group priority of the specified interrupt | |
452 | * (which is the top bits of its priority, with the number | |
453 | * of bits masked determined by the applicable binary point register). | |
454 | */ | |
455 | int bpr; | |
456 | uint32_t mask; | |
457 | ||
458 | if (gic_has_groups(s) && | |
459 | !(s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) && | |
86b350f0 | 460 | gic_test_group(s, irq, cpu)) { |
fc05a6f2 LM |
461 | bpr = s->abpr[cpu] - 1; |
462 | assert(bpr >= 0); | |
df92cfa6 PM |
463 | } else { |
464 | bpr = s->bpr[cpu]; | |
465 | } | |
466 | ||
467 | /* a BPR of 0 means the group priority bits are [7:1]; | |
468 | * a BPR of 1 means they are [7:2], and so on down to | |
469 | * a BPR of 7 meaning no group priority bits at all. | |
470 | */ | |
471 | mask = ~0U << ((bpr & 7) + 1); | |
472 | ||
86b350f0 | 473 | return gic_get_priority(s, irq, cpu) & mask; |
df92cfa6 PM |
474 | } |
475 | ||
72889c8a | 476 | static void gic_activate_irq(GICState *s, int cpu, int irq) |
e69954b9 | 477 | { |
72889c8a PM |
478 | /* Set the appropriate Active Priority Register bit for this IRQ, |
479 | * and update the running priority. | |
480 | */ | |
481 | int prio = gic_get_group_priority(s, cpu, irq); | |
a1d7b8d8 LM |
482 | int min_bpr = gic_is_vcpu(cpu) ? GIC_VIRT_MIN_BPR : GIC_MIN_BPR; |
483 | int preemption_level = prio >> (min_bpr + 1); | |
72889c8a PM |
484 | int regno = preemption_level / 32; |
485 | int bitno = preemption_level % 32; | |
a1d7b8d8 | 486 | uint32_t *papr = NULL; |
72889c8a | 487 | |
a1d7b8d8 LM |
488 | if (gic_is_vcpu(cpu)) { |
489 | assert(regno == 0); | |
490 | papr = &s->h_apr[gic_get_vcpu_real_id(cpu)]; | |
491 | } else if (gic_has_groups(s) && gic_test_group(s, irq, cpu)) { | |
492 | papr = &s->nsapr[regno][cpu]; | |
9ee6e8bb | 493 | } else { |
a1d7b8d8 | 494 | papr = &s->apr[regno][cpu]; |
9ee6e8bb | 495 | } |
72889c8a | 496 | |
a1d7b8d8 LM |
497 | *papr |= (1 << bitno); |
498 | ||
72889c8a | 499 | s->running_priority[cpu] = prio; |
86b350f0 | 500 | gic_set_active(s, irq, cpu); |
72889c8a PM |
501 | } |
502 | ||
503 | static int gic_get_prio_from_apr_bits(GICState *s, int cpu) | |
504 | { | |
505 | /* Recalculate the current running priority for this CPU based | |
506 | * on the set bits in the Active Priority Registers. | |
507 | */ | |
508 | int i; | |
a1d7b8d8 LM |
509 | |
510 | if (gic_is_vcpu(cpu)) { | |
511 | uint32_t apr = s->h_apr[gic_get_vcpu_real_id(cpu)]; | |
512 | if (apr) { | |
513 | return ctz32(apr) << (GIC_VIRT_MIN_BPR + 1); | |
514 | } else { | |
515 | return 0x100; | |
516 | } | |
517 | } | |
518 | ||
72889c8a PM |
519 | for (i = 0; i < GIC_NR_APRS; i++) { |
520 | uint32_t apr = s->apr[i][cpu] | s->nsapr[i][cpu]; | |
521 | if (!apr) { | |
522 | continue; | |
523 | } | |
524 | return (i * 32 + ctz32(apr)) << (GIC_MIN_BPR + 1); | |
525 | } | |
526 | return 0x100; | |
527 | } | |
528 | ||
529 | static void gic_drop_prio(GICState *s, int cpu, int group) | |
530 | { | |
531 | /* Drop the priority of the currently active interrupt in the | |
532 | * specified group. | |
533 | * | |
534 | * Note that we can guarantee (because of the requirement to nest | |
535 | * GICC_IAR reads [which activate an interrupt and raise priority] | |
536 | * with GICC_EOIR writes [which drop the priority for the interrupt]) | |
537 | * that the interrupt we're being called for is the highest priority | |
538 | * active interrupt, meaning that it has the lowest set bit in the | |
539 | * APR registers. | |
540 | * | |
541 | * If the guest does not honour the ordering constraints then the | |
542 | * behaviour of the GIC is UNPREDICTABLE, which for us means that | |
543 | * the values of the APR registers might become incorrect and the | |
544 | * running priority will be wrong, so interrupts that should preempt | |
545 | * might not do so, and interrupts that should not preempt might do so. | |
546 | */ | |
a1d7b8d8 LM |
547 | if (gic_is_vcpu(cpu)) { |
548 | int rcpu = gic_get_vcpu_real_id(cpu); | |
72889c8a | 549 | |
a1d7b8d8 LM |
550 | if (s->h_apr[rcpu]) { |
551 | /* Clear lowest set bit */ | |
552 | s->h_apr[rcpu] &= s->h_apr[rcpu] - 1; | |
553 | } | |
554 | } else { | |
555 | int i; | |
556 | ||
557 | for (i = 0; i < GIC_NR_APRS; i++) { | |
558 | uint32_t *papr = group ? &s->nsapr[i][cpu] : &s->apr[i][cpu]; | |
559 | if (!*papr) { | |
560 | continue; | |
561 | } | |
562 | /* Clear lowest set bit */ | |
563 | *papr &= *papr - 1; | |
564 | break; | |
72889c8a | 565 | } |
72889c8a PM |
566 | } |
567 | ||
568 | s->running_priority[cpu] = gic_get_prio_from_apr_bits(s, cpu); | |
e69954b9 PB |
569 | } |
570 | ||
439badd6 LM |
571 | static inline uint32_t gic_clear_pending_sgi(GICState *s, int irq, int cpu) |
572 | { | |
573 | int src; | |
574 | uint32_t ret; | |
575 | ||
576 | if (!gic_is_vcpu(cpu)) { | |
577 | /* Lookup the source CPU for the SGI and clear this in the | |
578 | * sgi_pending map. Return the src and clear the overall pending | |
579 | * state on this CPU if the SGI is not pending from any CPUs. | |
580 | */ | |
581 | assert(s->sgi_pending[irq][cpu] != 0); | |
582 | src = ctz32(s->sgi_pending[irq][cpu]); | |
583 | s->sgi_pending[irq][cpu] &= ~(1 << src); | |
584 | if (s->sgi_pending[irq][cpu] == 0) { | |
585 | gic_clear_pending(s, irq, cpu); | |
586 | } | |
587 | ret = irq | ((src & 0x7) << 10); | |
588 | } else { | |
589 | uint32_t *lr_entry = gic_get_lr_entry(s, irq, cpu); | |
590 | src = GICH_LR_CPUID(*lr_entry); | |
591 | ||
592 | gic_clear_pending(s, irq, cpu); | |
593 | ret = irq | (src << 10); | |
594 | } | |
595 | ||
596 | return ret; | |
597 | } | |
598 | ||
c5619bf9 | 599 | uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs) |
e69954b9 | 600 | { |
439badd6 | 601 | int ret, irq; |
c5619bf9 FA |
602 | |
603 | /* gic_get_current_pending_irq() will return 1022 or 1023 appropriately | |
604 | * for the case where this GIC supports grouping and the pending interrupt | |
605 | * is in the wrong group. | |
606 | */ | |
a8f15a27 | 607 | irq = gic_get_current_pending_irq(s, cpu, attrs); |
067a2b9c LM |
608 | trace_gic_acknowledge_irq(gic_is_vcpu(cpu) ? "vcpu" : "cpu", |
609 | gic_get_vcpu_real_id(cpu), irq); | |
c5619bf9 FA |
610 | |
611 | if (irq >= GIC_MAXIRQ) { | |
612 | DPRINTF("ACK, no pending interrupt or it is hidden: %d\n", irq); | |
613 | return irq; | |
614 | } | |
615 | ||
86b350f0 | 616 | if (gic_get_priority(s, irq, cpu) >= s->running_priority[cpu]) { |
c5619bf9 | 617 | DPRINTF("ACK, pending interrupt (%d) has insufficient priority\n", irq); |
e69954b9 PB |
618 | return 1023; |
619 | } | |
40d22500 | 620 | |
439badd6 LM |
621 | gic_activate_irq(s, cpu, irq); |
622 | ||
7c14b3ac | 623 | if (s->revision == REV_11MPCORE) { |
40d22500 CD |
624 | /* Clear pending flags for both level and edge triggered interrupts. |
625 | * Level triggered IRQs will be reasserted once they become inactive. | |
626 | */ | |
86b350f0 | 627 | gic_clear_pending(s, irq, cpu); |
40d22500 CD |
628 | ret = irq; |
629 | } else { | |
630 | if (irq < GIC_NR_SGIS) { | |
439badd6 | 631 | ret = gic_clear_pending_sgi(s, irq, cpu); |
40d22500 | 632 | } else { |
86b350f0 | 633 | gic_clear_pending(s, irq, cpu); |
40d22500 CD |
634 | ret = irq; |
635 | } | |
636 | } | |
637 | ||
cbe1282b LM |
638 | if (gic_is_vcpu(cpu)) { |
639 | gic_update_virt(s); | |
640 | } else { | |
641 | gic_update(s); | |
642 | } | |
40d22500 CD |
643 | DPRINTF("ACK %d\n", irq); |
644 | return ret; | |
e69954b9 PB |
645 | } |
646 | ||
11411489 SPB |
647 | static uint32_t gic_fullprio_mask(GICState *s, int cpu) |
648 | { | |
649 | /* | |
650 | * Return a mask word which clears the unimplemented priority | |
651 | * bits from a priority value for an interrupt. (Not to be | |
652 | * confused with the group priority, whose mask depends on BPR.) | |
653 | */ | |
654 | int priBits; | |
655 | ||
656 | if (gic_is_vcpu(cpu)) { | |
657 | priBits = GIC_VIRT_MAX_GROUP_PRIO_BITS; | |
658 | } else { | |
659 | priBits = s->n_prio_bits; | |
660 | } | |
661 | return ~0U << (8 - priBits); | |
662 | } | |
663 | ||
67ce697a | 664 | void gic_dist_set_priority(GICState *s, int cpu, int irq, uint8_t val, |
81508470 | 665 | MemTxAttrs attrs) |
9df90ad0 | 666 | { |
81508470 | 667 | if (s->security_extn && !attrs.secure) { |
67ce697a | 668 | if (!GIC_DIST_TEST_GROUP(irq, (1 << cpu))) { |
81508470 FA |
669 | return; /* Ignore Non-secure access of Group0 IRQ */ |
670 | } | |
671 | val = 0x80 | (val >> 1); /* Non-secure view */ | |
672 | } | |
673 | ||
11411489 SPB |
674 | val &= gic_fullprio_mask(s, cpu); |
675 | ||
9df90ad0 CD |
676 | if (irq < GIC_INTERNAL) { |
677 | s->priority1[irq][cpu] = val; | |
678 | } else { | |
679 | s->priority2[(irq) - GIC_INTERNAL] = val; | |
680 | } | |
681 | } | |
682 | ||
67ce697a | 683 | static uint32_t gic_dist_get_priority(GICState *s, int cpu, int irq, |
81508470 FA |
684 | MemTxAttrs attrs) |
685 | { | |
67ce697a | 686 | uint32_t prio = GIC_DIST_GET_PRIORITY(irq, cpu); |
81508470 FA |
687 | |
688 | if (s->security_extn && !attrs.secure) { | |
67ce697a | 689 | if (!GIC_DIST_TEST_GROUP(irq, (1 << cpu))) { |
81508470 FA |
690 | return 0; /* Non-secure access cannot read priority of Group0 IRQ */ |
691 | } | |
692 | prio = (prio << 1) & 0xff; /* Non-secure view */ | |
693 | } | |
11411489 | 694 | return prio & gic_fullprio_mask(s, cpu); |
81508470 FA |
695 | } |
696 | ||
697 | static void gic_set_priority_mask(GICState *s, int cpu, uint8_t pmask, | |
698 | MemTxAttrs attrs) | |
699 | { | |
3dd0471b | 700 | if (gic_cpu_ns_access(s, cpu, attrs)) { |
81508470 FA |
701 | if (s->priority_mask[cpu] & 0x80) { |
702 | /* Priority Mask in upper half */ | |
703 | pmask = 0x80 | (pmask >> 1); | |
704 | } else { | |
705 | /* Non-secure write ignored if priority mask is in lower half */ | |
706 | return; | |
707 | } | |
708 | } | |
11411489 | 709 | s->priority_mask[cpu] = pmask & gic_fullprio_mask(s, cpu); |
81508470 FA |
710 | } |
711 | ||
712 | static uint32_t gic_get_priority_mask(GICState *s, int cpu, MemTxAttrs attrs) | |
713 | { | |
714 | uint32_t pmask = s->priority_mask[cpu]; | |
715 | ||
3dd0471b | 716 | if (gic_cpu_ns_access(s, cpu, attrs)) { |
81508470 FA |
717 | if (pmask & 0x80) { |
718 | /* Priority Mask in upper half, return Non-secure view */ | |
719 | pmask = (pmask << 1) & 0xff; | |
720 | } else { | |
721 | /* Priority Mask in lower half, RAZ */ | |
722 | pmask = 0; | |
723 | } | |
724 | } | |
725 | return pmask; | |
726 | } | |
727 | ||
32951860 FA |
728 | static uint32_t gic_get_cpu_control(GICState *s, int cpu, MemTxAttrs attrs) |
729 | { | |
730 | uint32_t ret = s->cpu_ctlr[cpu]; | |
731 | ||
3dd0471b | 732 | if (gic_cpu_ns_access(s, cpu, attrs)) { |
32951860 FA |
733 | /* Construct the NS banked view of GICC_CTLR from the correct |
734 | * bits of the S banked view. We don't need to move the bypass | |
735 | * control bits because we don't implement that (IMPDEF) part | |
736 | * of the GIC architecture. | |
737 | */ | |
738 | ret = (ret & (GICC_CTLR_EN_GRP1 | GICC_CTLR_EOIMODE_NS)) >> 1; | |
739 | } | |
740 | return ret; | |
741 | } | |
742 | ||
743 | static void gic_set_cpu_control(GICState *s, int cpu, uint32_t value, | |
744 | MemTxAttrs attrs) | |
745 | { | |
746 | uint32_t mask; | |
747 | ||
3dd0471b | 748 | if (gic_cpu_ns_access(s, cpu, attrs)) { |
32951860 FA |
749 | /* The NS view can only write certain bits in the register; |
750 | * the rest are unchanged | |
751 | */ | |
752 | mask = GICC_CTLR_EN_GRP1; | |
753 | if (s->revision == 2) { | |
754 | mask |= GICC_CTLR_EOIMODE_NS; | |
755 | } | |
756 | s->cpu_ctlr[cpu] &= ~mask; | |
757 | s->cpu_ctlr[cpu] |= (value << 1) & mask; | |
758 | } else { | |
759 | if (s->revision == 2) { | |
760 | mask = s->security_extn ? GICC_CTLR_V2_S_MASK : GICC_CTLR_V2_MASK; | |
761 | } else { | |
762 | mask = s->security_extn ? GICC_CTLR_V1_S_MASK : GICC_CTLR_V1_MASK; | |
763 | } | |
764 | s->cpu_ctlr[cpu] = value & mask; | |
765 | } | |
766 | DPRINTF("CPU Interface %d: Group0 Interrupts %sabled, " | |
767 | "Group1 Interrupts %sabled\n", cpu, | |
768 | (s->cpu_ctlr[cpu] & GICC_CTLR_EN_GRP0) ? "En" : "Dis", | |
769 | (s->cpu_ctlr[cpu] & GICC_CTLR_EN_GRP1) ? "En" : "Dis"); | |
770 | } | |
771 | ||
08efa9f2 FA |
772 | static uint8_t gic_get_running_priority(GICState *s, int cpu, MemTxAttrs attrs) |
773 | { | |
71aa735b LM |
774 | if ((s->revision != REV_11MPCORE) && (s->running_priority[cpu] > 0xff)) { |
775 | /* Idle priority */ | |
776 | return 0xff; | |
777 | } | |
778 | ||
3dd0471b | 779 | if (gic_cpu_ns_access(s, cpu, attrs)) { |
08efa9f2 FA |
780 | if (s->running_priority[cpu] & 0x80) { |
781 | /* Running priority in upper half of range: return the Non-secure | |
782 | * view of the priority. | |
783 | */ | |
784 | return s->running_priority[cpu] << 1; | |
785 | } else { | |
786 | /* Running priority in lower half of range: RAZ */ | |
787 | return 0; | |
788 | } | |
789 | } else { | |
790 | return s->running_priority[cpu]; | |
791 | } | |
792 | } | |
793 | ||
a55c910e PM |
794 | /* Return true if we should split priority drop and interrupt deactivation, |
795 | * ie whether the relevant EOIMode bit is set. | |
796 | */ | |
797 | static bool gic_eoi_split(GICState *s, int cpu, MemTxAttrs attrs) | |
798 | { | |
799 | if (s->revision != 2) { | |
800 | /* Before GICv2 prio-drop and deactivate are not separable */ | |
801 | return false; | |
802 | } | |
3dd0471b | 803 | if (gic_cpu_ns_access(s, cpu, attrs)) { |
a55c910e PM |
804 | return s->cpu_ctlr[cpu] & GICC_CTLR_EOIMODE_NS; |
805 | } | |
806 | return s->cpu_ctlr[cpu] & GICC_CTLR_EOIMODE; | |
807 | } | |
808 | ||
809 | static void gic_deactivate_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs) | |
810 | { | |
ee03cca8 PM |
811 | int group; |
812 | ||
02f2e22d | 813 | if (irq >= GIC_MAXIRQ || (!gic_is_vcpu(cpu) && irq >= s->num_irq)) { |
ee03cca8 PM |
814 | /* |
815 | * This handles two cases: | |
816 | * 1. If software writes the ID of a spurious interrupt [ie 1023] | |
817 | * to the GICC_DIR, the GIC ignores that write. | |
818 | * 2. If software writes the number of a non-existent interrupt | |
819 | * this must be a subcase of "value written is not an active interrupt" | |
02f2e22d LM |
820 | * and so this is UNPREDICTABLE. We choose to ignore it. For vCPUs, |
821 | * all IRQs potentially exist, so this limit does not apply. | |
ee03cca8 PM |
822 | */ |
823 | return; | |
824 | } | |
825 | ||
a55c910e PM |
826 | if (!gic_eoi_split(s, cpu, attrs)) { |
827 | /* This is UNPREDICTABLE; we choose to ignore it */ | |
828 | qemu_log_mask(LOG_GUEST_ERROR, | |
829 | "gic_deactivate_irq: GICC_DIR write when EOIMode clear"); | |
830 | return; | |
831 | } | |
832 | ||
02f2e22d LM |
833 | if (gic_is_vcpu(cpu) && !gic_virq_is_valid(s, irq, cpu)) { |
834 | /* This vIRQ does not have an LR entry which is either active or | |
835 | * pending and active. Increment EOICount and ignore the write. | |
836 | */ | |
837 | int rcpu = gic_get_vcpu_real_id(cpu); | |
838 | s->h_hcr[rcpu] += 1 << R_GICH_HCR_EOICount_SHIFT; | |
cbe1282b LM |
839 | |
840 | /* Update the virtual interface in case a maintenance interrupt should | |
841 | * be raised. | |
842 | */ | |
843 | gic_update_virt(s); | |
02f2e22d LM |
844 | return; |
845 | } | |
846 | ||
847 | group = gic_has_groups(s) && gic_test_group(s, irq, cpu); | |
848 | ||
3dd0471b | 849 | if (gic_cpu_ns_access(s, cpu, attrs) && !group) { |
a55c910e PM |
850 | DPRINTF("Non-secure DI for Group0 interrupt %d ignored\n", irq); |
851 | return; | |
852 | } | |
853 | ||
86b350f0 | 854 | gic_clear_active(s, irq, cpu); |
a55c910e PM |
855 | } |
856 | ||
50491c56 | 857 | static void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs) |
e69954b9 | 858 | { |
9ee6e8bb | 859 | int cm = 1 << cpu; |
72889c8a PM |
860 | int group; |
861 | ||
df628ff1 | 862 | DPRINTF("EOI %d\n", irq); |
02f2e22d LM |
863 | if (gic_is_vcpu(cpu)) { |
864 | /* The call to gic_prio_drop() will clear a bit in GICH_APR iff the | |
865 | * running prio is < 0x100. | |
866 | */ | |
867 | bool prio_drop = s->running_priority[cpu] < 0x100; | |
868 | ||
869 | if (irq >= GIC_MAXIRQ) { | |
870 | /* Ignore spurious interrupt */ | |
871 | return; | |
872 | } | |
873 | ||
874 | gic_drop_prio(s, cpu, 0); | |
875 | ||
876 | if (!gic_eoi_split(s, cpu, attrs)) { | |
877 | bool valid = gic_virq_is_valid(s, irq, cpu); | |
878 | if (prio_drop && !valid) { | |
879 | /* We are in a situation where: | |
880 | * - V_CTRL.EOIMode is false (no EOI split), | |
881 | * - The call to gic_drop_prio() cleared a bit in GICH_APR, | |
882 | * - This vIRQ does not have an LR entry which is either | |
883 | * active or pending and active. | |
884 | * In that case, we must increment EOICount. | |
885 | */ | |
886 | int rcpu = gic_get_vcpu_real_id(cpu); | |
887 | s->h_hcr[rcpu] += 1 << R_GICH_HCR_EOICount_SHIFT; | |
888 | } else if (valid) { | |
889 | gic_clear_active(s, irq, cpu); | |
890 | } | |
891 | } | |
892 | ||
cbe1282b | 893 | gic_update_virt(s); |
02f2e22d LM |
894 | return; |
895 | } | |
896 | ||
a32134aa | 897 | if (irq >= s->num_irq) { |
217bfb44 PM |
898 | /* This handles two cases: |
899 | * 1. If software writes the ID of a spurious interrupt [ie 1023] | |
900 | * to the GICC_EOIR, the GIC ignores that write. | |
901 | * 2. If software writes the number of a non-existent interrupt | |
902 | * this must be a subcase of "value written does not match the last | |
903 | * valid interrupt value read from the Interrupt Acknowledge | |
904 | * register" and so this is UNPREDICTABLE. We choose to ignore it. | |
905 | */ | |
906 | return; | |
907 | } | |
72889c8a | 908 | if (s->running_priority[cpu] == 0x100) { |
e69954b9 | 909 | return; /* No active IRQ. */ |
72889c8a | 910 | } |
8d999995 | 911 | |
3bc4b52c | 912 | if (s->revision == REV_11MPCORE) { |
8d999995 CD |
913 | /* Mark level triggered interrupts as pending if they are still |
914 | raised. */ | |
67ce697a LM |
915 | if (!GIC_DIST_TEST_EDGE_TRIGGER(irq) && GIC_DIST_TEST_ENABLED(irq, cm) |
916 | && GIC_DIST_TEST_LEVEL(irq, cm) | |
917 | && (GIC_DIST_TARGET(irq) & cm) != 0) { | |
8d999995 | 918 | DPRINTF("Set %d pending mask %x\n", irq, cm); |
67ce697a | 919 | GIC_DIST_SET_PENDING(irq, cm); |
8d999995 | 920 | } |
e69954b9 | 921 | } |
8d999995 | 922 | |
86b350f0 | 923 | group = gic_has_groups(s) && gic_test_group(s, irq, cpu); |
72889c8a | 924 | |
3dd0471b | 925 | if (gic_cpu_ns_access(s, cpu, attrs) && !group) { |
f9c6a7f1 FA |
926 | DPRINTF("Non-secure EOI for Group0 interrupt %d ignored\n", irq); |
927 | return; | |
928 | } | |
929 | ||
930 | /* Secure EOI with GICC_CTLR.AckCtl == 0 when the IRQ is a Group 1 | |
931 | * interrupt is UNPREDICTABLE. We choose to handle it as if AckCtl == 1, | |
932 | * i.e. go ahead and complete the irq anyway. | |
933 | */ | |
934 | ||
72889c8a | 935 | gic_drop_prio(s, cpu, group); |
a55c910e PM |
936 | |
937 | /* In GICv2 the guest can choose to split priority-drop and deactivate */ | |
938 | if (!gic_eoi_split(s, cpu, attrs)) { | |
86b350f0 | 939 | gic_clear_active(s, irq, cpu); |
a55c910e | 940 | } |
72889c8a | 941 | gic_update(s); |
e69954b9 PB |
942 | } |
943 | ||
a9d85353 | 944 | static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs) |
e69954b9 | 945 | { |
fae15286 | 946 | GICState *s = (GICState *)opaque; |
e69954b9 PB |
947 | uint32_t res; |
948 | int irq; | |
949 | int i; | |
9ee6e8bb PB |
950 | int cpu; |
951 | int cm; | |
952 | int mask; | |
e69954b9 | 953 | |
926c4aff | 954 | cpu = gic_get_current_cpu(s); |
9ee6e8bb | 955 | cm = 1 << cpu; |
e69954b9 | 956 | if (offset < 0x100) { |
679aa175 FA |
957 | if (offset == 0) { /* GICD_CTLR */ |
958 | if (s->security_extn && !attrs.secure) { | |
959 | /* The NS bank of this register is just an alias of the | |
960 | * EnableGrp1 bit in the S bank version. | |
961 | */ | |
962 | return extract32(s->ctlr, 1, 1); | |
963 | } else { | |
964 | return s->ctlr; | |
965 | } | |
966 | } | |
e69954b9 | 967 | if (offset == 4) |
5543d1ab FA |
968 | /* Interrupt Controller Type Register */ |
969 | return ((s->num_irq / 32) - 1) | |
b95690c9 | 970 | | ((s->num_cpu - 1) << 5) |
5543d1ab | 971 | | (s->security_extn << 10); |
e69954b9 PB |
972 | if (offset < 0x08) |
973 | return 0; | |
b79f2265 | 974 | if (offset >= 0x80) { |
c27a5ba9 FA |
975 | /* Interrupt Group Registers: these RAZ/WI if this is an NS |
976 | * access to a GIC with the security extensions, or if the GIC | |
977 | * doesn't have groups at all. | |
978 | */ | |
979 | res = 0; | |
980 | if (!(s->security_extn && !attrs.secure) && gic_has_groups(s)) { | |
981 | /* Every byte offset holds 8 group status bits */ | |
b6e6c651 | 982 | irq = (offset - 0x080) * 8; |
c27a5ba9 FA |
983 | if (irq >= s->num_irq) { |
984 | goto bad_reg; | |
985 | } | |
986 | for (i = 0; i < 8; i++) { | |
67ce697a | 987 | if (GIC_DIST_TEST_GROUP(irq + i, cm)) { |
c27a5ba9 FA |
988 | res |= (1 << i); |
989 | } | |
990 | } | |
991 | } | |
992 | return res; | |
b79f2265 | 993 | } |
e69954b9 PB |
994 | goto bad_reg; |
995 | } else if (offset < 0x200) { | |
996 | /* Interrupt Set/Clear Enable. */ | |
997 | if (offset < 0x180) | |
998 | irq = (offset - 0x100) * 8; | |
999 | else | |
1000 | irq = (offset - 0x180) * 8; | |
a32134aa | 1001 | if (irq >= s->num_irq) |
e69954b9 PB |
1002 | goto bad_reg; |
1003 | res = 0; | |
1004 | for (i = 0; i < 8; i++) { | |
fea8a08e | 1005 | if (s->security_extn && !attrs.secure && |
67ce697a | 1006 | !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { |
fea8a08e JW |
1007 | continue; /* Ignore Non-secure access of Group0 IRQ */ |
1008 | } | |
1009 | ||
67ce697a | 1010 | if (GIC_DIST_TEST_ENABLED(irq + i, cm)) { |
e69954b9 PB |
1011 | res |= (1 << i); |
1012 | } | |
1013 | } | |
1014 | } else if (offset < 0x300) { | |
1015 | /* Interrupt Set/Clear Pending. */ | |
1016 | if (offset < 0x280) | |
1017 | irq = (offset - 0x200) * 8; | |
1018 | else | |
1019 | irq = (offset - 0x280) * 8; | |
a32134aa | 1020 | if (irq >= s->num_irq) |
e69954b9 PB |
1021 | goto bad_reg; |
1022 | res = 0; | |
69253800 | 1023 | mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; |
e69954b9 | 1024 | for (i = 0; i < 8; i++) { |
fea8a08e | 1025 | if (s->security_extn && !attrs.secure && |
67ce697a | 1026 | !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { |
fea8a08e JW |
1027 | continue; /* Ignore Non-secure access of Group0 IRQ */ |
1028 | } | |
1029 | ||
8d999995 | 1030 | if (gic_test_pending(s, irq + i, mask)) { |
e69954b9 PB |
1031 | res |= (1 << i); |
1032 | } | |
1033 | } | |
1034 | } else if (offset < 0x400) { | |
3bb0b038 LM |
1035 | /* Interrupt Set/Clear Active. */ |
1036 | if (offset < 0x380) { | |
1037 | irq = (offset - 0x300) * 8; | |
1038 | } else if (s->revision == 2) { | |
1039 | irq = (offset - 0x380) * 8; | |
1040 | } else { | |
1041 | goto bad_reg; | |
1042 | } | |
1043 | ||
a32134aa | 1044 | if (irq >= s->num_irq) |
e69954b9 PB |
1045 | goto bad_reg; |
1046 | res = 0; | |
69253800 | 1047 | mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; |
e69954b9 | 1048 | for (i = 0; i < 8; i++) { |
fea8a08e | 1049 | if (s->security_extn && !attrs.secure && |
67ce697a | 1050 | !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { |
fea8a08e JW |
1051 | continue; /* Ignore Non-secure access of Group0 IRQ */ |
1052 | } | |
1053 | ||
67ce697a | 1054 | if (GIC_DIST_TEST_ACTIVE(irq + i, mask)) { |
e69954b9 PB |
1055 | res |= (1 << i); |
1056 | } | |
1057 | } | |
1058 | } else if (offset < 0x800) { | |
1059 | /* Interrupt Priority. */ | |
b6e6c651 | 1060 | irq = (offset - 0x400); |
a32134aa | 1061 | if (irq >= s->num_irq) |
e69954b9 | 1062 | goto bad_reg; |
67ce697a | 1063 | res = gic_dist_get_priority(s, cpu, irq, attrs); |
e69954b9 PB |
1064 | } else if (offset < 0xc00) { |
1065 | /* Interrupt CPU Target. */ | |
6b9680bb PM |
1066 | if (s->num_cpu == 1 && s->revision != REV_11MPCORE) { |
1067 | /* For uniprocessor GICs these RAZ/WI */ | |
1068 | res = 0; | |
9ee6e8bb | 1069 | } else { |
b6e6c651 | 1070 | irq = (offset - 0x800); |
6b9680bb PM |
1071 | if (irq >= s->num_irq) { |
1072 | goto bad_reg; | |
1073 | } | |
7995206d PM |
1074 | if (irq < 29 && s->revision == REV_11MPCORE) { |
1075 | res = 0; | |
1076 | } else if (irq < GIC_INTERNAL) { | |
6b9680bb PM |
1077 | res = cm; |
1078 | } else { | |
67ce697a | 1079 | res = GIC_DIST_TARGET(irq); |
6b9680bb | 1080 | } |
9ee6e8bb | 1081 | } |
e69954b9 PB |
1082 | } else if (offset < 0xf00) { |
1083 | /* Interrupt Configuration. */ | |
b6e6c651 | 1084 | irq = (offset - 0xc00) * 4; |
a32134aa | 1085 | if (irq >= s->num_irq) |
e69954b9 PB |
1086 | goto bad_reg; |
1087 | res = 0; | |
1088 | for (i = 0; i < 4; i++) { | |
fea8a08e | 1089 | if (s->security_extn && !attrs.secure && |
67ce697a | 1090 | !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { |
fea8a08e JW |
1091 | continue; /* Ignore Non-secure access of Group0 IRQ */ |
1092 | } | |
1093 | ||
67ce697a | 1094 | if (GIC_DIST_TEST_MODEL(irq + i)) { |
e69954b9 | 1095 | res |= (1 << (i * 2)); |
67ce697a LM |
1096 | } |
1097 | if (GIC_DIST_TEST_EDGE_TRIGGER(irq + i)) { | |
e69954b9 | 1098 | res |= (2 << (i * 2)); |
67ce697a | 1099 | } |
e69954b9 | 1100 | } |
40d22500 CD |
1101 | } else if (offset < 0xf10) { |
1102 | goto bad_reg; | |
1103 | } else if (offset < 0xf30) { | |
7c14b3ac | 1104 | if (s->revision == REV_11MPCORE) { |
40d22500 CD |
1105 | goto bad_reg; |
1106 | } | |
1107 | ||
1108 | if (offset < 0xf20) { | |
1109 | /* GICD_CPENDSGIRn */ | |
1110 | irq = (offset - 0xf10); | |
1111 | } else { | |
1112 | irq = (offset - 0xf20); | |
1113 | /* GICD_SPENDSGIRn */ | |
1114 | } | |
1115 | ||
fea8a08e | 1116 | if (s->security_extn && !attrs.secure && |
67ce697a | 1117 | !GIC_DIST_TEST_GROUP(irq, 1 << cpu)) { |
fea8a08e JW |
1118 | res = 0; /* Ignore Non-secure access of Group0 IRQ */ |
1119 | } else { | |
1120 | res = s->sgi_pending[irq][cpu]; | |
1121 | } | |
3355c360 | 1122 | } else if (offset < 0xfd0) { |
e69954b9 | 1123 | goto bad_reg; |
3355c360 | 1124 | } else if (offset < 0x1000) { |
e69954b9 PB |
1125 | if (offset & 3) { |
1126 | res = 0; | |
1127 | } else { | |
3355c360 AF |
1128 | switch (s->revision) { |
1129 | case REV_11MPCORE: | |
1130 | res = gic_id_11mpcore[(offset - 0xfd0) >> 2]; | |
1131 | break; | |
1132 | case 1: | |
1133 | res = gic_id_gicv1[(offset - 0xfd0) >> 2]; | |
1134 | break; | |
1135 | case 2: | |
1136 | res = gic_id_gicv2[(offset - 0xfd0) >> 2]; | |
1137 | break; | |
3355c360 AF |
1138 | default: |
1139 | res = 0; | |
1140 | } | |
e69954b9 | 1141 | } |
3355c360 AF |
1142 | } else { |
1143 | g_assert_not_reached(); | |
e69954b9 PB |
1144 | } |
1145 | return res; | |
1146 | bad_reg: | |
8c8dc39f PM |
1147 | qemu_log_mask(LOG_GUEST_ERROR, |
1148 | "gic_dist_readb: Bad offset %x\n", (int)offset); | |
e69954b9 PB |
1149 | return 0; |
1150 | } | |
1151 | ||
a9d85353 PM |
1152 | static MemTxResult gic_dist_read(void *opaque, hwaddr offset, uint64_t *data, |
1153 | unsigned size, MemTxAttrs attrs) | |
e69954b9 | 1154 | { |
a9d85353 PM |
1155 | switch (size) { |
1156 | case 1: | |
1157 | *data = gic_dist_readb(opaque, offset, attrs); | |
067a2b9c | 1158 | break; |
a9d85353 PM |
1159 | case 2: |
1160 | *data = gic_dist_readb(opaque, offset, attrs); | |
1161 | *data |= gic_dist_readb(opaque, offset + 1, attrs) << 8; | |
067a2b9c | 1162 | break; |
a9d85353 PM |
1163 | case 4: |
1164 | *data = gic_dist_readb(opaque, offset, attrs); | |
1165 | *data |= gic_dist_readb(opaque, offset + 1, attrs) << 8; | |
1166 | *data |= gic_dist_readb(opaque, offset + 2, attrs) << 16; | |
1167 | *data |= gic_dist_readb(opaque, offset + 3, attrs) << 24; | |
067a2b9c | 1168 | break; |
a9d85353 PM |
1169 | default: |
1170 | return MEMTX_ERROR; | |
1171 | } | |
067a2b9c LM |
1172 | |
1173 | trace_gic_dist_read(offset, size, *data); | |
1174 | return MEMTX_OK; | |
e69954b9 PB |
1175 | } |
1176 | ||
a8170e5e | 1177 | static void gic_dist_writeb(void *opaque, hwaddr offset, |
a9d85353 | 1178 | uint32_t value, MemTxAttrs attrs) |
e69954b9 | 1179 | { |
fae15286 | 1180 | GICState *s = (GICState *)opaque; |
e69954b9 PB |
1181 | int irq; |
1182 | int i; | |
9ee6e8bb | 1183 | int cpu; |
e69954b9 | 1184 | |
926c4aff | 1185 | cpu = gic_get_current_cpu(s); |
e69954b9 PB |
1186 | if (offset < 0x100) { |
1187 | if (offset == 0) { | |
679aa175 FA |
1188 | if (s->security_extn && !attrs.secure) { |
1189 | /* NS version is just an alias of the S version's bit 1 */ | |
1190 | s->ctlr = deposit32(s->ctlr, 1, 1, value); | |
1191 | } else if (gic_has_groups(s)) { | |
1192 | s->ctlr = value & (GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1); | |
1193 | } else { | |
1194 | s->ctlr = value & GICD_CTLR_EN_GRP0; | |
1195 | } | |
1196 | DPRINTF("Distributor: Group0 %sabled; Group 1 %sabled\n", | |
1197 | s->ctlr & GICD_CTLR_EN_GRP0 ? "En" : "Dis", | |
1198 | s->ctlr & GICD_CTLR_EN_GRP1 ? "En" : "Dis"); | |
e69954b9 PB |
1199 | } else if (offset < 4) { |
1200 | /* ignored. */ | |
b79f2265 | 1201 | } else if (offset >= 0x80) { |
c27a5ba9 FA |
1202 | /* Interrupt Group Registers: RAZ/WI for NS access to secure |
1203 | * GIC, or for GICs without groups. | |
1204 | */ | |
1205 | if (!(s->security_extn && !attrs.secure) && gic_has_groups(s)) { | |
1206 | /* Every byte offset holds 8 group status bits */ | |
b6e6c651 | 1207 | irq = (offset - 0x80) * 8; |
c27a5ba9 FA |
1208 | if (irq >= s->num_irq) { |
1209 | goto bad_reg; | |
1210 | } | |
1211 | for (i = 0; i < 8; i++) { | |
1212 | /* Group bits are banked for private interrupts */ | |
1213 | int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; | |
1214 | if (value & (1 << i)) { | |
1215 | /* Group1 (Non-secure) */ | |
67ce697a | 1216 | GIC_DIST_SET_GROUP(irq + i, cm); |
c27a5ba9 FA |
1217 | } else { |
1218 | /* Group0 (Secure) */ | |
67ce697a | 1219 | GIC_DIST_CLEAR_GROUP(irq + i, cm); |
c27a5ba9 FA |
1220 | } |
1221 | } | |
1222 | } | |
e69954b9 PB |
1223 | } else { |
1224 | goto bad_reg; | |
1225 | } | |
1226 | } else if (offset < 0x180) { | |
1227 | /* Interrupt Set Enable. */ | |
b6e6c651 | 1228 | irq = (offset - 0x100) * 8; |
a32134aa | 1229 | if (irq >= s->num_irq) |
e69954b9 | 1230 | goto bad_reg; |
41ab7b55 CD |
1231 | if (irq < GIC_NR_SGIS) { |
1232 | value = 0xff; | |
1233 | } | |
1234 | ||
e69954b9 PB |
1235 | for (i = 0; i < 8; i++) { |
1236 | if (value & (1 << i)) { | |
f47b48fb | 1237 | int mask = |
67ce697a LM |
1238 | (irq < GIC_INTERNAL) ? (1 << cpu) |
1239 | : GIC_DIST_TARGET(irq + i); | |
69253800 | 1240 | int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; |
41bf234d | 1241 | |
fea8a08e | 1242 | if (s->security_extn && !attrs.secure && |
67ce697a | 1243 | !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { |
fea8a08e JW |
1244 | continue; /* Ignore Non-secure access of Group0 IRQ */ |
1245 | } | |
1246 | ||
67ce697a | 1247 | if (!GIC_DIST_TEST_ENABLED(irq + i, cm)) { |
e69954b9 | 1248 | DPRINTF("Enabled IRQ %d\n", irq + i); |
2531088f | 1249 | trace_gic_enable_irq(irq + i); |
41bf234d | 1250 | } |
67ce697a | 1251 | GIC_DIST_SET_ENABLED(irq + i, cm); |
e69954b9 PB |
1252 | /* If a raised level triggered IRQ enabled then mark |
1253 | is as pending. */ | |
67ce697a LM |
1254 | if (GIC_DIST_TEST_LEVEL(irq + i, mask) |
1255 | && !GIC_DIST_TEST_EDGE_TRIGGER(irq + i)) { | |
9ee6e8bb | 1256 | DPRINTF("Set %d pending mask %x\n", irq + i, mask); |
67ce697a | 1257 | GIC_DIST_SET_PENDING(irq + i, mask); |
9ee6e8bb | 1258 | } |
e69954b9 PB |
1259 | } |
1260 | } | |
1261 | } else if (offset < 0x200) { | |
1262 | /* Interrupt Clear Enable. */ | |
b6e6c651 | 1263 | irq = (offset - 0x180) * 8; |
a32134aa | 1264 | if (irq >= s->num_irq) |
e69954b9 | 1265 | goto bad_reg; |
41ab7b55 CD |
1266 | if (irq < GIC_NR_SGIS) { |
1267 | value = 0; | |
1268 | } | |
1269 | ||
e69954b9 PB |
1270 | for (i = 0; i < 8; i++) { |
1271 | if (value & (1 << i)) { | |
69253800 | 1272 | int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; |
41bf234d | 1273 | |
fea8a08e | 1274 | if (s->security_extn && !attrs.secure && |
67ce697a | 1275 | !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { |
fea8a08e JW |
1276 | continue; /* Ignore Non-secure access of Group0 IRQ */ |
1277 | } | |
1278 | ||
67ce697a | 1279 | if (GIC_DIST_TEST_ENABLED(irq + i, cm)) { |
e69954b9 | 1280 | DPRINTF("Disabled IRQ %d\n", irq + i); |
2531088f | 1281 | trace_gic_disable_irq(irq + i); |
41bf234d | 1282 | } |
67ce697a | 1283 | GIC_DIST_CLEAR_ENABLED(irq + i, cm); |
e69954b9 PB |
1284 | } |
1285 | } | |
1286 | } else if (offset < 0x280) { | |
1287 | /* Interrupt Set Pending. */ | |
b6e6c651 | 1288 | irq = (offset - 0x200) * 8; |
a32134aa | 1289 | if (irq >= s->num_irq) |
e69954b9 | 1290 | goto bad_reg; |
41ab7b55 | 1291 | if (irq < GIC_NR_SGIS) { |
5b0adce1 | 1292 | value = 0; |
41ab7b55 | 1293 | } |
9ee6e8bb | 1294 | |
e69954b9 PB |
1295 | for (i = 0; i < 8; i++) { |
1296 | if (value & (1 << i)) { | |
fea8a08e | 1297 | if (s->security_extn && !attrs.secure && |
67ce697a | 1298 | !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { |
fea8a08e JW |
1299 | continue; /* Ignore Non-secure access of Group0 IRQ */ |
1300 | } | |
1301 | ||
67ce697a | 1302 | GIC_DIST_SET_PENDING(irq + i, GIC_DIST_TARGET(irq + i)); |
e69954b9 PB |
1303 | } |
1304 | } | |
1305 | } else if (offset < 0x300) { | |
1306 | /* Interrupt Clear Pending. */ | |
b6e6c651 | 1307 | irq = (offset - 0x280) * 8; |
a32134aa | 1308 | if (irq >= s->num_irq) |
e69954b9 | 1309 | goto bad_reg; |
5b0adce1 CD |
1310 | if (irq < GIC_NR_SGIS) { |
1311 | value = 0; | |
1312 | } | |
1313 | ||
e69954b9 | 1314 | for (i = 0; i < 8; i++) { |
fea8a08e | 1315 | if (s->security_extn && !attrs.secure && |
67ce697a | 1316 | !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { |
fea8a08e JW |
1317 | continue; /* Ignore Non-secure access of Group0 IRQ */ |
1318 | } | |
1319 | ||
9ee6e8bb PB |
1320 | /* ??? This currently clears the pending bit for all CPUs, even |
1321 | for per-CPU interrupts. It's unclear whether this is the | |
1322 | corect behavior. */ | |
e69954b9 | 1323 | if (value & (1 << i)) { |
67ce697a | 1324 | GIC_DIST_CLEAR_PENDING(irq + i, ALL_CPU_MASK); |
e69954b9 PB |
1325 | } |
1326 | } | |
3bb0b038 LM |
1327 | } else if (offset < 0x380) { |
1328 | /* Interrupt Set Active. */ | |
1329 | if (s->revision != 2) { | |
1330 | goto bad_reg; | |
1331 | } | |
1332 | ||
b6e6c651 | 1333 | irq = (offset - 0x300) * 8; |
3bb0b038 LM |
1334 | if (irq >= s->num_irq) { |
1335 | goto bad_reg; | |
1336 | } | |
1337 | ||
1338 | /* This register is banked per-cpu for PPIs */ | |
1339 | int cm = irq < GIC_INTERNAL ? (1 << cpu) : ALL_CPU_MASK; | |
1340 | ||
1341 | for (i = 0; i < 8; i++) { | |
1342 | if (s->security_extn && !attrs.secure && | |
1343 | !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { | |
1344 | continue; /* Ignore Non-secure access of Group0 IRQ */ | |
1345 | } | |
1346 | ||
1347 | if (value & (1 << i)) { | |
1348 | GIC_DIST_SET_ACTIVE(irq + i, cm); | |
1349 | } | |
1350 | } | |
e69954b9 | 1351 | } else if (offset < 0x400) { |
3bb0b038 LM |
1352 | /* Interrupt Clear Active. */ |
1353 | if (s->revision != 2) { | |
1354 | goto bad_reg; | |
1355 | } | |
1356 | ||
b6e6c651 | 1357 | irq = (offset - 0x380) * 8; |
3bb0b038 LM |
1358 | if (irq >= s->num_irq) { |
1359 | goto bad_reg; | |
1360 | } | |
1361 | ||
1362 | /* This register is banked per-cpu for PPIs */ | |
1363 | int cm = irq < GIC_INTERNAL ? (1 << cpu) : ALL_CPU_MASK; | |
1364 | ||
1365 | for (i = 0; i < 8; i++) { | |
1366 | if (s->security_extn && !attrs.secure && | |
1367 | !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { | |
1368 | continue; /* Ignore Non-secure access of Group0 IRQ */ | |
1369 | } | |
1370 | ||
1371 | if (value & (1 << i)) { | |
1372 | GIC_DIST_CLEAR_ACTIVE(irq + i, cm); | |
1373 | } | |
1374 | } | |
e69954b9 PB |
1375 | } else if (offset < 0x800) { |
1376 | /* Interrupt Priority. */ | |
b6e6c651 | 1377 | irq = (offset - 0x400); |
a32134aa | 1378 | if (irq >= s->num_irq) |
e69954b9 | 1379 | goto bad_reg; |
67ce697a | 1380 | gic_dist_set_priority(s, cpu, irq, value, attrs); |
e69954b9 | 1381 | } else if (offset < 0xc00) { |
6b9680bb PM |
1382 | /* Interrupt CPU Target. RAZ/WI on uniprocessor GICs, with the |
1383 | * annoying exception of the 11MPCore's GIC. | |
1384 | */ | |
1385 | if (s->num_cpu != 1 || s->revision == REV_11MPCORE) { | |
b6e6c651 | 1386 | irq = (offset - 0x800); |
6b9680bb PM |
1387 | if (irq >= s->num_irq) { |
1388 | goto bad_reg; | |
1389 | } | |
7995206d | 1390 | if (irq < 29 && s->revision == REV_11MPCORE) { |
6b9680bb PM |
1391 | value = 0; |
1392 | } else if (irq < GIC_INTERNAL) { | |
1393 | value = ALL_CPU_MASK; | |
1394 | } | |
1395 | s->irq_target[irq] = value & ALL_CPU_MASK; | |
1396 | } | |
e69954b9 PB |
1397 | } else if (offset < 0xf00) { |
1398 | /* Interrupt Configuration. */ | |
b6e6c651 | 1399 | irq = (offset - 0xc00) * 4; |
a32134aa | 1400 | if (irq >= s->num_irq) |
e69954b9 | 1401 | goto bad_reg; |
de7a900f | 1402 | if (irq < GIC_NR_SGIS) |
9ee6e8bb | 1403 | value |= 0xaa; |
e69954b9 | 1404 | for (i = 0; i < 4; i++) { |
fea8a08e | 1405 | if (s->security_extn && !attrs.secure && |
67ce697a | 1406 | !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { |
fea8a08e JW |
1407 | continue; /* Ignore Non-secure access of Group0 IRQ */ |
1408 | } | |
1409 | ||
7c14b3ac | 1410 | if (s->revision == REV_11MPCORE) { |
24b790df | 1411 | if (value & (1 << (i * 2))) { |
67ce697a | 1412 | GIC_DIST_SET_MODEL(irq + i); |
24b790df | 1413 | } else { |
67ce697a | 1414 | GIC_DIST_CLEAR_MODEL(irq + i); |
24b790df | 1415 | } |
e69954b9 PB |
1416 | } |
1417 | if (value & (2 << (i * 2))) { | |
67ce697a | 1418 | GIC_DIST_SET_EDGE_TRIGGER(irq + i); |
e69954b9 | 1419 | } else { |
67ce697a | 1420 | GIC_DIST_CLEAR_EDGE_TRIGGER(irq + i); |
e69954b9 PB |
1421 | } |
1422 | } | |
40d22500 | 1423 | } else if (offset < 0xf10) { |
9ee6e8bb | 1424 | /* 0xf00 is only handled for 32-bit writes. */ |
e69954b9 | 1425 | goto bad_reg; |
40d22500 CD |
1426 | } else if (offset < 0xf20) { |
1427 | /* GICD_CPENDSGIRn */ | |
7c14b3ac | 1428 | if (s->revision == REV_11MPCORE) { |
40d22500 CD |
1429 | goto bad_reg; |
1430 | } | |
1431 | irq = (offset - 0xf10); | |
1432 | ||
fea8a08e | 1433 | if (!s->security_extn || attrs.secure || |
67ce697a | 1434 | GIC_DIST_TEST_GROUP(irq, 1 << cpu)) { |
fea8a08e JW |
1435 | s->sgi_pending[irq][cpu] &= ~value; |
1436 | if (s->sgi_pending[irq][cpu] == 0) { | |
67ce697a | 1437 | GIC_DIST_CLEAR_PENDING(irq, 1 << cpu); |
fea8a08e | 1438 | } |
40d22500 CD |
1439 | } |
1440 | } else if (offset < 0xf30) { | |
1441 | /* GICD_SPENDSGIRn */ | |
7c14b3ac | 1442 | if (s->revision == REV_11MPCORE) { |
40d22500 CD |
1443 | goto bad_reg; |
1444 | } | |
1445 | irq = (offset - 0xf20); | |
1446 | ||
fea8a08e | 1447 | if (!s->security_extn || attrs.secure || |
67ce697a LM |
1448 | GIC_DIST_TEST_GROUP(irq, 1 << cpu)) { |
1449 | GIC_DIST_SET_PENDING(irq, 1 << cpu); | |
fea8a08e JW |
1450 | s->sgi_pending[irq][cpu] |= value; |
1451 | } | |
40d22500 CD |
1452 | } else { |
1453 | goto bad_reg; | |
e69954b9 PB |
1454 | } |
1455 | gic_update(s); | |
1456 | return; | |
1457 | bad_reg: | |
8c8dc39f PM |
1458 | qemu_log_mask(LOG_GUEST_ERROR, |
1459 | "gic_dist_writeb: Bad offset %x\n", (int)offset); | |
e69954b9 PB |
1460 | } |
1461 | ||
a8170e5e | 1462 | static void gic_dist_writew(void *opaque, hwaddr offset, |
a9d85353 | 1463 | uint32_t value, MemTxAttrs attrs) |
e69954b9 | 1464 | { |
a9d85353 PM |
1465 | gic_dist_writeb(opaque, offset, value & 0xff, attrs); |
1466 | gic_dist_writeb(opaque, offset + 1, value >> 8, attrs); | |
e69954b9 PB |
1467 | } |
1468 | ||
a8170e5e | 1469 | static void gic_dist_writel(void *opaque, hwaddr offset, |
a9d85353 | 1470 | uint32_t value, MemTxAttrs attrs) |
e69954b9 | 1471 | { |
fae15286 | 1472 | GICState *s = (GICState *)opaque; |
8da3ff18 | 1473 | if (offset == 0xf00) { |
9ee6e8bb PB |
1474 | int cpu; |
1475 | int irq; | |
1476 | int mask; | |
40d22500 | 1477 | int target_cpu; |
9ee6e8bb | 1478 | |
926c4aff | 1479 | cpu = gic_get_current_cpu(s); |
edfe2eb4 | 1480 | irq = value & 0xf; |
9ee6e8bb PB |
1481 | switch ((value >> 24) & 3) { |
1482 | case 0: | |
1483 | mask = (value >> 16) & ALL_CPU_MASK; | |
1484 | break; | |
1485 | case 1: | |
fa250144 | 1486 | mask = ALL_CPU_MASK ^ (1 << cpu); |
9ee6e8bb PB |
1487 | break; |
1488 | case 2: | |
fa250144 | 1489 | mask = 1 << cpu; |
9ee6e8bb PB |
1490 | break; |
1491 | default: | |
1492 | DPRINTF("Bad Soft Int target filter\n"); | |
1493 | mask = ALL_CPU_MASK; | |
1494 | break; | |
1495 | } | |
67ce697a | 1496 | GIC_DIST_SET_PENDING(irq, mask); |
40d22500 CD |
1497 | target_cpu = ctz32(mask); |
1498 | while (target_cpu < GIC_NCPU) { | |
1499 | s->sgi_pending[irq][target_cpu] |= (1 << cpu); | |
1500 | mask &= ~(1 << target_cpu); | |
1501 | target_cpu = ctz32(mask); | |
1502 | } | |
9ee6e8bb PB |
1503 | gic_update(s); |
1504 | return; | |
1505 | } | |
a9d85353 PM |
1506 | gic_dist_writew(opaque, offset, value & 0xffff, attrs); |
1507 | gic_dist_writew(opaque, offset + 2, value >> 16, attrs); | |
1508 | } | |
1509 | ||
1510 | static MemTxResult gic_dist_write(void *opaque, hwaddr offset, uint64_t data, | |
1511 | unsigned size, MemTxAttrs attrs) | |
1512 | { | |
067a2b9c LM |
1513 | trace_gic_dist_write(offset, size, data); |
1514 | ||
a9d85353 PM |
1515 | switch (size) { |
1516 | case 1: | |
1517 | gic_dist_writeb(opaque, offset, data, attrs); | |
1518 | return MEMTX_OK; | |
1519 | case 2: | |
1520 | gic_dist_writew(opaque, offset, data, attrs); | |
1521 | return MEMTX_OK; | |
1522 | case 4: | |
1523 | gic_dist_writel(opaque, offset, data, attrs); | |
1524 | return MEMTX_OK; | |
1525 | default: | |
1526 | return MEMTX_ERROR; | |
1527 | } | |
e69954b9 PB |
1528 | } |
1529 | ||
51fd06e0 PM |
1530 | static inline uint32_t gic_apr_ns_view(GICState *s, int cpu, int regno) |
1531 | { | |
1532 | /* Return the Nonsecure view of GICC_APR<regno>. This is the | |
1533 | * second half of GICC_NSAPR. | |
1534 | */ | |
1535 | switch (GIC_MIN_BPR) { | |
1536 | case 0: | |
1537 | if (regno < 2) { | |
1538 | return s->nsapr[regno + 2][cpu]; | |
1539 | } | |
1540 | break; | |
1541 | case 1: | |
1542 | if (regno == 0) { | |
1543 | return s->nsapr[regno + 1][cpu]; | |
1544 | } | |
1545 | break; | |
1546 | case 2: | |
1547 | if (regno == 0) { | |
1548 | return extract32(s->nsapr[0][cpu], 16, 16); | |
1549 | } | |
1550 | break; | |
1551 | case 3: | |
1552 | if (regno == 0) { | |
1553 | return extract32(s->nsapr[0][cpu], 8, 8); | |
1554 | } | |
1555 | break; | |
1556 | default: | |
1557 | g_assert_not_reached(); | |
1558 | } | |
1559 | return 0; | |
1560 | } | |
1561 | ||
1562 | static inline void gic_apr_write_ns_view(GICState *s, int cpu, int regno, | |
1563 | uint32_t value) | |
1564 | { | |
1565 | /* Write the Nonsecure view of GICC_APR<regno>. */ | |
1566 | switch (GIC_MIN_BPR) { | |
1567 | case 0: | |
1568 | if (regno < 2) { | |
1569 | s->nsapr[regno + 2][cpu] = value; | |
1570 | } | |
1571 | break; | |
1572 | case 1: | |
1573 | if (regno == 0) { | |
1574 | s->nsapr[regno + 1][cpu] = value; | |
1575 | } | |
1576 | break; | |
1577 | case 2: | |
1578 | if (regno == 0) { | |
1579 | s->nsapr[0][cpu] = deposit32(s->nsapr[0][cpu], 16, 16, value); | |
1580 | } | |
1581 | break; | |
1582 | case 3: | |
1583 | if (regno == 0) { | |
1584 | s->nsapr[0][cpu] = deposit32(s->nsapr[0][cpu], 8, 8, value); | |
1585 | } | |
1586 | break; | |
1587 | default: | |
1588 | g_assert_not_reached(); | |
1589 | } | |
1590 | } | |
1591 | ||
a9d85353 PM |
1592 | static MemTxResult gic_cpu_read(GICState *s, int cpu, int offset, |
1593 | uint64_t *data, MemTxAttrs attrs) | |
e69954b9 | 1594 | { |
e69954b9 PB |
1595 | switch (offset) { |
1596 | case 0x00: /* Control */ | |
32951860 | 1597 | *data = gic_get_cpu_control(s, cpu, attrs); |
a9d85353 | 1598 | break; |
e69954b9 | 1599 | case 0x04: /* Priority mask */ |
81508470 | 1600 | *data = gic_get_priority_mask(s, cpu, attrs); |
a9d85353 | 1601 | break; |
e69954b9 | 1602 | case 0x08: /* Binary Point */ |
3dd0471b | 1603 | if (gic_cpu_ns_access(s, cpu, attrs)) { |
421a3c22 LM |
1604 | if (s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) { |
1605 | /* NS view of BPR when CBPR is 1 */ | |
1606 | *data = MIN(s->bpr[cpu] + 1, 7); | |
1607 | } else { | |
1608 | /* BPR is banked. Non-secure copy stored in ABPR. */ | |
1609 | *data = s->abpr[cpu]; | |
1610 | } | |
822e9cc3 FA |
1611 | } else { |
1612 | *data = s->bpr[cpu]; | |
1613 | } | |
a9d85353 | 1614 | break; |
e69954b9 | 1615 | case 0x0c: /* Acknowledge */ |
c5619bf9 | 1616 | *data = gic_acknowledge_irq(s, cpu, attrs); |
a9d85353 | 1617 | break; |
66a0a2cb | 1618 | case 0x14: /* Running Priority */ |
08efa9f2 | 1619 | *data = gic_get_running_priority(s, cpu, attrs); |
a9d85353 | 1620 | break; |
e69954b9 | 1621 | case 0x18: /* Highest Pending Interrupt */ |
7c0fa108 | 1622 | *data = gic_get_current_pending_irq(s, cpu, attrs); |
a9d85353 | 1623 | break; |
aa7d461a | 1624 | case 0x1c: /* Aliased Binary Point */ |
822e9cc3 FA |
1625 | /* GIC v2, no security: ABPR |
1626 | * GIC v1, no security: not implemented (RAZ/WI) | |
1627 | * With security extensions, secure access: ABPR (alias of NS BPR) | |
1628 | * With security extensions, nonsecure access: RAZ/WI | |
1629 | */ | |
3dd0471b | 1630 | if (!gic_has_groups(s) || (gic_cpu_ns_access(s, cpu, attrs))) { |
822e9cc3 FA |
1631 | *data = 0; |
1632 | } else { | |
1633 | *data = s->abpr[cpu]; | |
1634 | } | |
a9d85353 | 1635 | break; |
a9d477c4 | 1636 | case 0xd0: case 0xd4: case 0xd8: case 0xdc: |
51fd06e0 PM |
1637 | { |
1638 | int regno = (offset - 0xd0) / 4; | |
7eb079ec | 1639 | int nr_aprs = gic_is_vcpu(cpu) ? GIC_VIRT_NR_APRS : GIC_NR_APRS; |
51fd06e0 | 1640 | |
7eb079ec | 1641 | if (regno >= nr_aprs || s->revision != 2) { |
51fd06e0 | 1642 | *data = 0; |
7eb079ec LM |
1643 | } else if (gic_is_vcpu(cpu)) { |
1644 | *data = s->h_apr[gic_get_vcpu_real_id(cpu)]; | |
3dd0471b | 1645 | } else if (gic_cpu_ns_access(s, cpu, attrs)) { |
51fd06e0 PM |
1646 | /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */ |
1647 | *data = gic_apr_ns_view(s, regno, cpu); | |
1648 | } else { | |
1649 | *data = s->apr[regno][cpu]; | |
1650 | } | |
a9d85353 | 1651 | break; |
51fd06e0 PM |
1652 | } |
1653 | case 0xe0: case 0xe4: case 0xe8: case 0xec: | |
1654 | { | |
1655 | int regno = (offset - 0xe0) / 4; | |
1656 | ||
1657 | if (regno >= GIC_NR_APRS || s->revision != 2 || !gic_has_groups(s) || | |
7eb079ec | 1658 | gic_cpu_ns_access(s, cpu, attrs) || gic_is_vcpu(cpu)) { |
51fd06e0 PM |
1659 | *data = 0; |
1660 | } else { | |
1661 | *data = s->nsapr[regno][cpu]; | |
1662 | } | |
1663 | break; | |
1664 | } | |
e69954b9 | 1665 | default: |
8c8dc39f PM |
1666 | qemu_log_mask(LOG_GUEST_ERROR, |
1667 | "gic_cpu_read: Bad offset %x\n", (int)offset); | |
0cf09852 PM |
1668 | *data = 0; |
1669 | break; | |
e69954b9 | 1670 | } |
067a2b9c LM |
1671 | |
1672 | trace_gic_cpu_read(gic_is_vcpu(cpu) ? "vcpu" : "cpu", | |
1673 | gic_get_vcpu_real_id(cpu), offset, *data); | |
a9d85353 | 1674 | return MEMTX_OK; |
e69954b9 PB |
1675 | } |
1676 | ||
a9d85353 PM |
1677 | static MemTxResult gic_cpu_write(GICState *s, int cpu, int offset, |
1678 | uint32_t value, MemTxAttrs attrs) | |
e69954b9 | 1679 | { |
067a2b9c LM |
1680 | trace_gic_cpu_write(gic_is_vcpu(cpu) ? "vcpu" : "cpu", |
1681 | gic_get_vcpu_real_id(cpu), offset, value); | |
1682 | ||
e69954b9 PB |
1683 | switch (offset) { |
1684 | case 0x00: /* Control */ | |
32951860 | 1685 | gic_set_cpu_control(s, cpu, value, attrs); |
e69954b9 PB |
1686 | break; |
1687 | case 0x04: /* Priority mask */ | |
81508470 | 1688 | gic_set_priority_mask(s, cpu, value, attrs); |
e69954b9 PB |
1689 | break; |
1690 | case 0x08: /* Binary Point */ | |
3dd0471b | 1691 | if (gic_cpu_ns_access(s, cpu, attrs)) { |
421a3c22 LM |
1692 | if (s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) { |
1693 | /* WI when CBPR is 1 */ | |
1694 | return MEMTX_OK; | |
1695 | } else { | |
1696 | s->abpr[cpu] = MAX(value & 0x7, GIC_MIN_ABPR); | |
1697 | } | |
822e9cc3 | 1698 | } else { |
7eb079ec LM |
1699 | int min_bpr = gic_is_vcpu(cpu) ? GIC_VIRT_MIN_BPR : GIC_MIN_BPR; |
1700 | s->bpr[cpu] = MAX(value & 0x7, min_bpr); | |
822e9cc3 | 1701 | } |
e69954b9 PB |
1702 | break; |
1703 | case 0x10: /* End Of Interrupt */ | |
f9c6a7f1 | 1704 | gic_complete_irq(s, cpu, value & 0x3ff, attrs); |
a9d85353 | 1705 | return MEMTX_OK; |
aa7d461a | 1706 | case 0x1c: /* Aliased Binary Point */ |
3dd0471b | 1707 | if (!gic_has_groups(s) || (gic_cpu_ns_access(s, cpu, attrs))) { |
822e9cc3 FA |
1708 | /* unimplemented, or NS access: RAZ/WI */ |
1709 | return MEMTX_OK; | |
1710 | } else { | |
1711 | s->abpr[cpu] = MAX(value & 0x7, GIC_MIN_ABPR); | |
aa7d461a CD |
1712 | } |
1713 | break; | |
a9d477c4 | 1714 | case 0xd0: case 0xd4: case 0xd8: case 0xdc: |
51fd06e0 PM |
1715 | { |
1716 | int regno = (offset - 0xd0) / 4; | |
7eb079ec | 1717 | int nr_aprs = gic_is_vcpu(cpu) ? GIC_VIRT_NR_APRS : GIC_NR_APRS; |
51fd06e0 | 1718 | |
7eb079ec | 1719 | if (regno >= nr_aprs || s->revision != 2) { |
51fd06e0 PM |
1720 | return MEMTX_OK; |
1721 | } | |
7eb079ec LM |
1722 | if (gic_is_vcpu(cpu)) { |
1723 | s->h_apr[gic_get_vcpu_real_id(cpu)] = value; | |
1724 | } else if (gic_cpu_ns_access(s, cpu, attrs)) { | |
51fd06e0 PM |
1725 | /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */ |
1726 | gic_apr_write_ns_view(s, regno, cpu, value); | |
1727 | } else { | |
1728 | s->apr[regno][cpu] = value; | |
1729 | } | |
1730 | break; | |
1731 | } | |
1732 | case 0xe0: case 0xe4: case 0xe8: case 0xec: | |
1733 | { | |
1734 | int regno = (offset - 0xe0) / 4; | |
1735 | ||
1736 | if (regno >= GIC_NR_APRS || s->revision != 2) { | |
1737 | return MEMTX_OK; | |
1738 | } | |
7eb079ec LM |
1739 | if (gic_is_vcpu(cpu)) { |
1740 | return MEMTX_OK; | |
1741 | } | |
3dd0471b | 1742 | if (!gic_has_groups(s) || (gic_cpu_ns_access(s, cpu, attrs))) { |
51fd06e0 PM |
1743 | return MEMTX_OK; |
1744 | } | |
1745 | s->nsapr[regno][cpu] = value; | |
a9d477c4 | 1746 | break; |
51fd06e0 | 1747 | } |
a55c910e PM |
1748 | case 0x1000: |
1749 | /* GICC_DIR */ | |
1750 | gic_deactivate_irq(s, cpu, value & 0x3ff, attrs); | |
1751 | break; | |
e69954b9 | 1752 | default: |
8c8dc39f PM |
1753 | qemu_log_mask(LOG_GUEST_ERROR, |
1754 | "gic_cpu_write: Bad offset %x\n", (int)offset); | |
0cf09852 | 1755 | return MEMTX_OK; |
e69954b9 | 1756 | } |
cbe1282b LM |
1757 | |
1758 | if (gic_is_vcpu(cpu)) { | |
1759 | gic_update_virt(s); | |
1760 | } else { | |
1761 | gic_update(s); | |
1762 | } | |
1763 | ||
a9d85353 | 1764 | return MEMTX_OK; |
e69954b9 | 1765 | } |
e2c56465 PM |
1766 | |
1767 | /* Wrappers to read/write the GIC CPU interface for the current CPU */ | |
a9d85353 PM |
1768 | static MemTxResult gic_thiscpu_read(void *opaque, hwaddr addr, uint64_t *data, |
1769 | unsigned size, MemTxAttrs attrs) | |
e2c56465 | 1770 | { |
fae15286 | 1771 | GICState *s = (GICState *)opaque; |
a9d85353 | 1772 | return gic_cpu_read(s, gic_get_current_cpu(s), addr, data, attrs); |
e2c56465 PM |
1773 | } |
1774 | ||
a9d85353 PM |
1775 | static MemTxResult gic_thiscpu_write(void *opaque, hwaddr addr, |
1776 | uint64_t value, unsigned size, | |
1777 | MemTxAttrs attrs) | |
e2c56465 | 1778 | { |
fae15286 | 1779 | GICState *s = (GICState *)opaque; |
a9d85353 | 1780 | return gic_cpu_write(s, gic_get_current_cpu(s), addr, value, attrs); |
e2c56465 PM |
1781 | } |
1782 | ||
1783 | /* Wrappers to read/write the GIC CPU interface for a specific CPU. | |
fae15286 | 1784 | * These just decode the opaque pointer into GICState* + cpu id. |
e2c56465 | 1785 | */ |
a9d85353 PM |
1786 | static MemTxResult gic_do_cpu_read(void *opaque, hwaddr addr, uint64_t *data, |
1787 | unsigned size, MemTxAttrs attrs) | |
e2c56465 | 1788 | { |
fae15286 PM |
1789 | GICState **backref = (GICState **)opaque; |
1790 | GICState *s = *backref; | |
e2c56465 | 1791 | int id = (backref - s->backref); |
a9d85353 | 1792 | return gic_cpu_read(s, id, addr, data, attrs); |
e2c56465 PM |
1793 | } |
1794 | ||
a9d85353 PM |
1795 | static MemTxResult gic_do_cpu_write(void *opaque, hwaddr addr, |
1796 | uint64_t value, unsigned size, | |
1797 | MemTxAttrs attrs) | |
e2c56465 | 1798 | { |
fae15286 PM |
1799 | GICState **backref = (GICState **)opaque; |
1800 | GICState *s = *backref; | |
e2c56465 | 1801 | int id = (backref - s->backref); |
a9d85353 | 1802 | return gic_cpu_write(s, id, addr, value, attrs); |
e2c56465 PM |
1803 | } |
1804 | ||
2c679ac7 LM |
1805 | static MemTxResult gic_thisvcpu_read(void *opaque, hwaddr addr, uint64_t *data, |
1806 | unsigned size, MemTxAttrs attrs) | |
1807 | { | |
1808 | GICState *s = (GICState *)opaque; | |
1809 | ||
1810 | return gic_cpu_read(s, gic_get_current_vcpu(s), addr, data, attrs); | |
1811 | } | |
1812 | ||
1813 | static MemTxResult gic_thisvcpu_write(void *opaque, hwaddr addr, | |
1814 | uint64_t value, unsigned size, | |
1815 | MemTxAttrs attrs) | |
1816 | { | |
1817 | GICState *s = (GICState *)opaque; | |
1818 | ||
1819 | return gic_cpu_write(s, gic_get_current_vcpu(s), addr, value, attrs); | |
1820 | } | |
1821 | ||
527d296f LM |
1822 | static uint32_t gic_compute_eisr(GICState *s, int cpu, int lr_start) |
1823 | { | |
1824 | int lr_idx; | |
1825 | uint32_t ret = 0; | |
1826 | ||
1827 | for (lr_idx = lr_start; lr_idx < s->num_lrs; lr_idx++) { | |
1828 | uint32_t *entry = &s->h_lr[lr_idx][cpu]; | |
1829 | ret = deposit32(ret, lr_idx - lr_start, 1, | |
1830 | gic_lr_entry_is_eoi(*entry)); | |
1831 | } | |
1832 | ||
1833 | return ret; | |
1834 | } | |
1835 | ||
1836 | static uint32_t gic_compute_elrsr(GICState *s, int cpu, int lr_start) | |
1837 | { | |
1838 | int lr_idx; | |
1839 | uint32_t ret = 0; | |
1840 | ||
1841 | for (lr_idx = lr_start; lr_idx < s->num_lrs; lr_idx++) { | |
1842 | uint32_t *entry = &s->h_lr[lr_idx][cpu]; | |
1843 | ret = deposit32(ret, lr_idx - lr_start, 1, | |
1844 | gic_lr_entry_is_free(*entry)); | |
1845 | } | |
1846 | ||
1847 | return ret; | |
1848 | } | |
1849 | ||
1850 | static void gic_vmcr_write(GICState *s, uint32_t value, MemTxAttrs attrs) | |
1851 | { | |
1852 | int vcpu = gic_get_current_vcpu(s); | |
1853 | uint32_t ctlr; | |
1854 | uint32_t abpr; | |
1855 | uint32_t bpr; | |
1856 | uint32_t prio_mask; | |
1857 | ||
1858 | ctlr = FIELD_EX32(value, GICH_VMCR, VMCCtlr); | |
1859 | abpr = FIELD_EX32(value, GICH_VMCR, VMABP); | |
1860 | bpr = FIELD_EX32(value, GICH_VMCR, VMBP); | |
1861 | prio_mask = FIELD_EX32(value, GICH_VMCR, VMPriMask) << 3; | |
1862 | ||
1863 | gic_set_cpu_control(s, vcpu, ctlr, attrs); | |
1864 | s->abpr[vcpu] = MAX(abpr, GIC_VIRT_MIN_ABPR); | |
1865 | s->bpr[vcpu] = MAX(bpr, GIC_VIRT_MIN_BPR); | |
1866 | gic_set_priority_mask(s, vcpu, prio_mask, attrs); | |
1867 | } | |
1868 | ||
1869 | static MemTxResult gic_hyp_read(void *opaque, int cpu, hwaddr addr, | |
1870 | uint64_t *data, MemTxAttrs attrs) | |
1871 | { | |
1872 | GICState *s = ARM_GIC(opaque); | |
1873 | int vcpu = cpu + GIC_NCPU; | |
1874 | ||
1875 | switch (addr) { | |
1876 | case A_GICH_HCR: /* Hypervisor Control */ | |
1877 | *data = s->h_hcr[cpu]; | |
1878 | break; | |
1879 | ||
1880 | case A_GICH_VTR: /* VGIC Type */ | |
1881 | *data = FIELD_DP32(0, GICH_VTR, ListRegs, s->num_lrs - 1); | |
1882 | *data = FIELD_DP32(*data, GICH_VTR, PREbits, | |
1883 | GIC_VIRT_MAX_GROUP_PRIO_BITS - 1); | |
1884 | *data = FIELD_DP32(*data, GICH_VTR, PRIbits, | |
1885 | (7 - GIC_VIRT_MIN_BPR) - 1); | |
1886 | break; | |
1887 | ||
1888 | case A_GICH_VMCR: /* Virtual Machine Control */ | |
1889 | *data = FIELD_DP32(0, GICH_VMCR, VMCCtlr, | |
1890 | extract32(s->cpu_ctlr[vcpu], 0, 10)); | |
1891 | *data = FIELD_DP32(*data, GICH_VMCR, VMABP, s->abpr[vcpu]); | |
1892 | *data = FIELD_DP32(*data, GICH_VMCR, VMBP, s->bpr[vcpu]); | |
1893 | *data = FIELD_DP32(*data, GICH_VMCR, VMPriMask, | |
1894 | extract32(s->priority_mask[vcpu], 3, 5)); | |
1895 | break; | |
1896 | ||
1897 | case A_GICH_MISR: /* Maintenance Interrupt Status */ | |
1898 | *data = s->h_misr[cpu]; | |
1899 | break; | |
1900 | ||
1901 | case A_GICH_EISR0: /* End of Interrupt Status 0 and 1 */ | |
1902 | case A_GICH_EISR1: | |
1903 | *data = gic_compute_eisr(s, cpu, (addr - A_GICH_EISR0) * 8); | |
1904 | break; | |
1905 | ||
1906 | case A_GICH_ELRSR0: /* Empty List Status 0 and 1 */ | |
1907 | case A_GICH_ELRSR1: | |
1908 | *data = gic_compute_elrsr(s, cpu, (addr - A_GICH_ELRSR0) * 8); | |
1909 | break; | |
1910 | ||
1911 | case A_GICH_APR: /* Active Priorities */ | |
1912 | *data = s->h_apr[cpu]; | |
1913 | break; | |
1914 | ||
1915 | case A_GICH_LR0 ... A_GICH_LR63: /* List Registers */ | |
1916 | { | |
1917 | int lr_idx = (addr - A_GICH_LR0) / 4; | |
1918 | ||
1919 | if (lr_idx > s->num_lrs) { | |
1920 | *data = 0; | |
1921 | } else { | |
1922 | *data = s->h_lr[lr_idx][cpu]; | |
1923 | } | |
1924 | break; | |
1925 | } | |
1926 | ||
1927 | default: | |
1928 | qemu_log_mask(LOG_GUEST_ERROR, | |
1929 | "gic_hyp_read: Bad offset %" HWADDR_PRIx "\n", addr); | |
1930 | return MEMTX_OK; | |
1931 | } | |
1932 | ||
067a2b9c | 1933 | trace_gic_hyp_read(addr, *data); |
527d296f LM |
1934 | return MEMTX_OK; |
1935 | } | |
1936 | ||
1937 | static MemTxResult gic_hyp_write(void *opaque, int cpu, hwaddr addr, | |
1938 | uint64_t value, MemTxAttrs attrs) | |
1939 | { | |
1940 | GICState *s = ARM_GIC(opaque); | |
1941 | int vcpu = cpu + GIC_NCPU; | |
1942 | ||
067a2b9c LM |
1943 | trace_gic_hyp_write(addr, value); |
1944 | ||
527d296f LM |
1945 | switch (addr) { |
1946 | case A_GICH_HCR: /* Hypervisor Control */ | |
1947 | s->h_hcr[cpu] = value & GICH_HCR_MASK; | |
1948 | break; | |
1949 | ||
1950 | case A_GICH_VMCR: /* Virtual Machine Control */ | |
1951 | gic_vmcr_write(s, value, attrs); | |
1952 | break; | |
1953 | ||
1954 | case A_GICH_APR: /* Active Priorities */ | |
1955 | s->h_apr[cpu] = value; | |
1956 | s->running_priority[vcpu] = gic_get_prio_from_apr_bits(s, vcpu); | |
1957 | break; | |
1958 | ||
1959 | case A_GICH_LR0 ... A_GICH_LR63: /* List Registers */ | |
1960 | { | |
1961 | int lr_idx = (addr - A_GICH_LR0) / 4; | |
1962 | ||
1963 | if (lr_idx > s->num_lrs) { | |
1964 | return MEMTX_OK; | |
1965 | } | |
1966 | ||
1967 | s->h_lr[lr_idx][cpu] = value & GICH_LR_MASK; | |
067a2b9c | 1968 | trace_gic_lr_entry(cpu, lr_idx, s->h_lr[lr_idx][cpu]); |
527d296f LM |
1969 | break; |
1970 | } | |
1971 | ||
1972 | default: | |
1973 | qemu_log_mask(LOG_GUEST_ERROR, | |
1974 | "gic_hyp_write: Bad offset %" HWADDR_PRIx "\n", addr); | |
1975 | return MEMTX_OK; | |
1976 | } | |
1977 | ||
cbe1282b | 1978 | gic_update_virt(s); |
527d296f LM |
1979 | return MEMTX_OK; |
1980 | } | |
1981 | ||
1982 | static MemTxResult gic_thiscpu_hyp_read(void *opaque, hwaddr addr, uint64_t *data, | |
1983 | unsigned size, MemTxAttrs attrs) | |
1984 | { | |
1985 | GICState *s = (GICState *)opaque; | |
1986 | ||
1987 | return gic_hyp_read(s, gic_get_current_cpu(s), addr, data, attrs); | |
1988 | } | |
1989 | ||
1990 | static MemTxResult gic_thiscpu_hyp_write(void *opaque, hwaddr addr, | |
1991 | uint64_t value, unsigned size, | |
1992 | MemTxAttrs attrs) | |
1993 | { | |
1994 | GICState *s = (GICState *)opaque; | |
1995 | ||
1996 | return gic_hyp_write(s, gic_get_current_cpu(s), addr, value, attrs); | |
1997 | } | |
1998 | ||
1999 | static MemTxResult gic_do_hyp_read(void *opaque, hwaddr addr, uint64_t *data, | |
2000 | unsigned size, MemTxAttrs attrs) | |
2001 | { | |
2002 | GICState **backref = (GICState **)opaque; | |
2003 | GICState *s = *backref; | |
2004 | int id = (backref - s->backref); | |
2005 | ||
2006 | return gic_hyp_read(s, id, addr, data, attrs); | |
2007 | } | |
2008 | ||
2009 | static MemTxResult gic_do_hyp_write(void *opaque, hwaddr addr, | |
2010 | uint64_t value, unsigned size, | |
2011 | MemTxAttrs attrs) | |
2012 | { | |
2013 | GICState **backref = (GICState **)opaque; | |
2014 | GICState *s = *backref; | |
2015 | int id = (backref - s->backref); | |
2016 | ||
2017 | return gic_hyp_write(s, id + GIC_NCPU, addr, value, attrs); | |
2018 | ||
2019 | } | |
2020 | ||
7926c210 PF |
2021 | static const MemoryRegionOps gic_ops[2] = { |
2022 | { | |
2023 | .read_with_attrs = gic_dist_read, | |
2024 | .write_with_attrs = gic_dist_write, | |
2025 | .endianness = DEVICE_NATIVE_ENDIAN, | |
2026 | }, | |
2027 | { | |
2028 | .read_with_attrs = gic_thiscpu_read, | |
2029 | .write_with_attrs = gic_thiscpu_write, | |
2030 | .endianness = DEVICE_NATIVE_ENDIAN, | |
2031 | } | |
e2c56465 PM |
2032 | }; |
2033 | ||
2034 | static const MemoryRegionOps gic_cpu_ops = { | |
a9d85353 PM |
2035 | .read_with_attrs = gic_do_cpu_read, |
2036 | .write_with_attrs = gic_do_cpu_write, | |
e2c56465 PM |
2037 | .endianness = DEVICE_NATIVE_ENDIAN, |
2038 | }; | |
e69954b9 | 2039 | |
2c679ac7 LM |
2040 | static const MemoryRegionOps gic_virt_ops[2] = { |
2041 | { | |
527d296f LM |
2042 | .read_with_attrs = gic_thiscpu_hyp_read, |
2043 | .write_with_attrs = gic_thiscpu_hyp_write, | |
2c679ac7 LM |
2044 | .endianness = DEVICE_NATIVE_ENDIAN, |
2045 | }, | |
2046 | { | |
2047 | .read_with_attrs = gic_thisvcpu_read, | |
2048 | .write_with_attrs = gic_thisvcpu_write, | |
2049 | .endianness = DEVICE_NATIVE_ENDIAN, | |
2050 | } | |
2051 | }; | |
2052 | ||
527d296f LM |
2053 | static const MemoryRegionOps gic_viface_ops = { |
2054 | .read_with_attrs = gic_do_hyp_read, | |
2055 | .write_with_attrs = gic_do_hyp_write, | |
2056 | .endianness = DEVICE_NATIVE_ENDIAN, | |
2057 | }; | |
2058 | ||
53111180 | 2059 | static void arm_gic_realize(DeviceState *dev, Error **errp) |
2b518c56 | 2060 | { |
53111180 | 2061 | /* Device instance realize function for the GIC sysbus device */ |
2b518c56 | 2062 | int i; |
53111180 PM |
2063 | GICState *s = ARM_GIC(dev); |
2064 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | |
1e8cae4d | 2065 | ARMGICClass *agc = ARM_GIC_GET_CLASS(s); |
0175ba10 | 2066 | Error *local_err = NULL; |
1e8cae4d | 2067 | |
0175ba10 MA |
2068 | agc->parent_realize(dev, &local_err); |
2069 | if (local_err) { | |
2070 | error_propagate(errp, local_err); | |
53111180 PM |
2071 | return; |
2072 | } | |
1e8cae4d | 2073 | |
5d721b78 AG |
2074 | if (kvm_enabled() && !kvm_arm_supports_user_irq()) { |
2075 | error_setg(errp, "KVM with user space irqchip only works when the " | |
2076 | "host kernel supports KVM_CAP_ARM_USER_IRQ"); | |
2077 | return; | |
2078 | } | |
2079 | ||
11411489 SPB |
2080 | if (s->n_prio_bits > GIC_MAX_PRIORITY_BITS || |
2081 | (s->virt_extn ? s->n_prio_bits < GIC_VIRT_MAX_GROUP_PRIO_BITS : | |
2082 | s->n_prio_bits < GIC_MIN_PRIORITY_BITS)) { | |
2083 | error_setg(errp, "num-priority-bits cannot be greater than %d" | |
2084 | " or less than %d", GIC_MAX_PRIORITY_BITS, | |
2085 | s->virt_extn ? GIC_VIRT_MAX_GROUP_PRIO_BITS : | |
2086 | GIC_MIN_PRIORITY_BITS); | |
2087 | return; | |
2088 | } | |
2089 | ||
2c679ac7 LM |
2090 | /* This creates distributor, main CPU interface (s->cpuiomem[0]) and if |
2091 | * enabled, virtualization extensions related interfaces (main virtual | |
2092 | * interface (s->vifaceiomem[0]) and virtual CPU interface). | |
2093 | */ | |
2094 | gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops, gic_virt_ops); | |
2b518c56 | 2095 | |
7926c210 PF |
2096 | /* Extra core-specific regions for the CPU interfaces. This is |
2097 | * necessary for "franken-GIC" implementations, for example on | |
2098 | * Exynos 4. | |
e2c56465 PM |
2099 | * NB that the memory region size of 0x100 applies for the 11MPCore |
2100 | * and also cores following the GIC v1 spec (ie A9). | |
2101 | * GIC v2 defines a larger memory region (0x1000) so this will need | |
2102 | * to be extended when we implement A15. | |
2103 | */ | |
b95690c9 | 2104 | for (i = 0; i < s->num_cpu; i++) { |
e2c56465 | 2105 | s->backref[i] = s; |
1437c94b PB |
2106 | memory_region_init_io(&s->cpuiomem[i+1], OBJECT(s), &gic_cpu_ops, |
2107 | &s->backref[i], "gic_cpu", 0x100); | |
7926c210 | 2108 | sysbus_init_mmio(sbd, &s->cpuiomem[i+1]); |
496dbcd1 | 2109 | } |
527d296f LM |
2110 | |
2111 | /* Extra core-specific regions for virtual interfaces. This is required by | |
2112 | * the GICv2 specification. | |
2113 | */ | |
2114 | if (s->virt_extn) { | |
2115 | for (i = 0; i < s->num_cpu; i++) { | |
2116 | memory_region_init_io(&s->vifaceiomem[i + 1], OBJECT(s), | |
2117 | &gic_viface_ops, &s->backref[i], | |
7210918c | 2118 | "gic_viface", 0x200); |
527d296f LM |
2119 | sysbus_init_mmio(sbd, &s->vifaceiomem[i + 1]); |
2120 | } | |
2121 | } | |
2122 | ||
496dbcd1 PM |
2123 | } |
2124 | ||
496dbcd1 PM |
2125 | static void arm_gic_class_init(ObjectClass *klass, void *data) |
2126 | { | |
2127 | DeviceClass *dc = DEVICE_CLASS(klass); | |
1e8cae4d | 2128 | ARMGICClass *agc = ARM_GIC_CLASS(klass); |
53111180 | 2129 | |
bf853881 | 2130 | device_class_set_parent_realize(dc, arm_gic_realize, &agc->parent_realize); |
496dbcd1 PM |
2131 | } |
2132 | ||
8c43a6f0 | 2133 | static const TypeInfo arm_gic_info = { |
1e8cae4d PM |
2134 | .name = TYPE_ARM_GIC, |
2135 | .parent = TYPE_ARM_GIC_COMMON, | |
fae15286 | 2136 | .instance_size = sizeof(GICState), |
496dbcd1 | 2137 | .class_init = arm_gic_class_init, |
998a74bc | 2138 | .class_size = sizeof(ARMGICClass), |
496dbcd1 PM |
2139 | }; |
2140 | ||
2141 | static void arm_gic_register_types(void) | |
2142 | { | |
2143 | type_register_static(&arm_gic_info); | |
2144 | } | |
2145 | ||
2146 | type_init(arm_gic_register_types) |