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5fafdf24 | 1 | /* |
9ee6e8bb | 2 | * ARM Generic/Distributed Interrupt Controller |
e69954b9 | 3 | * |
9ee6e8bb | 4 | * Copyright (c) 2006-2007 CodeSourcery. |
e69954b9 PB |
5 | * Written by Paul Brook |
6 | * | |
8e31bf38 | 7 | * This code is licensed under the GPL. |
e69954b9 PB |
8 | */ |
9 | ||
9ee6e8bb | 10 | /* This file contains implementation code for the RealView EB interrupt |
0d256bdc PM |
11 | * controller, MPCore distributed interrupt controller and ARMv7-M |
12 | * Nested Vectored Interrupt Controller. | |
13 | * It is compiled in two ways: | |
14 | * (1) as a standalone file to produce a sysbus device which is a GIC | |
15 | * that can be used on the realview board and as one of the builtin | |
16 | * private peripherals for the ARM MP CPUs (11MPCore, A9, etc) | |
17 | * (2) by being directly #included into armv7m_nvic.c to produce the | |
18 | * armv7m_nvic device. | |
19 | */ | |
e69954b9 | 20 | |
83c9f4ca | 21 | #include "hw/sysbus.h" |
47b43a1f | 22 | #include "gic_internal.h" |
dfc08079 | 23 | #include "qom/cpu.h" |
386e2955 | 24 | |
e69954b9 PB |
25 | //#define DEBUG_GIC |
26 | ||
27 | #ifdef DEBUG_GIC | |
001faf32 | 28 | #define DPRINTF(fmt, ...) \ |
5eb98401 | 29 | do { fprintf(stderr, "arm_gic: " fmt , ## __VA_ARGS__); } while (0) |
e69954b9 | 30 | #else |
001faf32 | 31 | #define DPRINTF(fmt, ...) do {} while(0) |
e69954b9 PB |
32 | #endif |
33 | ||
2a29ddee PM |
34 | static const uint8_t gic_id[] = { |
35 | 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 | |
36 | }; | |
37 | ||
c988bfad | 38 | #define NUM_CPU(s) ((s)->num_cpu) |
9ee6e8bb | 39 | |
fae15286 | 40 | static inline int gic_get_current_cpu(GICState *s) |
926c4aff | 41 | { |
926c4aff | 42 | if (s->num_cpu > 1) { |
4917cf44 | 43 | return current_cpu->cpu_index; |
926c4aff | 44 | } |
926c4aff PM |
45 | return 0; |
46 | } | |
47 | ||
c27a5ba9 FA |
48 | /* Return true if this GIC config has interrupt groups, which is |
49 | * true if we're a GICv2, or a GICv1 with the security extensions. | |
50 | */ | |
51 | static inline bool gic_has_groups(GICState *s) | |
52 | { | |
53 | return s->revision == 2 || s->security_extn; | |
54 | } | |
55 | ||
e69954b9 PB |
56 | /* TODO: Many places that call this routine could be optimized. */ |
57 | /* Update interrupt status after enabled or pending bits have been changed. */ | |
fae15286 | 58 | void gic_update(GICState *s) |
e69954b9 PB |
59 | { |
60 | int best_irq; | |
61 | int best_prio; | |
62 | int irq; | |
dadbb58f | 63 | int irq_level, fiq_level; |
9ee6e8bb PB |
64 | int cpu; |
65 | int cm; | |
66 | ||
c988bfad | 67 | for (cpu = 0; cpu < NUM_CPU(s); cpu++) { |
9ee6e8bb PB |
68 | cm = 1 << cpu; |
69 | s->current_pending[cpu] = 1023; | |
679aa175 | 70 | if (!(s->ctlr & (GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1)) |
32951860 | 71 | || !(s->cpu_ctlr[cpu] & (GICC_CTLR_EN_GRP0 | GICC_CTLR_EN_GRP1))) { |
c79981ce | 72 | qemu_irq_lower(s->parent_irq[cpu]); |
dadbb58f | 73 | qemu_irq_lower(s->parent_fiq[cpu]); |
235069a3 | 74 | continue; |
9ee6e8bb PB |
75 | } |
76 | best_prio = 0x100; | |
77 | best_irq = 1023; | |
a32134aa | 78 | for (irq = 0; irq < s->num_irq; irq++) { |
b52b81e4 SF |
79 | if (GIC_TEST_ENABLED(irq, cm) && gic_test_pending(s, irq, cm) && |
80 | (irq < GIC_INTERNAL || GIC_TARGET(irq) & cm)) { | |
9ee6e8bb PB |
81 | if (GIC_GET_PRIORITY(irq, cpu) < best_prio) { |
82 | best_prio = GIC_GET_PRIORITY(irq, cpu); | |
83 | best_irq = irq; | |
84 | } | |
e69954b9 PB |
85 | } |
86 | } | |
dadbb58f PM |
87 | |
88 | irq_level = fiq_level = 0; | |
89 | ||
cad065f1 | 90 | if (best_prio < s->priority_mask[cpu]) { |
9ee6e8bb PB |
91 | s->current_pending[cpu] = best_irq; |
92 | if (best_prio < s->running_priority[cpu]) { | |
dadbb58f PM |
93 | int group = GIC_TEST_GROUP(best_irq, cm); |
94 | ||
95 | if (extract32(s->ctlr, group, 1) && | |
96 | extract32(s->cpu_ctlr[cpu], group, 1)) { | |
97 | if (group == 0 && s->cpu_ctlr[cpu] & GICC_CTLR_FIQ_EN) { | |
98 | DPRINTF("Raised pending FIQ %d (cpu %d)\n", | |
99 | best_irq, cpu); | |
100 | fiq_level = 1; | |
101 | } else { | |
102 | DPRINTF("Raised pending IRQ %d (cpu %d)\n", | |
103 | best_irq, cpu); | |
104 | irq_level = 1; | |
105 | } | |
106 | } | |
9ee6e8bb | 107 | } |
e69954b9 | 108 | } |
dadbb58f PM |
109 | |
110 | qemu_set_irq(s->parent_irq[cpu], irq_level); | |
111 | qemu_set_irq(s->parent_fiq[cpu], fiq_level); | |
e69954b9 PB |
112 | } |
113 | } | |
114 | ||
fae15286 | 115 | void gic_set_pending_private(GICState *s, int cpu, int irq) |
9ee6e8bb PB |
116 | { |
117 | int cm = 1 << cpu; | |
118 | ||
8d999995 | 119 | if (gic_test_pending(s, irq, cm)) { |
9ee6e8bb | 120 | return; |
8d999995 | 121 | } |
9ee6e8bb PB |
122 | |
123 | DPRINTF("Set %d pending cpu %d\n", irq, cpu); | |
124 | GIC_SET_PENDING(irq, cm); | |
125 | gic_update(s); | |
126 | } | |
127 | ||
8d999995 CD |
128 | static void gic_set_irq_11mpcore(GICState *s, int irq, int level, |
129 | int cm, int target) | |
130 | { | |
131 | if (level) { | |
132 | GIC_SET_LEVEL(irq, cm); | |
133 | if (GIC_TEST_EDGE_TRIGGER(irq) || GIC_TEST_ENABLED(irq, cm)) { | |
134 | DPRINTF("Set %d pending mask %x\n", irq, target); | |
135 | GIC_SET_PENDING(irq, target); | |
136 | } | |
137 | } else { | |
138 | GIC_CLEAR_LEVEL(irq, cm); | |
139 | } | |
140 | } | |
141 | ||
142 | static void gic_set_irq_generic(GICState *s, int irq, int level, | |
143 | int cm, int target) | |
144 | { | |
145 | if (level) { | |
146 | GIC_SET_LEVEL(irq, cm); | |
147 | DPRINTF("Set %d pending mask %x\n", irq, target); | |
148 | if (GIC_TEST_EDGE_TRIGGER(irq)) { | |
149 | GIC_SET_PENDING(irq, target); | |
150 | } | |
151 | } else { | |
152 | GIC_CLEAR_LEVEL(irq, cm); | |
153 | } | |
154 | } | |
155 | ||
9ee6e8bb | 156 | /* Process a change in an external IRQ input. */ |
e69954b9 PB |
157 | static void gic_set_irq(void *opaque, int irq, int level) |
158 | { | |
544d1afa PM |
159 | /* Meaning of the 'irq' parameter: |
160 | * [0..N-1] : external interrupts | |
161 | * [N..N+31] : PPI (internal) interrupts for CPU 0 | |
162 | * [N+32..N+63] : PPI (internal interrupts for CPU 1 | |
163 | * ... | |
164 | */ | |
fae15286 | 165 | GICState *s = (GICState *)opaque; |
544d1afa PM |
166 | int cm, target; |
167 | if (irq < (s->num_irq - GIC_INTERNAL)) { | |
168 | /* The first external input line is internal interrupt 32. */ | |
169 | cm = ALL_CPU_MASK; | |
170 | irq += GIC_INTERNAL; | |
171 | target = GIC_TARGET(irq); | |
172 | } else { | |
173 | int cpu; | |
174 | irq -= (s->num_irq - GIC_INTERNAL); | |
175 | cpu = irq / GIC_INTERNAL; | |
176 | irq %= GIC_INTERNAL; | |
177 | cm = 1 << cpu; | |
178 | target = cm; | |
179 | } | |
180 | ||
40d22500 CD |
181 | assert(irq >= GIC_NR_SGIS); |
182 | ||
544d1afa | 183 | if (level == GIC_TEST_LEVEL(irq, cm)) { |
e69954b9 | 184 | return; |
544d1afa | 185 | } |
e69954b9 | 186 | |
8d999995 CD |
187 | if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { |
188 | gic_set_irq_11mpcore(s, irq, level, cm, target); | |
e69954b9 | 189 | } else { |
8d999995 | 190 | gic_set_irq_generic(s, irq, level, cm, target); |
e69954b9 | 191 | } |
8d999995 | 192 | |
e69954b9 PB |
193 | gic_update(s); |
194 | } | |
195 | ||
7c0fa108 FA |
196 | static uint16_t gic_get_current_pending_irq(GICState *s, int cpu, |
197 | MemTxAttrs attrs) | |
198 | { | |
199 | uint16_t pending_irq = s->current_pending[cpu]; | |
200 | ||
201 | if (pending_irq < GIC_MAXIRQ && gic_has_groups(s)) { | |
202 | int group = GIC_TEST_GROUP(pending_irq, (1 << cpu)); | |
203 | /* On a GIC without the security extensions, reading this register | |
204 | * behaves in the same way as a secure access to a GIC with them. | |
205 | */ | |
206 | bool secure = !s->security_extn || attrs.secure; | |
207 | ||
208 | if (group == 0 && !secure) { | |
209 | /* Group0 interrupts hidden from Non-secure access */ | |
210 | return 1023; | |
211 | } | |
212 | if (group == 1 && secure && !(s->cpu_ctlr[cpu] & GICC_CTLR_ACK_CTL)) { | |
213 | /* Group1 interrupts only seen by Secure access if | |
214 | * AckCtl bit set. | |
215 | */ | |
216 | return 1022; | |
217 | } | |
218 | } | |
219 | return pending_irq; | |
220 | } | |
221 | ||
df92cfa6 PM |
222 | static int gic_get_group_priority(GICState *s, int cpu, int irq) |
223 | { | |
224 | /* Return the group priority of the specified interrupt | |
225 | * (which is the top bits of its priority, with the number | |
226 | * of bits masked determined by the applicable binary point register). | |
227 | */ | |
228 | int bpr; | |
229 | uint32_t mask; | |
230 | ||
231 | if (gic_has_groups(s) && | |
232 | !(s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) && | |
233 | GIC_TEST_GROUP(irq, (1 << cpu))) { | |
234 | bpr = s->abpr[cpu]; | |
235 | } else { | |
236 | bpr = s->bpr[cpu]; | |
237 | } | |
238 | ||
239 | /* a BPR of 0 means the group priority bits are [7:1]; | |
240 | * a BPR of 1 means they are [7:2], and so on down to | |
241 | * a BPR of 7 meaning no group priority bits at all. | |
242 | */ | |
243 | mask = ~0U << ((bpr & 7) + 1); | |
244 | ||
245 | return GIC_GET_PRIORITY(irq, cpu) & mask; | |
246 | } | |
247 | ||
72889c8a | 248 | static void gic_activate_irq(GICState *s, int cpu, int irq) |
e69954b9 | 249 | { |
72889c8a PM |
250 | /* Set the appropriate Active Priority Register bit for this IRQ, |
251 | * and update the running priority. | |
252 | */ | |
253 | int prio = gic_get_group_priority(s, cpu, irq); | |
254 | int preemption_level = prio >> (GIC_MIN_BPR + 1); | |
255 | int regno = preemption_level / 32; | |
256 | int bitno = preemption_level % 32; | |
257 | ||
258 | if (gic_has_groups(s) && GIC_TEST_GROUP(irq, (1 << cpu))) { | |
259 | s->nsapr[regno][cpu] &= (1 << bitno); | |
9ee6e8bb | 260 | } else { |
72889c8a | 261 | s->apr[regno][cpu] &= (1 << bitno); |
9ee6e8bb | 262 | } |
72889c8a PM |
263 | |
264 | s->running_priority[cpu] = prio; | |
d5523a13 | 265 | GIC_SET_ACTIVE(irq, 1 << cpu); |
72889c8a PM |
266 | } |
267 | ||
268 | static int gic_get_prio_from_apr_bits(GICState *s, int cpu) | |
269 | { | |
270 | /* Recalculate the current running priority for this CPU based | |
271 | * on the set bits in the Active Priority Registers. | |
272 | */ | |
273 | int i; | |
274 | for (i = 0; i < GIC_NR_APRS; i++) { | |
275 | uint32_t apr = s->apr[i][cpu] | s->nsapr[i][cpu]; | |
276 | if (!apr) { | |
277 | continue; | |
278 | } | |
279 | return (i * 32 + ctz32(apr)) << (GIC_MIN_BPR + 1); | |
280 | } | |
281 | return 0x100; | |
282 | } | |
283 | ||
284 | static void gic_drop_prio(GICState *s, int cpu, int group) | |
285 | { | |
286 | /* Drop the priority of the currently active interrupt in the | |
287 | * specified group. | |
288 | * | |
289 | * Note that we can guarantee (because of the requirement to nest | |
290 | * GICC_IAR reads [which activate an interrupt and raise priority] | |
291 | * with GICC_EOIR writes [which drop the priority for the interrupt]) | |
292 | * that the interrupt we're being called for is the highest priority | |
293 | * active interrupt, meaning that it has the lowest set bit in the | |
294 | * APR registers. | |
295 | * | |
296 | * If the guest does not honour the ordering constraints then the | |
297 | * behaviour of the GIC is UNPREDICTABLE, which for us means that | |
298 | * the values of the APR registers might become incorrect and the | |
299 | * running priority will be wrong, so interrupts that should preempt | |
300 | * might not do so, and interrupts that should not preempt might do so. | |
301 | */ | |
302 | int i; | |
303 | ||
304 | for (i = 0; i < GIC_NR_APRS; i++) { | |
305 | uint32_t *papr = group ? &s->nsapr[i][cpu] : &s->apr[i][cpu]; | |
306 | if (!*papr) { | |
307 | continue; | |
308 | } | |
309 | /* Clear lowest set bit */ | |
310 | *papr &= *papr - 1; | |
311 | break; | |
312 | } | |
313 | ||
314 | s->running_priority[cpu] = gic_get_prio_from_apr_bits(s, cpu); | |
e69954b9 PB |
315 | } |
316 | ||
c5619bf9 | 317 | uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs) |
e69954b9 | 318 | { |
40d22500 | 319 | int ret, irq, src; |
9ee6e8bb | 320 | int cm = 1 << cpu; |
c5619bf9 FA |
321 | |
322 | /* gic_get_current_pending_irq() will return 1022 or 1023 appropriately | |
323 | * for the case where this GIC supports grouping and the pending interrupt | |
324 | * is in the wrong group. | |
325 | */ | |
a8f15a27 | 326 | irq = gic_get_current_pending_irq(s, cpu, attrs); |
c5619bf9 FA |
327 | |
328 | if (irq >= GIC_MAXIRQ) { | |
329 | DPRINTF("ACK, no pending interrupt or it is hidden: %d\n", irq); | |
330 | return irq; | |
331 | } | |
332 | ||
333 | if (GIC_GET_PRIORITY(irq, cpu) >= s->running_priority[cpu]) { | |
334 | DPRINTF("ACK, pending interrupt (%d) has insufficient priority\n", irq); | |
e69954b9 PB |
335 | return 1023; |
336 | } | |
40d22500 | 337 | |
87316902 | 338 | if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { |
40d22500 CD |
339 | /* Clear pending flags for both level and edge triggered interrupts. |
340 | * Level triggered IRQs will be reasserted once they become inactive. | |
341 | */ | |
342 | GIC_CLEAR_PENDING(irq, GIC_TEST_MODEL(irq) ? ALL_CPU_MASK : cm); | |
343 | ret = irq; | |
344 | } else { | |
345 | if (irq < GIC_NR_SGIS) { | |
346 | /* Lookup the source CPU for the SGI and clear this in the | |
347 | * sgi_pending map. Return the src and clear the overall pending | |
348 | * state on this CPU if the SGI is not pending from any CPUs. | |
349 | */ | |
350 | assert(s->sgi_pending[irq][cpu] != 0); | |
351 | src = ctz32(s->sgi_pending[irq][cpu]); | |
352 | s->sgi_pending[irq][cpu] &= ~(1 << src); | |
353 | if (s->sgi_pending[irq][cpu] == 0) { | |
354 | GIC_CLEAR_PENDING(irq, GIC_TEST_MODEL(irq) ? ALL_CPU_MASK : cm); | |
355 | } | |
356 | ret = irq | ((src & 0x7) << 10); | |
357 | } else { | |
358 | /* Clear pending state for both level and edge triggered | |
359 | * interrupts. (level triggered interrupts with an active line | |
360 | * remain pending, see gic_test_pending) | |
361 | */ | |
362 | GIC_CLEAR_PENDING(irq, GIC_TEST_MODEL(irq) ? ALL_CPU_MASK : cm); | |
363 | ret = irq; | |
364 | } | |
365 | } | |
366 | ||
72889c8a PM |
367 | gic_activate_irq(s, cpu, irq); |
368 | gic_update(s); | |
40d22500 CD |
369 | DPRINTF("ACK %d\n", irq); |
370 | return ret; | |
e69954b9 PB |
371 | } |
372 | ||
81508470 FA |
373 | void gic_set_priority(GICState *s, int cpu, int irq, uint8_t val, |
374 | MemTxAttrs attrs) | |
9df90ad0 | 375 | { |
81508470 FA |
376 | if (s->security_extn && !attrs.secure) { |
377 | if (!GIC_TEST_GROUP(irq, (1 << cpu))) { | |
378 | return; /* Ignore Non-secure access of Group0 IRQ */ | |
379 | } | |
380 | val = 0x80 | (val >> 1); /* Non-secure view */ | |
381 | } | |
382 | ||
9df90ad0 CD |
383 | if (irq < GIC_INTERNAL) { |
384 | s->priority1[irq][cpu] = val; | |
385 | } else { | |
386 | s->priority2[(irq) - GIC_INTERNAL] = val; | |
387 | } | |
388 | } | |
389 | ||
81508470 FA |
390 | static uint32_t gic_get_priority(GICState *s, int cpu, int irq, |
391 | MemTxAttrs attrs) | |
392 | { | |
393 | uint32_t prio = GIC_GET_PRIORITY(irq, cpu); | |
394 | ||
395 | if (s->security_extn && !attrs.secure) { | |
396 | if (!GIC_TEST_GROUP(irq, (1 << cpu))) { | |
397 | return 0; /* Non-secure access cannot read priority of Group0 IRQ */ | |
398 | } | |
399 | prio = (prio << 1) & 0xff; /* Non-secure view */ | |
400 | } | |
401 | return prio; | |
402 | } | |
403 | ||
404 | static void gic_set_priority_mask(GICState *s, int cpu, uint8_t pmask, | |
405 | MemTxAttrs attrs) | |
406 | { | |
407 | if (s->security_extn && !attrs.secure) { | |
408 | if (s->priority_mask[cpu] & 0x80) { | |
409 | /* Priority Mask in upper half */ | |
410 | pmask = 0x80 | (pmask >> 1); | |
411 | } else { | |
412 | /* Non-secure write ignored if priority mask is in lower half */ | |
413 | return; | |
414 | } | |
415 | } | |
416 | s->priority_mask[cpu] = pmask; | |
417 | } | |
418 | ||
419 | static uint32_t gic_get_priority_mask(GICState *s, int cpu, MemTxAttrs attrs) | |
420 | { | |
421 | uint32_t pmask = s->priority_mask[cpu]; | |
422 | ||
423 | if (s->security_extn && !attrs.secure) { | |
424 | if (pmask & 0x80) { | |
425 | /* Priority Mask in upper half, return Non-secure view */ | |
426 | pmask = (pmask << 1) & 0xff; | |
427 | } else { | |
428 | /* Priority Mask in lower half, RAZ */ | |
429 | pmask = 0; | |
430 | } | |
431 | } | |
432 | return pmask; | |
433 | } | |
434 | ||
32951860 FA |
435 | static uint32_t gic_get_cpu_control(GICState *s, int cpu, MemTxAttrs attrs) |
436 | { | |
437 | uint32_t ret = s->cpu_ctlr[cpu]; | |
438 | ||
439 | if (s->security_extn && !attrs.secure) { | |
440 | /* Construct the NS banked view of GICC_CTLR from the correct | |
441 | * bits of the S banked view. We don't need to move the bypass | |
442 | * control bits because we don't implement that (IMPDEF) part | |
443 | * of the GIC architecture. | |
444 | */ | |
445 | ret = (ret & (GICC_CTLR_EN_GRP1 | GICC_CTLR_EOIMODE_NS)) >> 1; | |
446 | } | |
447 | return ret; | |
448 | } | |
449 | ||
450 | static void gic_set_cpu_control(GICState *s, int cpu, uint32_t value, | |
451 | MemTxAttrs attrs) | |
452 | { | |
453 | uint32_t mask; | |
454 | ||
455 | if (s->security_extn && !attrs.secure) { | |
456 | /* The NS view can only write certain bits in the register; | |
457 | * the rest are unchanged | |
458 | */ | |
459 | mask = GICC_CTLR_EN_GRP1; | |
460 | if (s->revision == 2) { | |
461 | mask |= GICC_CTLR_EOIMODE_NS; | |
462 | } | |
463 | s->cpu_ctlr[cpu] &= ~mask; | |
464 | s->cpu_ctlr[cpu] |= (value << 1) & mask; | |
465 | } else { | |
466 | if (s->revision == 2) { | |
467 | mask = s->security_extn ? GICC_CTLR_V2_S_MASK : GICC_CTLR_V2_MASK; | |
468 | } else { | |
469 | mask = s->security_extn ? GICC_CTLR_V1_S_MASK : GICC_CTLR_V1_MASK; | |
470 | } | |
471 | s->cpu_ctlr[cpu] = value & mask; | |
472 | } | |
473 | DPRINTF("CPU Interface %d: Group0 Interrupts %sabled, " | |
474 | "Group1 Interrupts %sabled\n", cpu, | |
475 | (s->cpu_ctlr[cpu] & GICC_CTLR_EN_GRP0) ? "En" : "Dis", | |
476 | (s->cpu_ctlr[cpu] & GICC_CTLR_EN_GRP1) ? "En" : "Dis"); | |
477 | } | |
478 | ||
08efa9f2 FA |
479 | static uint8_t gic_get_running_priority(GICState *s, int cpu, MemTxAttrs attrs) |
480 | { | |
481 | if (s->security_extn && !attrs.secure) { | |
482 | if (s->running_priority[cpu] & 0x80) { | |
483 | /* Running priority in upper half of range: return the Non-secure | |
484 | * view of the priority. | |
485 | */ | |
486 | return s->running_priority[cpu] << 1; | |
487 | } else { | |
488 | /* Running priority in lower half of range: RAZ */ | |
489 | return 0; | |
490 | } | |
491 | } else { | |
492 | return s->running_priority[cpu]; | |
493 | } | |
494 | } | |
495 | ||
f9c6a7f1 | 496 | void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs) |
e69954b9 | 497 | { |
9ee6e8bb | 498 | int cm = 1 << cpu; |
72889c8a PM |
499 | int group; |
500 | ||
df628ff1 | 501 | DPRINTF("EOI %d\n", irq); |
a32134aa | 502 | if (irq >= s->num_irq) { |
217bfb44 PM |
503 | /* This handles two cases: |
504 | * 1. If software writes the ID of a spurious interrupt [ie 1023] | |
505 | * to the GICC_EOIR, the GIC ignores that write. | |
506 | * 2. If software writes the number of a non-existent interrupt | |
507 | * this must be a subcase of "value written does not match the last | |
508 | * valid interrupt value read from the Interrupt Acknowledge | |
509 | * register" and so this is UNPREDICTABLE. We choose to ignore it. | |
510 | */ | |
511 | return; | |
512 | } | |
72889c8a | 513 | if (s->running_priority[cpu] == 0x100) { |
e69954b9 | 514 | return; /* No active IRQ. */ |
72889c8a | 515 | } |
8d999995 CD |
516 | |
517 | if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { | |
518 | /* Mark level triggered interrupts as pending if they are still | |
519 | raised. */ | |
520 | if (!GIC_TEST_EDGE_TRIGGER(irq) && GIC_TEST_ENABLED(irq, cm) | |
521 | && GIC_TEST_LEVEL(irq, cm) && (GIC_TARGET(irq) & cm) != 0) { | |
522 | DPRINTF("Set %d pending mask %x\n", irq, cm); | |
523 | GIC_SET_PENDING(irq, cm); | |
8d999995 | 524 | } |
e69954b9 | 525 | } |
8d999995 | 526 | |
72889c8a PM |
527 | group = gic_has_groups(s) && GIC_TEST_GROUP(irq, cm); |
528 | ||
529 | if (s->security_extn && !attrs.secure && !group) { | |
f9c6a7f1 FA |
530 | DPRINTF("Non-secure EOI for Group0 interrupt %d ignored\n", irq); |
531 | return; | |
532 | } | |
533 | ||
534 | /* Secure EOI with GICC_CTLR.AckCtl == 0 when the IRQ is a Group 1 | |
535 | * interrupt is UNPREDICTABLE. We choose to handle it as if AckCtl == 1, | |
536 | * i.e. go ahead and complete the irq anyway. | |
537 | */ | |
538 | ||
72889c8a | 539 | gic_drop_prio(s, cpu, group); |
d5523a13 | 540 | GIC_CLEAR_ACTIVE(irq, cm); |
72889c8a | 541 | gic_update(s); |
e69954b9 PB |
542 | } |
543 | ||
a9d85353 | 544 | static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs) |
e69954b9 | 545 | { |
fae15286 | 546 | GICState *s = (GICState *)opaque; |
e69954b9 PB |
547 | uint32_t res; |
548 | int irq; | |
549 | int i; | |
9ee6e8bb PB |
550 | int cpu; |
551 | int cm; | |
552 | int mask; | |
e69954b9 | 553 | |
926c4aff | 554 | cpu = gic_get_current_cpu(s); |
9ee6e8bb | 555 | cm = 1 << cpu; |
e69954b9 | 556 | if (offset < 0x100) { |
679aa175 FA |
557 | if (offset == 0) { /* GICD_CTLR */ |
558 | if (s->security_extn && !attrs.secure) { | |
559 | /* The NS bank of this register is just an alias of the | |
560 | * EnableGrp1 bit in the S bank version. | |
561 | */ | |
562 | return extract32(s->ctlr, 1, 1); | |
563 | } else { | |
564 | return s->ctlr; | |
565 | } | |
566 | } | |
e69954b9 | 567 | if (offset == 4) |
5543d1ab FA |
568 | /* Interrupt Controller Type Register */ |
569 | return ((s->num_irq / 32) - 1) | |
570 | | ((NUM_CPU(s) - 1) << 5) | |
571 | | (s->security_extn << 10); | |
e69954b9 PB |
572 | if (offset < 0x08) |
573 | return 0; | |
b79f2265 | 574 | if (offset >= 0x80) { |
c27a5ba9 FA |
575 | /* Interrupt Group Registers: these RAZ/WI if this is an NS |
576 | * access to a GIC with the security extensions, or if the GIC | |
577 | * doesn't have groups at all. | |
578 | */ | |
579 | res = 0; | |
580 | if (!(s->security_extn && !attrs.secure) && gic_has_groups(s)) { | |
581 | /* Every byte offset holds 8 group status bits */ | |
582 | irq = (offset - 0x080) * 8 + GIC_BASE_IRQ; | |
583 | if (irq >= s->num_irq) { | |
584 | goto bad_reg; | |
585 | } | |
586 | for (i = 0; i < 8; i++) { | |
587 | if (GIC_TEST_GROUP(irq + i, cm)) { | |
588 | res |= (1 << i); | |
589 | } | |
590 | } | |
591 | } | |
592 | return res; | |
b79f2265 | 593 | } |
e69954b9 PB |
594 | goto bad_reg; |
595 | } else if (offset < 0x200) { | |
596 | /* Interrupt Set/Clear Enable. */ | |
597 | if (offset < 0x180) | |
598 | irq = (offset - 0x100) * 8; | |
599 | else | |
600 | irq = (offset - 0x180) * 8; | |
9ee6e8bb | 601 | irq += GIC_BASE_IRQ; |
a32134aa | 602 | if (irq >= s->num_irq) |
e69954b9 PB |
603 | goto bad_reg; |
604 | res = 0; | |
605 | for (i = 0; i < 8; i++) { | |
41bf234d | 606 | if (GIC_TEST_ENABLED(irq + i, cm)) { |
e69954b9 PB |
607 | res |= (1 << i); |
608 | } | |
609 | } | |
610 | } else if (offset < 0x300) { | |
611 | /* Interrupt Set/Clear Pending. */ | |
612 | if (offset < 0x280) | |
613 | irq = (offset - 0x200) * 8; | |
614 | else | |
615 | irq = (offset - 0x280) * 8; | |
9ee6e8bb | 616 | irq += GIC_BASE_IRQ; |
a32134aa | 617 | if (irq >= s->num_irq) |
e69954b9 PB |
618 | goto bad_reg; |
619 | res = 0; | |
69253800 | 620 | mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; |
e69954b9 | 621 | for (i = 0; i < 8; i++) { |
8d999995 | 622 | if (gic_test_pending(s, irq + i, mask)) { |
e69954b9 PB |
623 | res |= (1 << i); |
624 | } | |
625 | } | |
626 | } else if (offset < 0x400) { | |
627 | /* Interrupt Active. */ | |
9ee6e8bb | 628 | irq = (offset - 0x300) * 8 + GIC_BASE_IRQ; |
a32134aa | 629 | if (irq >= s->num_irq) |
e69954b9 PB |
630 | goto bad_reg; |
631 | res = 0; | |
69253800 | 632 | mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; |
e69954b9 | 633 | for (i = 0; i < 8; i++) { |
9ee6e8bb | 634 | if (GIC_TEST_ACTIVE(irq + i, mask)) { |
e69954b9 PB |
635 | res |= (1 << i); |
636 | } | |
637 | } | |
638 | } else if (offset < 0x800) { | |
639 | /* Interrupt Priority. */ | |
9ee6e8bb | 640 | irq = (offset - 0x400) + GIC_BASE_IRQ; |
a32134aa | 641 | if (irq >= s->num_irq) |
e69954b9 | 642 | goto bad_reg; |
81508470 | 643 | res = gic_get_priority(s, cpu, irq, attrs); |
e69954b9 PB |
644 | } else if (offset < 0xc00) { |
645 | /* Interrupt CPU Target. */ | |
6b9680bb PM |
646 | if (s->num_cpu == 1 && s->revision != REV_11MPCORE) { |
647 | /* For uniprocessor GICs these RAZ/WI */ | |
648 | res = 0; | |
9ee6e8bb | 649 | } else { |
6b9680bb PM |
650 | irq = (offset - 0x800) + GIC_BASE_IRQ; |
651 | if (irq >= s->num_irq) { | |
652 | goto bad_reg; | |
653 | } | |
654 | if (irq >= 29 && irq <= 31) { | |
655 | res = cm; | |
656 | } else { | |
657 | res = GIC_TARGET(irq); | |
658 | } | |
9ee6e8bb | 659 | } |
e69954b9 PB |
660 | } else if (offset < 0xf00) { |
661 | /* Interrupt Configuration. */ | |
71a62046 | 662 | irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ; |
a32134aa | 663 | if (irq >= s->num_irq) |
e69954b9 PB |
664 | goto bad_reg; |
665 | res = 0; | |
666 | for (i = 0; i < 4; i++) { | |
667 | if (GIC_TEST_MODEL(irq + i)) | |
668 | res |= (1 << (i * 2)); | |
04050c5c | 669 | if (GIC_TEST_EDGE_TRIGGER(irq + i)) |
e69954b9 PB |
670 | res |= (2 << (i * 2)); |
671 | } | |
40d22500 CD |
672 | } else if (offset < 0xf10) { |
673 | goto bad_reg; | |
674 | } else if (offset < 0xf30) { | |
675 | if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { | |
676 | goto bad_reg; | |
677 | } | |
678 | ||
679 | if (offset < 0xf20) { | |
680 | /* GICD_CPENDSGIRn */ | |
681 | irq = (offset - 0xf10); | |
682 | } else { | |
683 | irq = (offset - 0xf20); | |
684 | /* GICD_SPENDSGIRn */ | |
685 | } | |
686 | ||
687 | res = s->sgi_pending[irq][cpu]; | |
e69954b9 PB |
688 | } else if (offset < 0xfe0) { |
689 | goto bad_reg; | |
690 | } else /* offset >= 0xfe0 */ { | |
691 | if (offset & 3) { | |
692 | res = 0; | |
693 | } else { | |
694 | res = gic_id[(offset - 0xfe0) >> 2]; | |
695 | } | |
696 | } | |
697 | return res; | |
698 | bad_reg: | |
8c8dc39f PM |
699 | qemu_log_mask(LOG_GUEST_ERROR, |
700 | "gic_dist_readb: Bad offset %x\n", (int)offset); | |
e69954b9 PB |
701 | return 0; |
702 | } | |
703 | ||
a9d85353 PM |
704 | static MemTxResult gic_dist_read(void *opaque, hwaddr offset, uint64_t *data, |
705 | unsigned size, MemTxAttrs attrs) | |
e69954b9 | 706 | { |
a9d85353 PM |
707 | switch (size) { |
708 | case 1: | |
709 | *data = gic_dist_readb(opaque, offset, attrs); | |
710 | return MEMTX_OK; | |
711 | case 2: | |
712 | *data = gic_dist_readb(opaque, offset, attrs); | |
713 | *data |= gic_dist_readb(opaque, offset + 1, attrs) << 8; | |
714 | return MEMTX_OK; | |
715 | case 4: | |
716 | *data = gic_dist_readb(opaque, offset, attrs); | |
717 | *data |= gic_dist_readb(opaque, offset + 1, attrs) << 8; | |
718 | *data |= gic_dist_readb(opaque, offset + 2, attrs) << 16; | |
719 | *data |= gic_dist_readb(opaque, offset + 3, attrs) << 24; | |
720 | return MEMTX_OK; | |
721 | default: | |
722 | return MEMTX_ERROR; | |
723 | } | |
e69954b9 PB |
724 | } |
725 | ||
a8170e5e | 726 | static void gic_dist_writeb(void *opaque, hwaddr offset, |
a9d85353 | 727 | uint32_t value, MemTxAttrs attrs) |
e69954b9 | 728 | { |
fae15286 | 729 | GICState *s = (GICState *)opaque; |
e69954b9 PB |
730 | int irq; |
731 | int i; | |
9ee6e8bb | 732 | int cpu; |
e69954b9 | 733 | |
926c4aff | 734 | cpu = gic_get_current_cpu(s); |
e69954b9 PB |
735 | if (offset < 0x100) { |
736 | if (offset == 0) { | |
679aa175 FA |
737 | if (s->security_extn && !attrs.secure) { |
738 | /* NS version is just an alias of the S version's bit 1 */ | |
739 | s->ctlr = deposit32(s->ctlr, 1, 1, value); | |
740 | } else if (gic_has_groups(s)) { | |
741 | s->ctlr = value & (GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1); | |
742 | } else { | |
743 | s->ctlr = value & GICD_CTLR_EN_GRP0; | |
744 | } | |
745 | DPRINTF("Distributor: Group0 %sabled; Group 1 %sabled\n", | |
746 | s->ctlr & GICD_CTLR_EN_GRP0 ? "En" : "Dis", | |
747 | s->ctlr & GICD_CTLR_EN_GRP1 ? "En" : "Dis"); | |
e69954b9 PB |
748 | } else if (offset < 4) { |
749 | /* ignored. */ | |
b79f2265 | 750 | } else if (offset >= 0x80) { |
c27a5ba9 FA |
751 | /* Interrupt Group Registers: RAZ/WI for NS access to secure |
752 | * GIC, or for GICs without groups. | |
753 | */ | |
754 | if (!(s->security_extn && !attrs.secure) && gic_has_groups(s)) { | |
755 | /* Every byte offset holds 8 group status bits */ | |
756 | irq = (offset - 0x80) * 8 + GIC_BASE_IRQ; | |
757 | if (irq >= s->num_irq) { | |
758 | goto bad_reg; | |
759 | } | |
760 | for (i = 0; i < 8; i++) { | |
761 | /* Group bits are banked for private interrupts */ | |
762 | int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; | |
763 | if (value & (1 << i)) { | |
764 | /* Group1 (Non-secure) */ | |
765 | GIC_SET_GROUP(irq + i, cm); | |
766 | } else { | |
767 | /* Group0 (Secure) */ | |
768 | GIC_CLEAR_GROUP(irq + i, cm); | |
769 | } | |
770 | } | |
771 | } | |
e69954b9 PB |
772 | } else { |
773 | goto bad_reg; | |
774 | } | |
775 | } else if (offset < 0x180) { | |
776 | /* Interrupt Set Enable. */ | |
9ee6e8bb | 777 | irq = (offset - 0x100) * 8 + GIC_BASE_IRQ; |
a32134aa | 778 | if (irq >= s->num_irq) |
e69954b9 | 779 | goto bad_reg; |
41ab7b55 CD |
780 | if (irq < GIC_NR_SGIS) { |
781 | value = 0xff; | |
782 | } | |
783 | ||
e69954b9 PB |
784 | for (i = 0; i < 8; i++) { |
785 | if (value & (1 << i)) { | |
f47b48fb DS |
786 | int mask = |
787 | (irq < GIC_INTERNAL) ? (1 << cpu) : GIC_TARGET(irq + i); | |
69253800 | 788 | int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; |
41bf234d RV |
789 | |
790 | if (!GIC_TEST_ENABLED(irq + i, cm)) { | |
e69954b9 | 791 | DPRINTF("Enabled IRQ %d\n", irq + i); |
41bf234d RV |
792 | } |
793 | GIC_SET_ENABLED(irq + i, cm); | |
e69954b9 PB |
794 | /* If a raised level triggered IRQ enabled then mark |
795 | is as pending. */ | |
9ee6e8bb | 796 | if (GIC_TEST_LEVEL(irq + i, mask) |
04050c5c | 797 | && !GIC_TEST_EDGE_TRIGGER(irq + i)) { |
9ee6e8bb PB |
798 | DPRINTF("Set %d pending mask %x\n", irq + i, mask); |
799 | GIC_SET_PENDING(irq + i, mask); | |
800 | } | |
e69954b9 PB |
801 | } |
802 | } | |
803 | } else if (offset < 0x200) { | |
804 | /* Interrupt Clear Enable. */ | |
9ee6e8bb | 805 | irq = (offset - 0x180) * 8 + GIC_BASE_IRQ; |
a32134aa | 806 | if (irq >= s->num_irq) |
e69954b9 | 807 | goto bad_reg; |
41ab7b55 CD |
808 | if (irq < GIC_NR_SGIS) { |
809 | value = 0; | |
810 | } | |
811 | ||
e69954b9 PB |
812 | for (i = 0; i < 8; i++) { |
813 | if (value & (1 << i)) { | |
69253800 | 814 | int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; |
41bf234d RV |
815 | |
816 | if (GIC_TEST_ENABLED(irq + i, cm)) { | |
e69954b9 | 817 | DPRINTF("Disabled IRQ %d\n", irq + i); |
41bf234d RV |
818 | } |
819 | GIC_CLEAR_ENABLED(irq + i, cm); | |
e69954b9 PB |
820 | } |
821 | } | |
822 | } else if (offset < 0x280) { | |
823 | /* Interrupt Set Pending. */ | |
9ee6e8bb | 824 | irq = (offset - 0x200) * 8 + GIC_BASE_IRQ; |
a32134aa | 825 | if (irq >= s->num_irq) |
e69954b9 | 826 | goto bad_reg; |
41ab7b55 | 827 | if (irq < GIC_NR_SGIS) { |
5b0adce1 | 828 | value = 0; |
41ab7b55 | 829 | } |
9ee6e8bb | 830 | |
e69954b9 PB |
831 | for (i = 0; i < 8; i++) { |
832 | if (value & (1 << i)) { | |
f47b48fb | 833 | GIC_SET_PENDING(irq + i, GIC_TARGET(irq + i)); |
e69954b9 PB |
834 | } |
835 | } | |
836 | } else if (offset < 0x300) { | |
837 | /* Interrupt Clear Pending. */ | |
9ee6e8bb | 838 | irq = (offset - 0x280) * 8 + GIC_BASE_IRQ; |
a32134aa | 839 | if (irq >= s->num_irq) |
e69954b9 | 840 | goto bad_reg; |
5b0adce1 CD |
841 | if (irq < GIC_NR_SGIS) { |
842 | value = 0; | |
843 | } | |
844 | ||
e69954b9 | 845 | for (i = 0; i < 8; i++) { |
9ee6e8bb PB |
846 | /* ??? This currently clears the pending bit for all CPUs, even |
847 | for per-CPU interrupts. It's unclear whether this is the | |
848 | corect behavior. */ | |
e69954b9 | 849 | if (value & (1 << i)) { |
9ee6e8bb | 850 | GIC_CLEAR_PENDING(irq + i, ALL_CPU_MASK); |
e69954b9 PB |
851 | } |
852 | } | |
853 | } else if (offset < 0x400) { | |
854 | /* Interrupt Active. */ | |
855 | goto bad_reg; | |
856 | } else if (offset < 0x800) { | |
857 | /* Interrupt Priority. */ | |
9ee6e8bb | 858 | irq = (offset - 0x400) + GIC_BASE_IRQ; |
a32134aa | 859 | if (irq >= s->num_irq) |
e69954b9 | 860 | goto bad_reg; |
81508470 | 861 | gic_set_priority(s, cpu, irq, value, attrs); |
e69954b9 | 862 | } else if (offset < 0xc00) { |
6b9680bb PM |
863 | /* Interrupt CPU Target. RAZ/WI on uniprocessor GICs, with the |
864 | * annoying exception of the 11MPCore's GIC. | |
865 | */ | |
866 | if (s->num_cpu != 1 || s->revision == REV_11MPCORE) { | |
867 | irq = (offset - 0x800) + GIC_BASE_IRQ; | |
868 | if (irq >= s->num_irq) { | |
869 | goto bad_reg; | |
870 | } | |
871 | if (irq < 29) { | |
872 | value = 0; | |
873 | } else if (irq < GIC_INTERNAL) { | |
874 | value = ALL_CPU_MASK; | |
875 | } | |
876 | s->irq_target[irq] = value & ALL_CPU_MASK; | |
877 | } | |
e69954b9 PB |
878 | } else if (offset < 0xf00) { |
879 | /* Interrupt Configuration. */ | |
9ee6e8bb | 880 | irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ; |
a32134aa | 881 | if (irq >= s->num_irq) |
e69954b9 | 882 | goto bad_reg; |
de7a900f | 883 | if (irq < GIC_NR_SGIS) |
9ee6e8bb | 884 | value |= 0xaa; |
e69954b9 | 885 | for (i = 0; i < 4; i++) { |
24b790df AL |
886 | if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { |
887 | if (value & (1 << (i * 2))) { | |
888 | GIC_SET_MODEL(irq + i); | |
889 | } else { | |
890 | GIC_CLEAR_MODEL(irq + i); | |
891 | } | |
e69954b9 PB |
892 | } |
893 | if (value & (2 << (i * 2))) { | |
04050c5c | 894 | GIC_SET_EDGE_TRIGGER(irq + i); |
e69954b9 | 895 | } else { |
04050c5c | 896 | GIC_CLEAR_EDGE_TRIGGER(irq + i); |
e69954b9 PB |
897 | } |
898 | } | |
40d22500 | 899 | } else if (offset < 0xf10) { |
9ee6e8bb | 900 | /* 0xf00 is only handled for 32-bit writes. */ |
e69954b9 | 901 | goto bad_reg; |
40d22500 CD |
902 | } else if (offset < 0xf20) { |
903 | /* GICD_CPENDSGIRn */ | |
904 | if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { | |
905 | goto bad_reg; | |
906 | } | |
907 | irq = (offset - 0xf10); | |
908 | ||
909 | s->sgi_pending[irq][cpu] &= ~value; | |
910 | if (s->sgi_pending[irq][cpu] == 0) { | |
911 | GIC_CLEAR_PENDING(irq, 1 << cpu); | |
912 | } | |
913 | } else if (offset < 0xf30) { | |
914 | /* GICD_SPENDSGIRn */ | |
915 | if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { | |
916 | goto bad_reg; | |
917 | } | |
918 | irq = (offset - 0xf20); | |
919 | ||
920 | GIC_SET_PENDING(irq, 1 << cpu); | |
921 | s->sgi_pending[irq][cpu] |= value; | |
922 | } else { | |
923 | goto bad_reg; | |
e69954b9 PB |
924 | } |
925 | gic_update(s); | |
926 | return; | |
927 | bad_reg: | |
8c8dc39f PM |
928 | qemu_log_mask(LOG_GUEST_ERROR, |
929 | "gic_dist_writeb: Bad offset %x\n", (int)offset); | |
e69954b9 PB |
930 | } |
931 | ||
a8170e5e | 932 | static void gic_dist_writew(void *opaque, hwaddr offset, |
a9d85353 | 933 | uint32_t value, MemTxAttrs attrs) |
e69954b9 | 934 | { |
a9d85353 PM |
935 | gic_dist_writeb(opaque, offset, value & 0xff, attrs); |
936 | gic_dist_writeb(opaque, offset + 1, value >> 8, attrs); | |
e69954b9 PB |
937 | } |
938 | ||
a8170e5e | 939 | static void gic_dist_writel(void *opaque, hwaddr offset, |
a9d85353 | 940 | uint32_t value, MemTxAttrs attrs) |
e69954b9 | 941 | { |
fae15286 | 942 | GICState *s = (GICState *)opaque; |
8da3ff18 | 943 | if (offset == 0xf00) { |
9ee6e8bb PB |
944 | int cpu; |
945 | int irq; | |
946 | int mask; | |
40d22500 | 947 | int target_cpu; |
9ee6e8bb | 948 | |
926c4aff | 949 | cpu = gic_get_current_cpu(s); |
9ee6e8bb PB |
950 | irq = value & 0x3ff; |
951 | switch ((value >> 24) & 3) { | |
952 | case 0: | |
953 | mask = (value >> 16) & ALL_CPU_MASK; | |
954 | break; | |
955 | case 1: | |
fa250144 | 956 | mask = ALL_CPU_MASK ^ (1 << cpu); |
9ee6e8bb PB |
957 | break; |
958 | case 2: | |
fa250144 | 959 | mask = 1 << cpu; |
9ee6e8bb PB |
960 | break; |
961 | default: | |
962 | DPRINTF("Bad Soft Int target filter\n"); | |
963 | mask = ALL_CPU_MASK; | |
964 | break; | |
965 | } | |
966 | GIC_SET_PENDING(irq, mask); | |
40d22500 CD |
967 | target_cpu = ctz32(mask); |
968 | while (target_cpu < GIC_NCPU) { | |
969 | s->sgi_pending[irq][target_cpu] |= (1 << cpu); | |
970 | mask &= ~(1 << target_cpu); | |
971 | target_cpu = ctz32(mask); | |
972 | } | |
9ee6e8bb PB |
973 | gic_update(s); |
974 | return; | |
975 | } | |
a9d85353 PM |
976 | gic_dist_writew(opaque, offset, value & 0xffff, attrs); |
977 | gic_dist_writew(opaque, offset + 2, value >> 16, attrs); | |
978 | } | |
979 | ||
980 | static MemTxResult gic_dist_write(void *opaque, hwaddr offset, uint64_t data, | |
981 | unsigned size, MemTxAttrs attrs) | |
982 | { | |
983 | switch (size) { | |
984 | case 1: | |
985 | gic_dist_writeb(opaque, offset, data, attrs); | |
986 | return MEMTX_OK; | |
987 | case 2: | |
988 | gic_dist_writew(opaque, offset, data, attrs); | |
989 | return MEMTX_OK; | |
990 | case 4: | |
991 | gic_dist_writel(opaque, offset, data, attrs); | |
992 | return MEMTX_OK; | |
993 | default: | |
994 | return MEMTX_ERROR; | |
995 | } | |
e69954b9 PB |
996 | } |
997 | ||
51fd06e0 PM |
998 | static inline uint32_t gic_apr_ns_view(GICState *s, int cpu, int regno) |
999 | { | |
1000 | /* Return the Nonsecure view of GICC_APR<regno>. This is the | |
1001 | * second half of GICC_NSAPR. | |
1002 | */ | |
1003 | switch (GIC_MIN_BPR) { | |
1004 | case 0: | |
1005 | if (regno < 2) { | |
1006 | return s->nsapr[regno + 2][cpu]; | |
1007 | } | |
1008 | break; | |
1009 | case 1: | |
1010 | if (regno == 0) { | |
1011 | return s->nsapr[regno + 1][cpu]; | |
1012 | } | |
1013 | break; | |
1014 | case 2: | |
1015 | if (regno == 0) { | |
1016 | return extract32(s->nsapr[0][cpu], 16, 16); | |
1017 | } | |
1018 | break; | |
1019 | case 3: | |
1020 | if (regno == 0) { | |
1021 | return extract32(s->nsapr[0][cpu], 8, 8); | |
1022 | } | |
1023 | break; | |
1024 | default: | |
1025 | g_assert_not_reached(); | |
1026 | } | |
1027 | return 0; | |
1028 | } | |
1029 | ||
1030 | static inline void gic_apr_write_ns_view(GICState *s, int cpu, int regno, | |
1031 | uint32_t value) | |
1032 | { | |
1033 | /* Write the Nonsecure view of GICC_APR<regno>. */ | |
1034 | switch (GIC_MIN_BPR) { | |
1035 | case 0: | |
1036 | if (regno < 2) { | |
1037 | s->nsapr[regno + 2][cpu] = value; | |
1038 | } | |
1039 | break; | |
1040 | case 1: | |
1041 | if (regno == 0) { | |
1042 | s->nsapr[regno + 1][cpu] = value; | |
1043 | } | |
1044 | break; | |
1045 | case 2: | |
1046 | if (regno == 0) { | |
1047 | s->nsapr[0][cpu] = deposit32(s->nsapr[0][cpu], 16, 16, value); | |
1048 | } | |
1049 | break; | |
1050 | case 3: | |
1051 | if (regno == 0) { | |
1052 | s->nsapr[0][cpu] = deposit32(s->nsapr[0][cpu], 8, 8, value); | |
1053 | } | |
1054 | break; | |
1055 | default: | |
1056 | g_assert_not_reached(); | |
1057 | } | |
1058 | } | |
1059 | ||
a9d85353 PM |
1060 | static MemTxResult gic_cpu_read(GICState *s, int cpu, int offset, |
1061 | uint64_t *data, MemTxAttrs attrs) | |
e69954b9 | 1062 | { |
e69954b9 PB |
1063 | switch (offset) { |
1064 | case 0x00: /* Control */ | |
32951860 | 1065 | *data = gic_get_cpu_control(s, cpu, attrs); |
a9d85353 | 1066 | break; |
e69954b9 | 1067 | case 0x04: /* Priority mask */ |
81508470 | 1068 | *data = gic_get_priority_mask(s, cpu, attrs); |
a9d85353 | 1069 | break; |
e69954b9 | 1070 | case 0x08: /* Binary Point */ |
822e9cc3 FA |
1071 | if (s->security_extn && !attrs.secure) { |
1072 | /* BPR is banked. Non-secure copy stored in ABPR. */ | |
1073 | *data = s->abpr[cpu]; | |
1074 | } else { | |
1075 | *data = s->bpr[cpu]; | |
1076 | } | |
a9d85353 | 1077 | break; |
e69954b9 | 1078 | case 0x0c: /* Acknowledge */ |
c5619bf9 | 1079 | *data = gic_acknowledge_irq(s, cpu, attrs); |
a9d85353 | 1080 | break; |
66a0a2cb | 1081 | case 0x14: /* Running Priority */ |
08efa9f2 | 1082 | *data = gic_get_running_priority(s, cpu, attrs); |
a9d85353 | 1083 | break; |
e69954b9 | 1084 | case 0x18: /* Highest Pending Interrupt */ |
7c0fa108 | 1085 | *data = gic_get_current_pending_irq(s, cpu, attrs); |
a9d85353 | 1086 | break; |
aa7d461a | 1087 | case 0x1c: /* Aliased Binary Point */ |
822e9cc3 FA |
1088 | /* GIC v2, no security: ABPR |
1089 | * GIC v1, no security: not implemented (RAZ/WI) | |
1090 | * With security extensions, secure access: ABPR (alias of NS BPR) | |
1091 | * With security extensions, nonsecure access: RAZ/WI | |
1092 | */ | |
1093 | if (!gic_has_groups(s) || (s->security_extn && !attrs.secure)) { | |
1094 | *data = 0; | |
1095 | } else { | |
1096 | *data = s->abpr[cpu]; | |
1097 | } | |
a9d85353 | 1098 | break; |
a9d477c4 | 1099 | case 0xd0: case 0xd4: case 0xd8: case 0xdc: |
51fd06e0 PM |
1100 | { |
1101 | int regno = (offset - 0xd0) / 4; | |
1102 | ||
1103 | if (regno >= GIC_NR_APRS || s->revision != 2) { | |
1104 | *data = 0; | |
1105 | } else if (s->security_extn && !attrs.secure) { | |
1106 | /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */ | |
1107 | *data = gic_apr_ns_view(s, regno, cpu); | |
1108 | } else { | |
1109 | *data = s->apr[regno][cpu]; | |
1110 | } | |
a9d85353 | 1111 | break; |
51fd06e0 PM |
1112 | } |
1113 | case 0xe0: case 0xe4: case 0xe8: case 0xec: | |
1114 | { | |
1115 | int regno = (offset - 0xe0) / 4; | |
1116 | ||
1117 | if (regno >= GIC_NR_APRS || s->revision != 2 || !gic_has_groups(s) || | |
1118 | (s->security_extn && !attrs.secure)) { | |
1119 | *data = 0; | |
1120 | } else { | |
1121 | *data = s->nsapr[regno][cpu]; | |
1122 | } | |
1123 | break; | |
1124 | } | |
e69954b9 | 1125 | default: |
8c8dc39f PM |
1126 | qemu_log_mask(LOG_GUEST_ERROR, |
1127 | "gic_cpu_read: Bad offset %x\n", (int)offset); | |
a9d85353 | 1128 | return MEMTX_ERROR; |
e69954b9 | 1129 | } |
a9d85353 | 1130 | return MEMTX_OK; |
e69954b9 PB |
1131 | } |
1132 | ||
a9d85353 PM |
1133 | static MemTxResult gic_cpu_write(GICState *s, int cpu, int offset, |
1134 | uint32_t value, MemTxAttrs attrs) | |
e69954b9 | 1135 | { |
e69954b9 PB |
1136 | switch (offset) { |
1137 | case 0x00: /* Control */ | |
32951860 | 1138 | gic_set_cpu_control(s, cpu, value, attrs); |
e69954b9 PB |
1139 | break; |
1140 | case 0x04: /* Priority mask */ | |
81508470 | 1141 | gic_set_priority_mask(s, cpu, value, attrs); |
e69954b9 PB |
1142 | break; |
1143 | case 0x08: /* Binary Point */ | |
822e9cc3 FA |
1144 | if (s->security_extn && !attrs.secure) { |
1145 | s->abpr[cpu] = MAX(value & 0x7, GIC_MIN_ABPR); | |
1146 | } else { | |
1147 | s->bpr[cpu] = MAX(value & 0x7, GIC_MIN_BPR); | |
1148 | } | |
e69954b9 PB |
1149 | break; |
1150 | case 0x10: /* End Of Interrupt */ | |
f9c6a7f1 | 1151 | gic_complete_irq(s, cpu, value & 0x3ff, attrs); |
a9d85353 | 1152 | return MEMTX_OK; |
aa7d461a | 1153 | case 0x1c: /* Aliased Binary Point */ |
822e9cc3 FA |
1154 | if (!gic_has_groups(s) || (s->security_extn && !attrs.secure)) { |
1155 | /* unimplemented, or NS access: RAZ/WI */ | |
1156 | return MEMTX_OK; | |
1157 | } else { | |
1158 | s->abpr[cpu] = MAX(value & 0x7, GIC_MIN_ABPR); | |
aa7d461a CD |
1159 | } |
1160 | break; | |
a9d477c4 | 1161 | case 0xd0: case 0xd4: case 0xd8: case 0xdc: |
51fd06e0 PM |
1162 | { |
1163 | int regno = (offset - 0xd0) / 4; | |
1164 | ||
1165 | if (regno >= GIC_NR_APRS || s->revision != 2) { | |
1166 | return MEMTX_OK; | |
1167 | } | |
1168 | if (s->security_extn && !attrs.secure) { | |
1169 | /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */ | |
1170 | gic_apr_write_ns_view(s, regno, cpu, value); | |
1171 | } else { | |
1172 | s->apr[regno][cpu] = value; | |
1173 | } | |
1174 | break; | |
1175 | } | |
1176 | case 0xe0: case 0xe4: case 0xe8: case 0xec: | |
1177 | { | |
1178 | int regno = (offset - 0xe0) / 4; | |
1179 | ||
1180 | if (regno >= GIC_NR_APRS || s->revision != 2) { | |
1181 | return MEMTX_OK; | |
1182 | } | |
1183 | if (!gic_has_groups(s) || (s->security_extn && !attrs.secure)) { | |
1184 | return MEMTX_OK; | |
1185 | } | |
1186 | s->nsapr[regno][cpu] = value; | |
a9d477c4 | 1187 | break; |
51fd06e0 | 1188 | } |
e69954b9 | 1189 | default: |
8c8dc39f PM |
1190 | qemu_log_mask(LOG_GUEST_ERROR, |
1191 | "gic_cpu_write: Bad offset %x\n", (int)offset); | |
a9d85353 | 1192 | return MEMTX_ERROR; |
e69954b9 PB |
1193 | } |
1194 | gic_update(s); | |
a9d85353 | 1195 | return MEMTX_OK; |
e69954b9 | 1196 | } |
e2c56465 PM |
1197 | |
1198 | /* Wrappers to read/write the GIC CPU interface for the current CPU */ | |
a9d85353 PM |
1199 | static MemTxResult gic_thiscpu_read(void *opaque, hwaddr addr, uint64_t *data, |
1200 | unsigned size, MemTxAttrs attrs) | |
e2c56465 | 1201 | { |
fae15286 | 1202 | GICState *s = (GICState *)opaque; |
a9d85353 | 1203 | return gic_cpu_read(s, gic_get_current_cpu(s), addr, data, attrs); |
e2c56465 PM |
1204 | } |
1205 | ||
a9d85353 PM |
1206 | static MemTxResult gic_thiscpu_write(void *opaque, hwaddr addr, |
1207 | uint64_t value, unsigned size, | |
1208 | MemTxAttrs attrs) | |
e2c56465 | 1209 | { |
fae15286 | 1210 | GICState *s = (GICState *)opaque; |
a9d85353 | 1211 | return gic_cpu_write(s, gic_get_current_cpu(s), addr, value, attrs); |
e2c56465 PM |
1212 | } |
1213 | ||
1214 | /* Wrappers to read/write the GIC CPU interface for a specific CPU. | |
fae15286 | 1215 | * These just decode the opaque pointer into GICState* + cpu id. |
e2c56465 | 1216 | */ |
a9d85353 PM |
1217 | static MemTxResult gic_do_cpu_read(void *opaque, hwaddr addr, uint64_t *data, |
1218 | unsigned size, MemTxAttrs attrs) | |
e2c56465 | 1219 | { |
fae15286 PM |
1220 | GICState **backref = (GICState **)opaque; |
1221 | GICState *s = *backref; | |
e2c56465 | 1222 | int id = (backref - s->backref); |
a9d85353 | 1223 | return gic_cpu_read(s, id, addr, data, attrs); |
e2c56465 PM |
1224 | } |
1225 | ||
a9d85353 PM |
1226 | static MemTxResult gic_do_cpu_write(void *opaque, hwaddr addr, |
1227 | uint64_t value, unsigned size, | |
1228 | MemTxAttrs attrs) | |
e2c56465 | 1229 | { |
fae15286 PM |
1230 | GICState **backref = (GICState **)opaque; |
1231 | GICState *s = *backref; | |
e2c56465 | 1232 | int id = (backref - s->backref); |
a9d85353 | 1233 | return gic_cpu_write(s, id, addr, value, attrs); |
e2c56465 PM |
1234 | } |
1235 | ||
7926c210 PF |
1236 | static const MemoryRegionOps gic_ops[2] = { |
1237 | { | |
1238 | .read_with_attrs = gic_dist_read, | |
1239 | .write_with_attrs = gic_dist_write, | |
1240 | .endianness = DEVICE_NATIVE_ENDIAN, | |
1241 | }, | |
1242 | { | |
1243 | .read_with_attrs = gic_thiscpu_read, | |
1244 | .write_with_attrs = gic_thiscpu_write, | |
1245 | .endianness = DEVICE_NATIVE_ENDIAN, | |
1246 | } | |
e2c56465 PM |
1247 | }; |
1248 | ||
1249 | static const MemoryRegionOps gic_cpu_ops = { | |
a9d85353 PM |
1250 | .read_with_attrs = gic_do_cpu_read, |
1251 | .write_with_attrs = gic_do_cpu_write, | |
e2c56465 PM |
1252 | .endianness = DEVICE_NATIVE_ENDIAN, |
1253 | }; | |
e69954b9 | 1254 | |
7926c210 | 1255 | /* This function is used by nvic model */ |
7b95a508 | 1256 | void gic_init_irqs_and_distributor(GICState *s) |
e69954b9 | 1257 | { |
7926c210 | 1258 | gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops); |
2b518c56 PM |
1259 | } |
1260 | ||
53111180 | 1261 | static void arm_gic_realize(DeviceState *dev, Error **errp) |
2b518c56 | 1262 | { |
53111180 | 1263 | /* Device instance realize function for the GIC sysbus device */ |
2b518c56 | 1264 | int i; |
53111180 PM |
1265 | GICState *s = ARM_GIC(dev); |
1266 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | |
1e8cae4d | 1267 | ARMGICClass *agc = ARM_GIC_GET_CLASS(s); |
0175ba10 | 1268 | Error *local_err = NULL; |
1e8cae4d | 1269 | |
0175ba10 MA |
1270 | agc->parent_realize(dev, &local_err); |
1271 | if (local_err) { | |
1272 | error_propagate(errp, local_err); | |
53111180 PM |
1273 | return; |
1274 | } | |
1e8cae4d | 1275 | |
7926c210 PF |
1276 | /* This creates distributor and main CPU interface (s->cpuiomem[0]) */ |
1277 | gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops); | |
2b518c56 | 1278 | |
7926c210 PF |
1279 | /* Extra core-specific regions for the CPU interfaces. This is |
1280 | * necessary for "franken-GIC" implementations, for example on | |
1281 | * Exynos 4. | |
e2c56465 PM |
1282 | * NB that the memory region size of 0x100 applies for the 11MPCore |
1283 | * and also cores following the GIC v1 spec (ie A9). | |
1284 | * GIC v2 defines a larger memory region (0x1000) so this will need | |
1285 | * to be extended when we implement A15. | |
1286 | */ | |
e2c56465 PM |
1287 | for (i = 0; i < NUM_CPU(s); i++) { |
1288 | s->backref[i] = s; | |
1437c94b PB |
1289 | memory_region_init_io(&s->cpuiomem[i+1], OBJECT(s), &gic_cpu_ops, |
1290 | &s->backref[i], "gic_cpu", 0x100); | |
7926c210 | 1291 | sysbus_init_mmio(sbd, &s->cpuiomem[i+1]); |
496dbcd1 | 1292 | } |
496dbcd1 PM |
1293 | } |
1294 | ||
496dbcd1 PM |
1295 | static void arm_gic_class_init(ObjectClass *klass, void *data) |
1296 | { | |
1297 | DeviceClass *dc = DEVICE_CLASS(klass); | |
1e8cae4d | 1298 | ARMGICClass *agc = ARM_GIC_CLASS(klass); |
53111180 | 1299 | |
53111180 PM |
1300 | agc->parent_realize = dc->realize; |
1301 | dc->realize = arm_gic_realize; | |
496dbcd1 PM |
1302 | } |
1303 | ||
8c43a6f0 | 1304 | static const TypeInfo arm_gic_info = { |
1e8cae4d PM |
1305 | .name = TYPE_ARM_GIC, |
1306 | .parent = TYPE_ARM_GIC_COMMON, | |
fae15286 | 1307 | .instance_size = sizeof(GICState), |
496dbcd1 | 1308 | .class_init = arm_gic_class_init, |
998a74bc | 1309 | .class_size = sizeof(ARMGICClass), |
496dbcd1 PM |
1310 | }; |
1311 | ||
1312 | static void arm_gic_register_types(void) | |
1313 | { | |
1314 | type_register_static(&arm_gic_info); | |
1315 | } | |
1316 | ||
1317 | type_init(arm_gic_register_types) |