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Commit | Line | Data |
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1e8cae4d PM |
1 | /* |
2 | * ARM GIC support - common bits of emulated and KVM kernel model | |
3 | * | |
4 | * Copyright (c) 2012 Linaro Limited | |
5 | * Written by Peter Maydell | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation, either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along | |
18 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
20 | ||
8ef94f0b | 21 | #include "qemu/osdep.h" |
da34e65c | 22 | #include "qapi/error.h" |
0b8fa32f | 23 | #include "qemu/module.h" |
47b43a1f | 24 | #include "gic_internal.h" |
8ff41f39 | 25 | #include "hw/arm/linux-boot-if.h" |
1e8cae4d | 26 | |
44b1ff31 | 27 | static int gic_pre_save(void *opaque) |
1e8cae4d | 28 | { |
fae15286 | 29 | GICState *s = (GICState *)opaque; |
9ecb9926 | 30 | ARMGICCommonClass *c = ARM_GIC_COMMON_GET_CLASS(s); |
1e8cae4d | 31 | |
9ecb9926 PM |
32 | if (c->pre_save) { |
33 | c->pre_save(s); | |
34 | } | |
44b1ff31 DDAG |
35 | |
36 | return 0; | |
1e8cae4d PM |
37 | } |
38 | ||
2e19a703 | 39 | static int gic_post_load(void *opaque, int version_id) |
1e8cae4d | 40 | { |
fae15286 | 41 | GICState *s = (GICState *)opaque; |
9ecb9926 | 42 | ARMGICCommonClass *c = ARM_GIC_COMMON_GET_CLASS(s); |
1e8cae4d | 43 | |
9ecb9926 PM |
44 | if (c->post_load) { |
45 | c->post_load(s); | |
46 | } | |
1e8cae4d PM |
47 | return 0; |
48 | } | |
49 | ||
5773c049 LM |
50 | static bool gic_virt_state_needed(void *opaque) |
51 | { | |
52 | GICState *s = (GICState *)opaque; | |
53 | ||
54 | return s->virt_extn; | |
55 | } | |
56 | ||
2e19a703 PM |
57 | static const VMStateDescription vmstate_gic_irq_state = { |
58 | .name = "arm_gic_irq_state", | |
59 | .version_id = 1, | |
60 | .minimum_version_id = 1, | |
61 | .fields = (VMStateField[]) { | |
62 | VMSTATE_UINT8(enabled, gic_irq_state), | |
63 | VMSTATE_UINT8(pending, gic_irq_state), | |
64 | VMSTATE_UINT8(active, gic_irq_state), | |
65 | VMSTATE_UINT8(level, gic_irq_state), | |
66 | VMSTATE_BOOL(model, gic_irq_state), | |
04050c5c | 67 | VMSTATE_BOOL(edge_trigger, gic_irq_state), |
c27a5ba9 | 68 | VMSTATE_UINT8(group, gic_irq_state), |
2e19a703 PM |
69 | VMSTATE_END_OF_LIST() |
70 | } | |
71 | }; | |
72 | ||
5773c049 LM |
73 | static const VMStateDescription vmstate_gic_virt_state = { |
74 | .name = "arm_gic_virt_state", | |
75 | .version_id = 1, | |
76 | .minimum_version_id = 1, | |
77 | .needed = gic_virt_state_needed, | |
78 | .fields = (VMStateField[]) { | |
79 | /* Virtual interface */ | |
80 | VMSTATE_UINT32_ARRAY(h_hcr, GICState, GIC_NCPU), | |
81 | VMSTATE_UINT32_ARRAY(h_misr, GICState, GIC_NCPU), | |
82 | VMSTATE_UINT32_2DARRAY(h_lr, GICState, GIC_MAX_LR, GIC_NCPU), | |
83 | VMSTATE_UINT32_ARRAY(h_apr, GICState, GIC_NCPU), | |
84 | ||
85 | /* Virtual CPU interfaces */ | |
86 | VMSTATE_UINT32_SUB_ARRAY(cpu_ctlr, GICState, GIC_NCPU, GIC_NCPU), | |
87 | VMSTATE_UINT16_SUB_ARRAY(priority_mask, GICState, GIC_NCPU, GIC_NCPU), | |
88 | VMSTATE_UINT16_SUB_ARRAY(running_priority, GICState, GIC_NCPU, GIC_NCPU), | |
89 | VMSTATE_UINT16_SUB_ARRAY(current_pending, GICState, GIC_NCPU, GIC_NCPU), | |
90 | VMSTATE_UINT8_SUB_ARRAY(bpr, GICState, GIC_NCPU, GIC_NCPU), | |
91 | VMSTATE_UINT8_SUB_ARRAY(abpr, GICState, GIC_NCPU, GIC_NCPU), | |
92 | ||
93 | VMSTATE_END_OF_LIST() | |
94 | } | |
95 | }; | |
96 | ||
2e19a703 PM |
97 | static const VMStateDescription vmstate_gic = { |
98 | .name = "arm_gic", | |
72889c8a PM |
99 | .version_id = 12, |
100 | .minimum_version_id = 12, | |
2e19a703 PM |
101 | .pre_save = gic_pre_save, |
102 | .post_load = gic_post_load, | |
103 | .fields = (VMStateField[]) { | |
679aa175 | 104 | VMSTATE_UINT32(ctlr, GICState), |
5773c049 | 105 | VMSTATE_UINT32_SUB_ARRAY(cpu_ctlr, GICState, 0, GIC_NCPU), |
2e19a703 PM |
106 | VMSTATE_STRUCT_ARRAY(irq_state, GICState, GIC_MAXIRQ, 1, |
107 | vmstate_gic_irq_state, gic_irq_state), | |
108 | VMSTATE_UINT8_ARRAY(irq_target, GICState, GIC_MAXIRQ), | |
83728796 | 109 | VMSTATE_UINT8_2DARRAY(priority1, GICState, GIC_INTERNAL, GIC_NCPU), |
2e19a703 | 110 | VMSTATE_UINT8_ARRAY(priority2, GICState, GIC_MAXIRQ - GIC_INTERNAL), |
40d22500 | 111 | VMSTATE_UINT8_2DARRAY(sgi_pending, GICState, GIC_NR_SGIS, GIC_NCPU), |
5773c049 LM |
112 | VMSTATE_UINT16_SUB_ARRAY(priority_mask, GICState, 0, GIC_NCPU), |
113 | VMSTATE_UINT16_SUB_ARRAY(running_priority, GICState, 0, GIC_NCPU), | |
114 | VMSTATE_UINT16_SUB_ARRAY(current_pending, GICState, 0, GIC_NCPU), | |
115 | VMSTATE_UINT8_SUB_ARRAY(bpr, GICState, 0, GIC_NCPU), | |
116 | VMSTATE_UINT8_SUB_ARRAY(abpr, GICState, 0, GIC_NCPU), | |
a9d477c4 | 117 | VMSTATE_UINT32_2DARRAY(apr, GICState, GIC_NR_APRS, GIC_NCPU), |
51fd06e0 | 118 | VMSTATE_UINT32_2DARRAY(nsapr, GICState, GIC_NR_APRS, GIC_NCPU), |
2e19a703 | 119 | VMSTATE_END_OF_LIST() |
5773c049 LM |
120 | }, |
121 | .subsections = (const VMStateDescription * []) { | |
122 | &vmstate_gic_virt_state, | |
123 | NULL | |
2e19a703 PM |
124 | } |
125 | }; | |
126 | ||
7926c210 | 127 | void gic_init_irqs_and_mmio(GICState *s, qemu_irq_handler handler, |
5773c049 LM |
128 | const MemoryRegionOps *ops, |
129 | const MemoryRegionOps *virt_ops) | |
7926c210 PF |
130 | { |
131 | SysBusDevice *sbd = SYS_BUS_DEVICE(s); | |
132 | int i = s->num_irq - GIC_INTERNAL; | |
133 | ||
134 | /* For the GIC, also expose incoming GPIO lines for PPIs for each CPU. | |
135 | * GPIO array layout is thus: | |
136 | * [0..N-1] SPIs | |
137 | * [N..N+31] PPIs for CPU 0 | |
138 | * [N+32..N+63] PPIs for CPU 1 | |
139 | * ... | |
140 | */ | |
7c14b3ac | 141 | i += (GIC_INTERNAL * s->num_cpu); |
7926c210 PF |
142 | qdev_init_gpio_in(DEVICE(s), handler, i); |
143 | ||
144 | for (i = 0; i < s->num_cpu; i++) { | |
145 | sysbus_init_irq(sbd, &s->parent_irq[i]); | |
146 | } | |
147 | for (i = 0; i < s->num_cpu; i++) { | |
148 | sysbus_init_irq(sbd, &s->parent_fiq[i]); | |
149 | } | |
6a228959 PM |
150 | for (i = 0; i < s->num_cpu; i++) { |
151 | sysbus_init_irq(sbd, &s->parent_virq[i]); | |
152 | } | |
153 | for (i = 0; i < s->num_cpu; i++) { | |
154 | sysbus_init_irq(sbd, &s->parent_vfiq[i]); | |
155 | } | |
5773c049 LM |
156 | if (s->virt_extn) { |
157 | for (i = 0; i < s->num_cpu; i++) { | |
158 | sysbus_init_irq(sbd, &s->maintenance_irq[i]); | |
159 | } | |
160 | } | |
7926c210 PF |
161 | |
162 | /* Distributor */ | |
163 | memory_region_init_io(&s->iomem, OBJECT(s), ops, s, "gic_dist", 0x1000); | |
164 | sysbus_init_mmio(sbd, &s->iomem); | |
165 | ||
7c14b3ac MD |
166 | /* This is the main CPU interface "for this core". It is always |
167 | * present because it is required by both software emulation and KVM. | |
168 | */ | |
169 | memory_region_init_io(&s->cpuiomem[0], OBJECT(s), ops ? &ops[1] : NULL, | |
170 | s, "gic_cpu", s->revision == 2 ? 0x2000 : 0x100); | |
171 | sysbus_init_mmio(sbd, &s->cpuiomem[0]); | |
5773c049 LM |
172 | |
173 | if (s->virt_extn) { | |
174 | memory_region_init_io(&s->vifaceiomem[0], OBJECT(s), virt_ops, | |
175 | s, "gic_viface", 0x1000); | |
176 | sysbus_init_mmio(sbd, &s->vifaceiomem[0]); | |
177 | ||
178 | memory_region_init_io(&s->vcpuiomem, OBJECT(s), | |
179 | virt_ops ? &virt_ops[1] : NULL, | |
180 | s, "gic_vcpu", 0x2000); | |
181 | sysbus_init_mmio(sbd, &s->vcpuiomem); | |
182 | } | |
7926c210 PF |
183 | } |
184 | ||
53111180 | 185 | static void arm_gic_common_realize(DeviceState *dev, Error **errp) |
1e8cae4d | 186 | { |
53111180 | 187 | GICState *s = ARM_GIC_COMMON(dev); |
1e8cae4d PM |
188 | int num_irq = s->num_irq; |
189 | ||
83728796 | 190 | if (s->num_cpu > GIC_NCPU) { |
53111180 | 191 | error_setg(errp, "requested %u CPUs exceeds GIC maximum %d", |
83728796 | 192 | s->num_cpu, GIC_NCPU); |
53111180 | 193 | return; |
1e8cae4d | 194 | } |
1e8cae4d | 195 | if (s->num_irq > GIC_MAXIRQ) { |
53111180 PM |
196 | error_setg(errp, |
197 | "requested %u interrupt lines exceeds GIC maximum %d", | |
198 | num_irq, GIC_MAXIRQ); | |
199 | return; | |
1e8cae4d PM |
200 | } |
201 | /* ITLinesNumber is represented as (N / 32) - 1 (see | |
202 | * gic_dist_readb) so this is an implementation imposed | |
203 | * restriction, not an architectural one: | |
204 | */ | |
205 | if (s->num_irq < 32 || (s->num_irq % 32)) { | |
53111180 PM |
206 | error_setg(errp, |
207 | "%d interrupt lines unsupported: not divisible by 32", | |
208 | num_irq); | |
209 | return; | |
1e8cae4d | 210 | } |
5543d1ab FA |
211 | |
212 | if (s->security_extn && | |
7c14b3ac | 213 | (s->revision == REV_11MPCORE)) { |
5543d1ab FA |
214 | error_setg(errp, "this GIC revision does not implement " |
215 | "the security extensions"); | |
216 | return; | |
217 | } | |
5773c049 LM |
218 | |
219 | if (s->virt_extn) { | |
220 | if (s->revision != 2) { | |
221 | error_setg(errp, "GIC virtualization extensions are only " | |
222 | "supported by revision 2"); | |
223 | return; | |
224 | } | |
225 | ||
226 | /* For now, set the number of implemented LRs to 4, as found in most | |
227 | * real GICv2. This could be promoted as a QOM property if we need to | |
228 | * emulate a variant with another num_lrs. | |
229 | */ | |
230 | s->num_lrs = 4; | |
231 | } | |
232 | } | |
233 | ||
234 | static inline void arm_gic_common_reset_irq_state(GICState *s, int first_cpu, | |
235 | int resetprio) | |
236 | { | |
237 | int i, j; | |
238 | ||
239 | for (i = first_cpu; i < first_cpu + s->num_cpu; i++) { | |
240 | if (s->revision == REV_11MPCORE) { | |
241 | s->priority_mask[i] = 0xf0; | |
242 | } else { | |
243 | s->priority_mask[i] = resetprio; | |
244 | } | |
245 | s->current_pending[i] = 1023; | |
246 | s->running_priority[i] = 0x100; | |
247 | s->cpu_ctlr[i] = 0; | |
248 | s->bpr[i] = gic_is_vcpu(i) ? GIC_VIRT_MIN_BPR : GIC_MIN_BPR; | |
249 | s->abpr[i] = gic_is_vcpu(i) ? GIC_VIRT_MIN_ABPR : GIC_MIN_ABPR; | |
250 | ||
251 | if (!gic_is_vcpu(i)) { | |
252 | for (j = 0; j < GIC_INTERNAL; j++) { | |
253 | s->priority1[j][i] = resetprio; | |
254 | } | |
255 | for (j = 0; j < GIC_NR_SGIS; j++) { | |
256 | s->sgi_pending[j][i] = 0; | |
257 | } | |
258 | } | |
259 | } | |
1e8cae4d PM |
260 | } |
261 | ||
262 | static void arm_gic_common_reset(DeviceState *dev) | |
263 | { | |
285b4432 | 264 | GICState *s = ARM_GIC_COMMON(dev); |
12dc273e | 265 | int i, j; |
8ff41f39 PM |
266 | int resetprio; |
267 | ||
268 | /* If we're resetting a TZ-aware GIC as if secure firmware | |
269 | * had set it up ready to start a kernel in non-secure, | |
270 | * we need to set interrupt priorities to a "zero for the | |
271 | * NS view" value. This is particularly critical for the | |
272 | * priority_mask[] values, because if they are zero then NS | |
273 | * code cannot ever rewrite the priority to anything else. | |
274 | */ | |
275 | if (s->security_extn && s->irq_reset_nonsecure) { | |
276 | resetprio = 0x80; | |
277 | } else { | |
278 | resetprio = 0; | |
279 | } | |
280 | ||
1e8cae4d | 281 | memset(s->irq_state, 0, GIC_MAXIRQ * sizeof(gic_irq_state)); |
5773c049 LM |
282 | arm_gic_common_reset_irq_state(s, 0, resetprio); |
283 | ||
284 | if (s->virt_extn) { | |
285 | /* vCPU states are stored at indexes GIC_NCPU .. GIC_NCPU+num_cpu. | |
286 | * The exposed vCPU interface does not have security extensions. | |
287 | */ | |
288 | arm_gic_common_reset_irq_state(s, GIC_NCPU, 0); | |
1e8cae4d | 289 | } |
5773c049 | 290 | |
93b5f6f1 | 291 | for (i = 0; i < GIC_NR_SGIS; i++) { |
67ce697a LM |
292 | GIC_DIST_SET_ENABLED(i, ALL_CPU_MASK); |
293 | GIC_DIST_SET_EDGE_TRIGGER(i); | |
1e8cae4d | 294 | } |
12dc273e PM |
295 | |
296 | for (i = 0; i < ARRAY_SIZE(s->priority2); i++) { | |
8ff41f39 | 297 | s->priority2[i] = resetprio; |
12dc273e PM |
298 | } |
299 | ||
300 | for (i = 0; i < GIC_MAXIRQ; i++) { | |
1e8cae4d | 301 | /* For uniprocessor GICs all interrupts always target the sole CPU */ |
12dc273e | 302 | if (s->num_cpu == 1) { |
1e8cae4d | 303 | s->irq_target[i] = 1; |
12dc273e PM |
304 | } else { |
305 | s->irq_target[i] = 0; | |
1e8cae4d PM |
306 | } |
307 | } | |
8ff41f39 PM |
308 | if (s->security_extn && s->irq_reset_nonsecure) { |
309 | for (i = 0; i < GIC_MAXIRQ; i++) { | |
67ce697a | 310 | GIC_DIST_SET_GROUP(i, ALL_CPU_MASK); |
8ff41f39 PM |
311 | } |
312 | } | |
313 | ||
5773c049 LM |
314 | if (s->virt_extn) { |
315 | for (i = 0; i < s->num_lrs; i++) { | |
316 | for (j = 0; j < s->num_cpu; j++) { | |
317 | s->h_lr[i][j] = 0; | |
318 | } | |
319 | } | |
320 | ||
321 | for (i = 0; i < s->num_cpu; i++) { | |
322 | s->h_hcr[i] = 0; | |
323 | s->h_misr[i] = 0; | |
324 | } | |
325 | } | |
326 | ||
679aa175 | 327 | s->ctlr = 0; |
1e8cae4d PM |
328 | } |
329 | ||
8ff41f39 PM |
330 | static void arm_gic_common_linux_init(ARMLinuxBootIf *obj, |
331 | bool secure_boot) | |
332 | { | |
333 | GICState *s = ARM_GIC_COMMON(obj); | |
334 | ||
335 | if (s->security_extn && !secure_boot) { | |
336 | /* We're directly booting a kernel into NonSecure. If this GIC | |
337 | * implements the security extensions then we must configure it | |
338 | * to have all the interrupts be NonSecure (this is a job that | |
339 | * is done by the Secure boot firmware in real hardware, and in | |
340 | * this mode QEMU is acting as a minimalist firmware-and-bootloader | |
341 | * equivalent). | |
342 | */ | |
343 | s->irq_reset_nonsecure = true; | |
344 | } | |
345 | } | |
346 | ||
1e8cae4d | 347 | static Property arm_gic_common_properties[] = { |
fae15286 PM |
348 | DEFINE_PROP_UINT32("num-cpu", GICState, num_cpu, 1), |
349 | DEFINE_PROP_UINT32("num-irq", GICState, num_irq, 32), | |
1e8cae4d PM |
350 | /* Revision can be 1 or 2 for GIC architecture specification |
351 | * versions 1 or 2, or 0 to indicate the legacy 11MPCore GIC. | |
1e8cae4d | 352 | */ |
fae15286 | 353 | DEFINE_PROP_UINT32("revision", GICState, revision, 1), |
5543d1ab FA |
354 | /* True if the GIC should implement the security extensions */ |
355 | DEFINE_PROP_BOOL("has-security-extensions", GICState, security_extn, 0), | |
5773c049 LM |
356 | /* True if the GIC should implement the virtualization extensions */ |
357 | DEFINE_PROP_BOOL("has-virtualization-extensions", GICState, virt_extn, 0), | |
1e8cae4d PM |
358 | DEFINE_PROP_END_OF_LIST(), |
359 | }; | |
360 | ||
361 | static void arm_gic_common_class_init(ObjectClass *klass, void *data) | |
362 | { | |
1e8cae4d | 363 | DeviceClass *dc = DEVICE_CLASS(klass); |
8ff41f39 | 364 | ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_CLASS(klass); |
53111180 | 365 | |
1e8cae4d | 366 | dc->reset = arm_gic_common_reset; |
53111180 | 367 | dc->realize = arm_gic_common_realize; |
1e8cae4d | 368 | dc->props = arm_gic_common_properties; |
2e19a703 | 369 | dc->vmsd = &vmstate_gic; |
8ff41f39 | 370 | albifc->arm_linux_init = arm_gic_common_linux_init; |
1e8cae4d PM |
371 | } |
372 | ||
8c43a6f0 | 373 | static const TypeInfo arm_gic_common_type = { |
1e8cae4d PM |
374 | .name = TYPE_ARM_GIC_COMMON, |
375 | .parent = TYPE_SYS_BUS_DEVICE, | |
fae15286 | 376 | .instance_size = sizeof(GICState), |
1e8cae4d PM |
377 | .class_size = sizeof(ARMGICCommonClass), |
378 | .class_init = arm_gic_common_class_init, | |
379 | .abstract = true, | |
8ff41f39 PM |
380 | .interfaces = (InterfaceInfo []) { |
381 | { TYPE_ARM_LINUX_BOOT_IF }, | |
382 | { }, | |
383 | }, | |
1e8cae4d PM |
384 | }; |
385 | ||
386 | static void register_types(void) | |
387 | { | |
388 | type_register_static(&arm_gic_common_type); | |
389 | } | |
390 | ||
391 | type_init(register_types) |