]>
Commit | Line | Data |
---|---|---|
ed466761 PM |
1 | /* |
2 | * ARM Generic Interrupt Controller using KVM in-kernel support | |
3 | * | |
4 | * Copyright (c) 2012 Linaro Limited | |
5 | * Written by Peter Maydell | |
855011be | 6 | * Save/Restore logic added by Christoffer Dall. |
ed466761 PM |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License along | |
19 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
8ef94f0b | 22 | #include "qemu/osdep.h" |
da34e65c | 23 | #include "qapi/error.h" |
33c11879 PB |
24 | #include "qemu-common.h" |
25 | #include "cpu.h" | |
ed466761 | 26 | #include "hw/sysbus.h" |
795c40b8 | 27 | #include "migration/blocker.h" |
ed466761 PM |
28 | #include "sysemu/kvm.h" |
29 | #include "kvm_arm.h" | |
47b43a1f | 30 | #include "gic_internal.h" |
4b3cfe72 | 31 | #include "vgic_common.h" |
ed466761 PM |
32 | |
33 | #define TYPE_KVM_ARM_GIC "kvm-arm-gic" | |
34 | #define KVM_ARM_GIC(obj) \ | |
35 | OBJECT_CHECK(GICState, (obj), TYPE_KVM_ARM_GIC) | |
36 | #define KVM_ARM_GIC_CLASS(klass) \ | |
37 | OBJECT_CLASS_CHECK(KVMARMGICClass, (klass), TYPE_KVM_ARM_GIC) | |
38 | #define KVM_ARM_GIC_GET_CLASS(obj) \ | |
39 | OBJECT_GET_CLASS(KVMARMGICClass, (obj), TYPE_KVM_ARM_GIC) | |
40 | ||
41 | typedef struct KVMARMGICClass { | |
42 | ARMGICCommonClass parent_class; | |
43 | DeviceRealize parent_realize; | |
44 | void (*parent_reset)(DeviceState *dev); | |
45 | } KVMARMGICClass; | |
46 | ||
4b3cfe72 | 47 | void kvm_arm_gic_set_irq(uint32_t num_irq, int irq, int level) |
ed466761 PM |
48 | { |
49 | /* Meaning of the 'irq' parameter: | |
50 | * [0..N-1] : external interrupts | |
51 | * [N..N+31] : PPI (internal) interrupts for CPU 0 | |
52 | * [N+32..N+63] : PPI (internal interrupts for CPU 1 | |
53 | * ... | |
54 | * Convert this to the kernel's desired encoding, which | |
55 | * has separate fields in the irq number for type, | |
56 | * CPU number and interrupt number. | |
57 | */ | |
ed466761 PM |
58 | int kvm_irq, irqtype, cpu; |
59 | ||
4b3cfe72 | 60 | if (irq < (num_irq - GIC_INTERNAL)) { |
ed466761 PM |
61 | /* External interrupt. The kernel numbers these like the GIC |
62 | * hardware, with external interrupt IDs starting after the | |
63 | * internal ones. | |
64 | */ | |
65 | irqtype = KVM_ARM_IRQ_TYPE_SPI; | |
66 | cpu = 0; | |
67 | irq += GIC_INTERNAL; | |
68 | } else { | |
69 | /* Internal interrupt: decode into (cpu, interrupt id) */ | |
70 | irqtype = KVM_ARM_IRQ_TYPE_PPI; | |
4b3cfe72 | 71 | irq -= (num_irq - GIC_INTERNAL); |
ed466761 PM |
72 | cpu = irq / GIC_INTERNAL; |
73 | irq %= GIC_INTERNAL; | |
74 | } | |
75 | kvm_irq = (irqtype << KVM_ARM_IRQ_TYPE_SHIFT) | |
76 | | (cpu << KVM_ARM_IRQ_VCPU_SHIFT) | irq; | |
77 | ||
78 | kvm_set_irq(kvm_state, kvm_irq, !!level); | |
79 | } | |
80 | ||
4b3cfe72 | 81 | static void kvm_arm_gicv2_set_irq(void *opaque, int irq, int level) |
72149414 | 82 | { |
4b3cfe72 | 83 | GICState *s = (GICState *)opaque; |
72149414 | 84 | |
4b3cfe72 | 85 | kvm_arm_gic_set_irq(s->num_irq, irq, level); |
72149414 PM |
86 | } |
87 | ||
4b3cfe72 | 88 | static bool kvm_arm_gic_can_save_restore(GICState *s) |
855011be | 89 | { |
4b3cfe72 | 90 | return s->dev_fd >= 0; |
855011be CD |
91 | } |
92 | ||
4b3cfe72 PF |
93 | #define KVM_VGIC_ATTR(offset, cpu) \ |
94 | ((((uint64_t)(cpu) << KVM_DEV_ARM_VGIC_CPUID_SHIFT) & \ | |
95 | KVM_DEV_ARM_VGIC_CPUID_MASK) | \ | |
96 | (((uint64_t)(offset) << KVM_DEV_ARM_VGIC_OFFSET_SHIFT) & \ | |
97 | KVM_DEV_ARM_VGIC_OFFSET_MASK)) | |
98 | ||
855011be CD |
99 | static void kvm_gicd_access(GICState *s, int offset, int cpu, |
100 | uint32_t *val, bool write) | |
101 | { | |
4b3cfe72 | 102 | kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_DIST_REGS, |
556969e9 | 103 | KVM_VGIC_ATTR(offset, cpu), val, write, &error_abort); |
855011be CD |
104 | } |
105 | ||
106 | static void kvm_gicc_access(GICState *s, int offset, int cpu, | |
107 | uint32_t *val, bool write) | |
108 | { | |
4b3cfe72 | 109 | kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_REGS, |
556969e9 | 110 | KVM_VGIC_ATTR(offset, cpu), val, write, &error_abort); |
855011be CD |
111 | } |
112 | ||
113 | #define for_each_irq_reg(_ctr, _max_irq, _field_width) \ | |
114 | for (_ctr = 0; _ctr < ((_max_irq) / (32 / (_field_width))); _ctr++) | |
115 | ||
116 | /* | |
117 | * Translate from the in-kernel field for an IRQ value to/from the qemu | |
118 | * representation. | |
119 | */ | |
120 | typedef void (*vgic_translate_fn)(GICState *s, int irq, int cpu, | |
121 | uint32_t *field, bool to_kernel); | |
122 | ||
123 | /* synthetic translate function used for clear/set registers to completely | |
3b163b01 | 124 | * clear a setting using a clear-register before setting the remaining bits |
855011be CD |
125 | * using a set-register */ |
126 | static void translate_clear(GICState *s, int irq, int cpu, | |
127 | uint32_t *field, bool to_kernel) | |
128 | { | |
129 | if (to_kernel) { | |
130 | *field = ~0; | |
131 | } else { | |
132 | /* does not make sense: qemu model doesn't use set/clear regs */ | |
133 | abort(); | |
134 | } | |
135 | } | |
136 | ||
eb8b9530 PM |
137 | static void translate_group(GICState *s, int irq, int cpu, |
138 | uint32_t *field, bool to_kernel) | |
139 | { | |
140 | int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; | |
141 | ||
142 | if (to_kernel) { | |
67ce697a | 143 | *field = GIC_DIST_TEST_GROUP(irq, cm); |
eb8b9530 PM |
144 | } else { |
145 | if (*field & 1) { | |
67ce697a | 146 | GIC_DIST_SET_GROUP(irq, cm); |
eb8b9530 PM |
147 | } |
148 | } | |
149 | } | |
150 | ||
855011be CD |
151 | static void translate_enabled(GICState *s, int irq, int cpu, |
152 | uint32_t *field, bool to_kernel) | |
153 | { | |
154 | int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; | |
155 | ||
156 | if (to_kernel) { | |
67ce697a | 157 | *field = GIC_DIST_TEST_ENABLED(irq, cm); |
855011be CD |
158 | } else { |
159 | if (*field & 1) { | |
67ce697a | 160 | GIC_DIST_SET_ENABLED(irq, cm); |
855011be CD |
161 | } |
162 | } | |
163 | } | |
164 | ||
165 | static void translate_pending(GICState *s, int irq, int cpu, | |
166 | uint32_t *field, bool to_kernel) | |
167 | { | |
168 | int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; | |
169 | ||
170 | if (to_kernel) { | |
171 | *field = gic_test_pending(s, irq, cm); | |
172 | } else { | |
173 | if (*field & 1) { | |
67ce697a | 174 | GIC_DIST_SET_PENDING(irq, cm); |
855011be CD |
175 | /* TODO: Capture is level-line is held high in the kernel */ |
176 | } | |
177 | } | |
178 | } | |
179 | ||
180 | static void translate_active(GICState *s, int irq, int cpu, | |
181 | uint32_t *field, bool to_kernel) | |
182 | { | |
183 | int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; | |
184 | ||
185 | if (to_kernel) { | |
67ce697a | 186 | *field = GIC_DIST_TEST_ACTIVE(irq, cm); |
855011be CD |
187 | } else { |
188 | if (*field & 1) { | |
67ce697a | 189 | GIC_DIST_SET_ACTIVE(irq, cm); |
855011be CD |
190 | } |
191 | } | |
192 | } | |
193 | ||
194 | static void translate_trigger(GICState *s, int irq, int cpu, | |
195 | uint32_t *field, bool to_kernel) | |
196 | { | |
197 | if (to_kernel) { | |
67ce697a | 198 | *field = (GIC_DIST_TEST_EDGE_TRIGGER(irq)) ? 0x2 : 0x0; |
855011be CD |
199 | } else { |
200 | if (*field & 0x2) { | |
67ce697a | 201 | GIC_DIST_SET_EDGE_TRIGGER(irq); |
855011be CD |
202 | } |
203 | } | |
204 | } | |
205 | ||
206 | static void translate_priority(GICState *s, int irq, int cpu, | |
207 | uint32_t *field, bool to_kernel) | |
208 | { | |
209 | if (to_kernel) { | |
67ce697a | 210 | *field = GIC_DIST_GET_PRIORITY(irq, cpu) & 0xff; |
855011be | 211 | } else { |
67ce697a LM |
212 | gic_dist_set_priority(s, cpu, irq, |
213 | *field & 0xff, MEMTXATTRS_UNSPECIFIED); | |
855011be CD |
214 | } |
215 | } | |
216 | ||
217 | static void translate_targets(GICState *s, int irq, int cpu, | |
218 | uint32_t *field, bool to_kernel) | |
219 | { | |
220 | if (to_kernel) { | |
221 | *field = s->irq_target[irq] & 0xff; | |
222 | } else { | |
223 | s->irq_target[irq] = *field & 0xff; | |
224 | } | |
225 | } | |
226 | ||
227 | static void translate_sgisource(GICState *s, int irq, int cpu, | |
228 | uint32_t *field, bool to_kernel) | |
229 | { | |
230 | if (to_kernel) { | |
231 | *field = s->sgi_pending[irq][cpu] & 0xff; | |
232 | } else { | |
233 | s->sgi_pending[irq][cpu] = *field & 0xff; | |
234 | } | |
235 | } | |
236 | ||
237 | /* Read a register group from the kernel VGIC */ | |
238 | static void kvm_dist_get(GICState *s, uint32_t offset, int width, | |
239 | int maxirq, vgic_translate_fn translate_fn) | |
240 | { | |
241 | uint32_t reg; | |
242 | int i; | |
243 | int j; | |
244 | int irq; | |
245 | int cpu; | |
246 | int regsz = 32 / width; /* irqs per kernel register */ | |
247 | uint32_t field; | |
248 | ||
249 | for_each_irq_reg(i, maxirq, width) { | |
250 | irq = i * regsz; | |
251 | cpu = 0; | |
252 | while ((cpu < s->num_cpu && irq < GIC_INTERNAL) || cpu == 0) { | |
253 | kvm_gicd_access(s, offset, cpu, ®, false); | |
254 | for (j = 0; j < regsz; j++) { | |
255 | field = extract32(reg, j * width, width); | |
256 | translate_fn(s, irq + j, cpu, &field, false); | |
257 | } | |
258 | ||
259 | cpu++; | |
260 | } | |
261 | offset += 4; | |
262 | } | |
263 | } | |
264 | ||
265 | /* Write a register group to the kernel VGIC */ | |
266 | static void kvm_dist_put(GICState *s, uint32_t offset, int width, | |
267 | int maxirq, vgic_translate_fn translate_fn) | |
268 | { | |
269 | uint32_t reg; | |
270 | int i; | |
271 | int j; | |
272 | int irq; | |
273 | int cpu; | |
274 | int regsz = 32 / width; /* irqs per kernel register */ | |
275 | uint32_t field; | |
276 | ||
277 | for_each_irq_reg(i, maxirq, width) { | |
278 | irq = i * regsz; | |
279 | cpu = 0; | |
280 | while ((cpu < s->num_cpu && irq < GIC_INTERNAL) || cpu == 0) { | |
281 | reg = 0; | |
282 | for (j = 0; j < regsz; j++) { | |
283 | translate_fn(s, irq + j, cpu, &field, true); | |
284 | reg = deposit32(reg, j * width, width, field); | |
285 | } | |
286 | kvm_gicd_access(s, offset, cpu, ®, true); | |
287 | ||
288 | cpu++; | |
289 | } | |
290 | offset += 4; | |
291 | } | |
292 | } | |
293 | ||
ed466761 PM |
294 | static void kvm_arm_gic_put(GICState *s) |
295 | { | |
855011be CD |
296 | uint32_t reg; |
297 | int i; | |
298 | int cpu; | |
299 | int num_cpu; | |
300 | int num_irq; | |
301 | ||
855011be CD |
302 | /* Note: We do the restore in a slightly different order than the save |
303 | * (where the order doesn't matter and is simply ordered according to the | |
304 | * register offset values */ | |
305 | ||
306 | /***************************************************************** | |
307 | * Distributor State | |
308 | */ | |
309 | ||
679aa175 FA |
310 | /* s->ctlr -> GICD_CTLR */ |
311 | reg = s->ctlr; | |
855011be CD |
312 | kvm_gicd_access(s, 0x0, 0, ®, true); |
313 | ||
314 | /* Sanity checking on GICD_TYPER and s->num_irq, s->num_cpu */ | |
315 | kvm_gicd_access(s, 0x4, 0, ®, false); | |
316 | num_irq = ((reg & 0x1f) + 1) * 32; | |
317 | num_cpu = ((reg & 0xe0) >> 5) + 1; | |
318 | ||
319 | if (num_irq < s->num_irq) { | |
320 | fprintf(stderr, "Restoring %u IRQs, but kernel supports max %d\n", | |
321 | s->num_irq, num_irq); | |
322 | abort(); | |
323 | } else if (num_cpu != s->num_cpu) { | |
324 | fprintf(stderr, "Restoring %u CPU interfaces, kernel only has %d\n", | |
325 | s->num_cpu, num_cpu); | |
326 | /* Did we not create the VCPUs in the kernel yet? */ | |
327 | abort(); | |
328 | } | |
329 | ||
330 | /* TODO: Consider checking compatibility with the IIDR ? */ | |
331 | ||
332 | /* irq_state[n].enabled -> GICD_ISENABLERn */ | |
333 | kvm_dist_put(s, 0x180, 1, s->num_irq, translate_clear); | |
334 | kvm_dist_put(s, 0x100, 1, s->num_irq, translate_enabled); | |
335 | ||
eb8b9530 PM |
336 | /* irq_state[n].group -> GICD_IGROUPRn */ |
337 | kvm_dist_put(s, 0x80, 1, s->num_irq, translate_group); | |
338 | ||
855011be CD |
339 | /* s->irq_target[irq] -> GICD_ITARGETSRn |
340 | * (restore targets before pending to ensure the pending state is set on | |
341 | * the appropriate CPU interfaces in the kernel) */ | |
342 | kvm_dist_put(s, 0x800, 8, s->num_irq, translate_targets); | |
343 | ||
74fdb781 AB |
344 | /* irq_state[n].trigger -> GICD_ICFGRn |
345 | * (restore configuration registers before pending IRQs so we treat | |
346 | * level/edge correctly) */ | |
347 | kvm_dist_put(s, 0xc00, 2, s->num_irq, translate_trigger); | |
348 | ||
855011be CD |
349 | /* irq_state[n].pending + irq_state[n].level -> GICD_ISPENDRn */ |
350 | kvm_dist_put(s, 0x280, 1, s->num_irq, translate_clear); | |
351 | kvm_dist_put(s, 0x200, 1, s->num_irq, translate_pending); | |
352 | ||
353 | /* irq_state[n].active -> GICD_ISACTIVERn */ | |
354 | kvm_dist_put(s, 0x380, 1, s->num_irq, translate_clear); | |
355 | kvm_dist_put(s, 0x300, 1, s->num_irq, translate_active); | |
356 | ||
855011be CD |
357 | |
358 | /* s->priorityX[irq] -> ICD_IPRIORITYRn */ | |
359 | kvm_dist_put(s, 0x400, 8, s->num_irq, translate_priority); | |
360 | ||
361 | /* s->sgi_pending -> ICD_CPENDSGIRn */ | |
362 | kvm_dist_put(s, 0xf10, 8, GIC_NR_SGIS, translate_clear); | |
363 | kvm_dist_put(s, 0xf20, 8, GIC_NR_SGIS, translate_sgisource); | |
364 | ||
365 | ||
366 | /***************************************************************** | |
367 | * CPU Interface(s) State | |
368 | */ | |
369 | ||
370 | for (cpu = 0; cpu < s->num_cpu; cpu++) { | |
32951860 FA |
371 | /* s->cpu_ctlr[cpu] -> GICC_CTLR */ |
372 | reg = s->cpu_ctlr[cpu]; | |
855011be CD |
373 | kvm_gicc_access(s, 0x00, cpu, ®, true); |
374 | ||
375 | /* s->priority_mask[cpu] -> GICC_PMR */ | |
376 | reg = (s->priority_mask[cpu] & 0xff); | |
377 | kvm_gicc_access(s, 0x04, cpu, ®, true); | |
378 | ||
379 | /* s->bpr[cpu] -> GICC_BPR */ | |
380 | reg = (s->bpr[cpu] & 0x7); | |
381 | kvm_gicc_access(s, 0x08, cpu, ®, true); | |
382 | ||
383 | /* s->abpr[cpu] -> GICC_ABPR */ | |
384 | reg = (s->abpr[cpu] & 0x7); | |
385 | kvm_gicc_access(s, 0x1c, cpu, ®, true); | |
386 | ||
387 | /* s->apr[n][cpu] -> GICC_APRn */ | |
388 | for (i = 0; i < 4; i++) { | |
389 | reg = s->apr[i][cpu]; | |
390 | kvm_gicc_access(s, 0xd0 + i * 4, cpu, ®, true); | |
391 | } | |
392 | } | |
ed466761 PM |
393 | } |
394 | ||
395 | static void kvm_arm_gic_get(GICState *s) | |
396 | { | |
855011be CD |
397 | uint32_t reg; |
398 | int i; | |
399 | int cpu; | |
400 | ||
855011be CD |
401 | /***************************************************************** |
402 | * Distributor State | |
403 | */ | |
404 | ||
679aa175 | 405 | /* GICD_CTLR -> s->ctlr */ |
855011be | 406 | kvm_gicd_access(s, 0x0, 0, ®, false); |
679aa175 | 407 | s->ctlr = reg; |
855011be CD |
408 | |
409 | /* Sanity checking on GICD_TYPER -> s->num_irq, s->num_cpu */ | |
410 | kvm_gicd_access(s, 0x4, 0, ®, false); | |
411 | s->num_irq = ((reg & 0x1f) + 1) * 32; | |
412 | s->num_cpu = ((reg & 0xe0) >> 5) + 1; | |
413 | ||
414 | if (s->num_irq > GIC_MAXIRQ) { | |
415 | fprintf(stderr, "Too many IRQs reported from the kernel: %d\n", | |
416 | s->num_irq); | |
417 | abort(); | |
418 | } | |
419 | ||
420 | /* GICD_IIDR -> ? */ | |
421 | kvm_gicd_access(s, 0x8, 0, ®, false); | |
422 | ||
855011be CD |
423 | /* Clear all the IRQ settings */ |
424 | for (i = 0; i < s->num_irq; i++) { | |
425 | memset(&s->irq_state[i], 0, sizeof(s->irq_state[0])); | |
426 | } | |
427 | ||
eb8b9530 PM |
428 | /* GICD_IGROUPRn -> irq_state[n].group */ |
429 | kvm_dist_get(s, 0x80, 1, s->num_irq, translate_group); | |
430 | ||
855011be CD |
431 | /* GICD_ISENABLERn -> irq_state[n].enabled */ |
432 | kvm_dist_get(s, 0x100, 1, s->num_irq, translate_enabled); | |
433 | ||
434 | /* GICD_ISPENDRn -> irq_state[n].pending + irq_state[n].level */ | |
435 | kvm_dist_get(s, 0x200, 1, s->num_irq, translate_pending); | |
436 | ||
437 | /* GICD_ISACTIVERn -> irq_state[n].active */ | |
438 | kvm_dist_get(s, 0x300, 1, s->num_irq, translate_active); | |
439 | ||
440 | /* GICD_ICFRn -> irq_state[n].trigger */ | |
441 | kvm_dist_get(s, 0xc00, 2, s->num_irq, translate_trigger); | |
442 | ||
443 | /* GICD_IPRIORITYRn -> s->priorityX[irq] */ | |
444 | kvm_dist_get(s, 0x400, 8, s->num_irq, translate_priority); | |
445 | ||
446 | /* GICD_ITARGETSRn -> s->irq_target[irq] */ | |
447 | kvm_dist_get(s, 0x800, 8, s->num_irq, translate_targets); | |
448 | ||
449 | /* GICD_CPENDSGIRn -> s->sgi_pending */ | |
450 | kvm_dist_get(s, 0xf10, 8, GIC_NR_SGIS, translate_sgisource); | |
451 | ||
452 | ||
453 | /***************************************************************** | |
454 | * CPU Interface(s) State | |
455 | */ | |
456 | ||
457 | for (cpu = 0; cpu < s->num_cpu; cpu++) { | |
32951860 | 458 | /* GICC_CTLR -> s->cpu_ctlr[cpu] */ |
855011be | 459 | kvm_gicc_access(s, 0x00, cpu, ®, false); |
32951860 | 460 | s->cpu_ctlr[cpu] = reg; |
855011be CD |
461 | |
462 | /* GICC_PMR -> s->priority_mask[cpu] */ | |
463 | kvm_gicc_access(s, 0x04, cpu, ®, false); | |
464 | s->priority_mask[cpu] = (reg & 0xff); | |
465 | ||
466 | /* GICC_BPR -> s->bpr[cpu] */ | |
467 | kvm_gicc_access(s, 0x08, cpu, ®, false); | |
468 | s->bpr[cpu] = (reg & 0x7); | |
469 | ||
470 | /* GICC_ABPR -> s->abpr[cpu] */ | |
471 | kvm_gicc_access(s, 0x1c, cpu, ®, false); | |
472 | s->abpr[cpu] = (reg & 0x7); | |
473 | ||
474 | /* GICC_APRn -> s->apr[n][cpu] */ | |
475 | for (i = 0; i < 4; i++) { | |
476 | kvm_gicc_access(s, 0xd0 + i * 4, cpu, ®, false); | |
477 | s->apr[i][cpu] = reg; | |
478 | } | |
479 | } | |
ed466761 PM |
480 | } |
481 | ||
482 | static void kvm_arm_gic_reset(DeviceState *dev) | |
483 | { | |
484 | GICState *s = ARM_GIC_COMMON(dev); | |
485 | KVMARMGICClass *kgc = KVM_ARM_GIC_GET_CLASS(s); | |
486 | ||
487 | kgc->parent_reset(dev); | |
24182fbc PF |
488 | |
489 | if (kvm_arm_gic_can_save_restore(s)) { | |
490 | kvm_arm_gic_put(s); | |
491 | } | |
ed466761 PM |
492 | } |
493 | ||
494 | static void kvm_arm_gic_realize(DeviceState *dev, Error **errp) | |
495 | { | |
496 | int i; | |
497 | GICState *s = KVM_ARM_GIC(dev); | |
ed466761 | 498 | KVMARMGICClass *kgc = KVM_ARM_GIC_GET_CLASS(s); |
0175ba10 | 499 | Error *local_err = NULL; |
1da41cc1 | 500 | int ret; |
ed466761 | 501 | |
0175ba10 MA |
502 | kgc->parent_realize(dev, &local_err); |
503 | if (local_err) { | |
504 | error_propagate(errp, local_err); | |
ed466761 PM |
505 | return; |
506 | } | |
507 | ||
5543d1ab FA |
508 | if (s->security_extn) { |
509 | error_setg(errp, "the in-kernel VGIC does not implement the " | |
510 | "security extensions"); | |
511 | return; | |
512 | } | |
513 | ||
5773c049 LM |
514 | if (s->virt_extn) { |
515 | error_setg(errp, "the in-kernel VGIC does not implement the " | |
516 | "virtualization extensions"); | |
517 | return; | |
518 | } | |
519 | ||
fe44dc91 AA |
520 | if (!kvm_arm_gic_can_save_restore(s)) { |
521 | error_setg(&s->migration_blocker, "This operating system kernel does " | |
522 | "not support vGICv2 migration"); | |
523 | migrate_add_blocker(s->migration_blocker, &local_err); | |
524 | if (local_err) { | |
525 | error_propagate(errp, local_err); | |
526 | error_free(s->migration_blocker); | |
527 | return; | |
528 | } | |
529 | } | |
530 | ||
5773c049 | 531 | gic_init_irqs_and_mmio(s, kvm_arm_gicv2_set_irq, NULL, NULL); |
6a1a9cfa EA |
532 | |
533 | for (i = 0; i < s->num_irq - GIC_INTERNAL; i++) { | |
534 | qemu_irq irq = qdev_get_gpio_in(dev, i); | |
535 | kvm_irqchip_set_qemuirq_gsi(kvm_state, irq, i); | |
536 | } | |
537 | ||
1da41cc1 CD |
538 | /* Try to create the device via the device control API */ |
539 | s->dev_fd = -1; | |
540 | ret = kvm_create_device(kvm_state, KVM_DEV_TYPE_ARM_VGIC_V2, false); | |
541 | if (ret >= 0) { | |
542 | s->dev_fd = ret; | |
4b3cfe72 PF |
543 | |
544 | /* Newstyle API is used, we may have attributes */ | |
545 | if (kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS, 0)) { | |
546 | uint32_t numirqs = s->num_irq; | |
547 | kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS, 0, | |
556969e9 | 548 | &numirqs, true, &error_abort); |
4b3cfe72 PF |
549 | } |
550 | /* Tell the kernel to complete VGIC initialization now */ | |
551 | if (kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, | |
552 | KVM_DEV_ARM_VGIC_CTRL_INIT)) { | |
553 | kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, | |
556969e9 EA |
554 | KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true, |
555 | &error_abort); | |
4b3cfe72 | 556 | } |
1da41cc1 CD |
557 | } else if (ret != -ENODEV && ret != -ENOTSUP) { |
558 | error_setg_errno(errp, -ret, "error creating in-kernel VGIC"); | |
559 | return; | |
560 | } | |
561 | ||
ed466761 | 562 | /* Distributor */ |
ed466761 PM |
563 | kvm_arm_register_device(&s->iomem, |
564 | (KVM_ARM_DEVICE_VGIC_V2 << KVM_ARM_DEVICE_ID_SHIFT) | |
1da41cc1 CD |
565 | | KVM_VGIC_V2_ADDR_TYPE_DIST, |
566 | KVM_DEV_ARM_VGIC_GRP_ADDR, | |
567 | KVM_VGIC_V2_ADDR_TYPE_DIST, | |
19d1bd0b | 568 | s->dev_fd, 0); |
ed466761 PM |
569 | /* CPU interface for current core. Unlike arm_gic, we don't |
570 | * provide the "interface for core #N" memory regions, because | |
571 | * cores with a VGIC don't have those. | |
572 | */ | |
ed466761 PM |
573 | kvm_arm_register_device(&s->cpuiomem[0], |
574 | (KVM_ARM_DEVICE_VGIC_V2 << KVM_ARM_DEVICE_ID_SHIFT) | |
1da41cc1 CD |
575 | | KVM_VGIC_V2_ADDR_TYPE_CPU, |
576 | KVM_DEV_ARM_VGIC_GRP_ADDR, | |
577 | KVM_VGIC_V2_ADDR_TYPE_CPU, | |
19d1bd0b | 578 | s->dev_fd, 0); |
24182fbc | 579 | |
d19a4d4e EA |
580 | if (kvm_has_gsi_routing()) { |
581 | /* set up irq routing */ | |
d19a4d4e EA |
582 | for (i = 0; i < s->num_irq - GIC_INTERNAL; ++i) { |
583 | kvm_irqchip_add_irq_route(kvm_state, i, 0, i); | |
584 | } | |
585 | ||
586 | kvm_gsi_routing_allowed = true; | |
587 | ||
588 | kvm_irqchip_commit_routes(kvm_state); | |
589 | } | |
ed466761 PM |
590 | } |
591 | ||
592 | static void kvm_arm_gic_class_init(ObjectClass *klass, void *data) | |
593 | { | |
594 | DeviceClass *dc = DEVICE_CLASS(klass); | |
595 | ARMGICCommonClass *agcc = ARM_GIC_COMMON_CLASS(klass); | |
596 | KVMARMGICClass *kgc = KVM_ARM_GIC_CLASS(klass); | |
597 | ||
598 | agcc->pre_save = kvm_arm_gic_get; | |
599 | agcc->post_load = kvm_arm_gic_put; | |
bf853881 PMD |
600 | device_class_set_parent_realize(dc, kvm_arm_gic_realize, |
601 | &kgc->parent_realize); | |
602 | device_class_set_parent_reset(dc, kvm_arm_gic_reset, &kgc->parent_reset); | |
ed466761 PM |
603 | } |
604 | ||
605 | static const TypeInfo kvm_arm_gic_info = { | |
606 | .name = TYPE_KVM_ARM_GIC, | |
607 | .parent = TYPE_ARM_GIC_COMMON, | |
608 | .instance_size = sizeof(GICState), | |
609 | .class_init = kvm_arm_gic_class_init, | |
610 | .class_size = sizeof(KVMARMGICClass), | |
611 | }; | |
612 | ||
613 | static void kvm_arm_gic_register_types(void) | |
614 | { | |
615 | type_register_static(&kvm_arm_gic_info); | |
616 | } | |
617 | ||
618 | type_init(kvm_arm_gic_register_types) |