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359fbe65 PM |
1 | /* |
2 | * ARM Generic Interrupt Controller v3 | |
3 | * | |
4 | * Copyright (c) 2016 Linaro Limited | |
5 | * Written by Peter Maydell | |
6 | * | |
7 | * This code is licensed under the GPL, version 2 or (at your option) | |
8 | * any later version. | |
9 | */ | |
10 | ||
11 | /* This file contains the code for the system register interface | |
12 | * portions of the GICv3. | |
13 | */ | |
14 | ||
15 | #include "qemu/osdep.h" | |
77620ba6 | 16 | #include "qemu/bitops.h" |
8d04fb55 | 17 | #include "qemu/main-loop.h" |
359fbe65 PM |
18 | #include "trace.h" |
19 | #include "gicv3_internal.h" | |
20 | #include "cpu.h" | |
21 | ||
d3a3e529 VK |
22 | void gicv3_set_gicv3state(CPUState *cpu, GICv3CPUState *s) |
23 | { | |
24 | ARMCPU *arm_cpu = ARM_CPU(cpu); | |
25 | CPUARMState *env = &arm_cpu->env; | |
26 | ||
27 | env->gicv3state = (void *)s; | |
28 | }; | |
29 | ||
359fbe65 PM |
30 | static GICv3CPUState *icc_cs_from_env(CPUARMState *env) |
31 | { | |
d5a5e4c9 | 32 | return env->gicv3state; |
359fbe65 PM |
33 | } |
34 | ||
35 | static bool gicv3_use_ns_bank(CPUARMState *env) | |
36 | { | |
37 | /* Return true if we should use the NonSecure bank for a banked GIC | |
38 | * CPU interface register. Note that this differs from the | |
39 | * access_secure_reg() function because GICv3 banked registers are | |
40 | * banked even for AArch64, unlike the other CPU system registers. | |
41 | */ | |
42 | return !arm_is_secure_below_el3(env); | |
43 | } | |
44 | ||
4eb833b5 PM |
45 | /* The minimum BPR for the virtual interface is a configurable property */ |
46 | static inline int icv_min_vbpr(GICv3CPUState *cs) | |
47 | { | |
48 | return 7 - cs->vprebits; | |
49 | } | |
50 | ||
83f036fe | 51 | /* Simple accessor functions for LR fields */ |
df313f48 PM |
52 | static uint32_t ich_lr_vintid(uint64_t lr) |
53 | { | |
54 | return extract64(lr, ICH_LR_EL2_VINTID_SHIFT, ICH_LR_EL2_VINTID_LENGTH); | |
55 | } | |
56 | ||
57 | static uint32_t ich_lr_pintid(uint64_t lr) | |
58 | { | |
59 | return extract64(lr, ICH_LR_EL2_PINTID_SHIFT, ICH_LR_EL2_PINTID_LENGTH); | |
60 | } | |
61 | ||
62 | static uint32_t ich_lr_prio(uint64_t lr) | |
63 | { | |
64 | return extract64(lr, ICH_LR_EL2_PRIORITY_SHIFT, ICH_LR_EL2_PRIORITY_LENGTH); | |
65 | } | |
66 | ||
83f036fe PM |
67 | static int ich_lr_state(uint64_t lr) |
68 | { | |
69 | return extract64(lr, ICH_LR_EL2_STATE_SHIFT, ICH_LR_EL2_STATE_LENGTH); | |
70 | } | |
71 | ||
77620ba6 PM |
72 | static bool icv_access(CPUARMState *env, int hcr_flags) |
73 | { | |
74 | /* Return true if this ICC_ register access should really be | |
75 | * directed to an ICV_ access. hcr_flags is a mask of | |
76 | * HCR_EL2 bits to check: we treat this as an ICV_ access | |
77 | * if we are in NS EL1 and at least one of the specified | |
78 | * HCR_EL2 bits is set. | |
79 | * | |
80 | * ICV registers fall into four categories: | |
81 | * * access if NS EL1 and HCR_EL2.FMO == 1: | |
82 | * all ICV regs with '0' in their name | |
83 | * * access if NS EL1 and HCR_EL2.IMO == 1: | |
84 | * all ICV regs with '1' in their name | |
85 | * * access if NS EL1 and either IMO or FMO == 1: | |
86 | * CTLR, DIR, PMR, RPR | |
87 | */ | |
f7778444 RH |
88 | uint64_t hcr_el2 = arm_hcr_el2_eff(env); |
89 | bool flagmatch = hcr_el2 & hcr_flags & (HCR_IMO | HCR_FMO); | |
ac656b16 PM |
90 | |
91 | return flagmatch && arm_current_el(env) == 1 | |
77620ba6 PM |
92 | && !arm_is_secure_below_el3(env); |
93 | } | |
94 | ||
83f036fe PM |
95 | static int read_vbpr(GICv3CPUState *cs, int grp) |
96 | { | |
97 | /* Read VBPR value out of the VMCR field (caller must handle | |
98 | * VCBPR effects if required) | |
99 | */ | |
100 | if (grp == GICV3_G0) { | |
101 | return extract64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VBPR0_SHIFT, | |
102 | ICH_VMCR_EL2_VBPR0_LENGTH); | |
103 | } else { | |
104 | return extract64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VBPR1_SHIFT, | |
105 | ICH_VMCR_EL2_VBPR1_LENGTH); | |
106 | } | |
107 | } | |
108 | ||
109 | static void write_vbpr(GICv3CPUState *cs, int grp, int value) | |
110 | { | |
111 | /* Write new VBPR1 value, handling the "writing a value less than | |
112 | * the minimum sets it to the minimum" semantics. | |
113 | */ | |
114 | int min = icv_min_vbpr(cs); | |
115 | ||
116 | if (grp != GICV3_G0) { | |
117 | min++; | |
118 | } | |
119 | ||
120 | value = MAX(value, min); | |
121 | ||
122 | if (grp == GICV3_G0) { | |
123 | cs->ich_vmcr_el2 = deposit64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VBPR0_SHIFT, | |
124 | ICH_VMCR_EL2_VBPR0_LENGTH, value); | |
125 | } else { | |
126 | cs->ich_vmcr_el2 = deposit64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VBPR1_SHIFT, | |
127 | ICH_VMCR_EL2_VBPR1_LENGTH, value); | |
128 | } | |
129 | } | |
130 | ||
77620ba6 PM |
131 | static uint32_t icv_fullprio_mask(GICv3CPUState *cs) |
132 | { | |
133 | /* Return a mask word which clears the unimplemented priority bits | |
134 | * from a priority value for a virtual interrupt. (Not to be confused | |
135 | * with the group priority, whose mask depends on the value of VBPR | |
136 | * for the interrupt group.) | |
137 | */ | |
138 | return ~0U << (8 - cs->vpribits); | |
139 | } | |
140 | ||
df313f48 PM |
141 | static int ich_highest_active_virt_prio(GICv3CPUState *cs) |
142 | { | |
143 | /* Calculate the current running priority based on the set bits | |
144 | * in the ICH Active Priority Registers. | |
145 | */ | |
146 | int i; | |
147 | int aprmax = 1 << (cs->vprebits - 5); | |
148 | ||
149 | assert(aprmax <= ARRAY_SIZE(cs->ich_apr[0])); | |
150 | ||
151 | for (i = 0; i < aprmax; i++) { | |
152 | uint32_t apr = cs->ich_apr[GICV3_G0][i] | | |
153 | cs->ich_apr[GICV3_G1NS][i]; | |
154 | ||
155 | if (!apr) { | |
156 | continue; | |
157 | } | |
158 | return (i * 32 + ctz32(apr)) << (icv_min_vbpr(cs) + 1); | |
159 | } | |
160 | /* No current active interrupts: return idle priority */ | |
161 | return 0xff; | |
162 | } | |
163 | ||
164 | static int hppvi_index(GICv3CPUState *cs) | |
165 | { | |
166 | /* Return the list register index of the highest priority pending | |
167 | * virtual interrupt, as per the HighestPriorityVirtualInterrupt | |
168 | * pseudocode. If no pending virtual interrupts, return -1. | |
169 | */ | |
170 | int idx = -1; | |
171 | int i; | |
172 | /* Note that a list register entry with a priority of 0xff will | |
173 | * never be reported by this function; this is the architecturally | |
174 | * correct behaviour. | |
175 | */ | |
176 | int prio = 0xff; | |
177 | ||
178 | if (!(cs->ich_vmcr_el2 & (ICH_VMCR_EL2_VENG0 | ICH_VMCR_EL2_VENG1))) { | |
179 | /* Both groups disabled, definitely nothing to do */ | |
180 | return idx; | |
181 | } | |
182 | ||
183 | for (i = 0; i < cs->num_list_regs; i++) { | |
184 | uint64_t lr = cs->ich_lr_el2[i]; | |
185 | int thisprio; | |
186 | ||
187 | if (ich_lr_state(lr) != ICH_LR_EL2_STATE_PENDING) { | |
188 | /* Not Pending */ | |
189 | continue; | |
190 | } | |
191 | ||
192 | /* Ignore interrupts if relevant group enable not set */ | |
193 | if (lr & ICH_LR_EL2_GROUP) { | |
194 | if (!(cs->ich_vmcr_el2 & ICH_VMCR_EL2_VENG1)) { | |
195 | continue; | |
196 | } | |
197 | } else { | |
198 | if (!(cs->ich_vmcr_el2 & ICH_VMCR_EL2_VENG0)) { | |
199 | continue; | |
200 | } | |
201 | } | |
202 | ||
203 | thisprio = ich_lr_prio(lr); | |
204 | ||
205 | if (thisprio < prio) { | |
206 | prio = thisprio; | |
207 | idx = i; | |
208 | } | |
209 | } | |
210 | ||
211 | return idx; | |
212 | } | |
213 | ||
b3b48f52 PM |
214 | static uint32_t icv_gprio_mask(GICv3CPUState *cs, int group) |
215 | { | |
216 | /* Return a mask word which clears the subpriority bits from | |
217 | * a priority value for a virtual interrupt in the specified group. | |
a89ff39e PM |
218 | * This depends on the VBPR value. |
219 | * If using VBPR0 then: | |
b3b48f52 PM |
220 | * a BPR of 0 means the group priority bits are [7:1]; |
221 | * a BPR of 1 means they are [7:2], and so on down to | |
222 | * a BPR of 7 meaning no group priority bits at all. | |
a89ff39e PM |
223 | * If using VBPR1 then: |
224 | * a BPR of 0 is impossible (the minimum value is 1) | |
225 | * a BPR of 1 means the group priority bits are [7:1]; | |
226 | * a BPR of 2 means they are [7:2], and so on down to | |
227 | * a BPR of 7 meaning the group priority is [7]. | |
228 | * | |
b3b48f52 PM |
229 | * Which BPR to use depends on the group of the interrupt and |
230 | * the current ICH_VMCR_EL2.VCBPR settings. | |
a89ff39e PM |
231 | * |
232 | * This corresponds to the VGroupBits() pseudocode. | |
b3b48f52 | 233 | */ |
a89ff39e PM |
234 | int bpr; |
235 | ||
b3b48f52 PM |
236 | if (group == GICV3_G1NS && cs->ich_vmcr_el2 & ICH_VMCR_EL2_VCBPR) { |
237 | group = GICV3_G0; | |
238 | } | |
239 | ||
a89ff39e PM |
240 | bpr = read_vbpr(cs, group); |
241 | if (group == GICV3_G1NS) { | |
242 | assert(bpr > 0); | |
243 | bpr--; | |
244 | } | |
245 | ||
246 | return ~0U << (bpr + 1); | |
b3b48f52 PM |
247 | } |
248 | ||
249 | static bool icv_hppi_can_preempt(GICv3CPUState *cs, uint64_t lr) | |
250 | { | |
251 | /* Return true if we can signal this virtual interrupt defined by | |
252 | * the given list register value; see the pseudocode functions | |
253 | * CanSignalVirtualInterrupt and CanSignalVirtualInt. | |
254 | * Compare also icc_hppi_can_preempt() which is the non-virtual | |
255 | * equivalent of these checks. | |
256 | */ | |
257 | int grp; | |
258 | uint32_t mask, prio, rprio, vpmr; | |
259 | ||
260 | if (!(cs->ich_hcr_el2 & ICH_HCR_EL2_EN)) { | |
261 | /* Virtual interface disabled */ | |
262 | return false; | |
263 | } | |
264 | ||
265 | /* We don't need to check that this LR is in Pending state because | |
266 | * that has already been done in hppvi_index(). | |
267 | */ | |
268 | ||
269 | prio = ich_lr_prio(lr); | |
270 | vpmr = extract64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VPMR_SHIFT, | |
271 | ICH_VMCR_EL2_VPMR_LENGTH); | |
272 | ||
273 | if (prio >= vpmr) { | |
274 | /* Priority mask masks this interrupt */ | |
275 | return false; | |
276 | } | |
277 | ||
278 | rprio = ich_highest_active_virt_prio(cs); | |
279 | if (rprio == 0xff) { | |
280 | /* No running interrupt so we can preempt */ | |
281 | return true; | |
282 | } | |
283 | ||
284 | grp = (lr & ICH_LR_EL2_GROUP) ? GICV3_G1NS : GICV3_G0; | |
285 | ||
286 | mask = icv_gprio_mask(cs, grp); | |
287 | ||
288 | /* We only preempt a running interrupt if the pending interrupt's | |
289 | * group priority is sufficient (the subpriorities are not considered). | |
290 | */ | |
291 | if ((prio & mask) < (rprio & mask)) { | |
292 | return true; | |
293 | } | |
294 | ||
295 | return false; | |
296 | } | |
297 | ||
83f036fe PM |
298 | static uint32_t eoi_maintenance_interrupt_state(GICv3CPUState *cs, |
299 | uint32_t *misr) | |
300 | { | |
301 | /* Return a set of bits indicating the EOI maintenance interrupt status | |
302 | * for each list register. The EOI maintenance interrupt status is | |
303 | * 1 if LR.State == 0 && LR.HW == 0 && LR.EOI == 1 | |
304 | * (see the GICv3 spec for the ICH_EISR_EL2 register). | |
305 | * If misr is not NULL then we should also collect the information | |
306 | * about the MISR.EOI, MISR.NP and MISR.U bits. | |
307 | */ | |
308 | uint32_t value = 0; | |
309 | int validcount = 0; | |
310 | bool seenpending = false; | |
311 | int i; | |
312 | ||
313 | for (i = 0; i < cs->num_list_regs; i++) { | |
314 | uint64_t lr = cs->ich_lr_el2[i]; | |
315 | ||
316 | if ((lr & (ICH_LR_EL2_STATE_MASK | ICH_LR_EL2_HW | ICH_LR_EL2_EOI)) | |
317 | == ICH_LR_EL2_EOI) { | |
318 | value |= (1 << i); | |
319 | } | |
320 | if ((lr & ICH_LR_EL2_STATE_MASK)) { | |
321 | validcount++; | |
322 | } | |
323 | if (ich_lr_state(lr) == ICH_LR_EL2_STATE_PENDING) { | |
324 | seenpending = true; | |
325 | } | |
326 | } | |
327 | ||
328 | if (misr) { | |
329 | if (validcount < 2 && (cs->ich_hcr_el2 & ICH_HCR_EL2_UIE)) { | |
330 | *misr |= ICH_MISR_EL2_U; | |
331 | } | |
332 | if (!seenpending && (cs->ich_hcr_el2 & ICH_HCR_EL2_NPIE)) { | |
333 | *misr |= ICH_MISR_EL2_NP; | |
334 | } | |
335 | if (value) { | |
336 | *misr |= ICH_MISR_EL2_EOI; | |
337 | } | |
338 | } | |
339 | return value; | |
340 | } | |
341 | ||
342 | static uint32_t maintenance_interrupt_state(GICv3CPUState *cs) | |
343 | { | |
344 | /* Return a set of bits indicating the maintenance interrupt status | |
345 | * (as seen in the ICH_MISR_EL2 register). | |
346 | */ | |
347 | uint32_t value = 0; | |
348 | ||
349 | /* Scan list registers and fill in the U, NP and EOI bits */ | |
350 | eoi_maintenance_interrupt_state(cs, &value); | |
351 | ||
352 | if (cs->ich_hcr_el2 & (ICH_HCR_EL2_LRENPIE | ICH_HCR_EL2_EOICOUNT_MASK)) { | |
353 | value |= ICH_MISR_EL2_LRENP; | |
354 | } | |
355 | ||
356 | if ((cs->ich_hcr_el2 & ICH_HCR_EL2_VGRP0EIE) && | |
357 | (cs->ich_vmcr_el2 & ICH_VMCR_EL2_VENG0)) { | |
358 | value |= ICH_MISR_EL2_VGRP0E; | |
359 | } | |
360 | ||
361 | if ((cs->ich_hcr_el2 & ICH_HCR_EL2_VGRP0DIE) && | |
362 | !(cs->ich_vmcr_el2 & ICH_VMCR_EL2_VENG1)) { | |
363 | value |= ICH_MISR_EL2_VGRP0D; | |
364 | } | |
365 | if ((cs->ich_hcr_el2 & ICH_HCR_EL2_VGRP1EIE) && | |
366 | (cs->ich_vmcr_el2 & ICH_VMCR_EL2_VENG1)) { | |
367 | value |= ICH_MISR_EL2_VGRP1E; | |
368 | } | |
369 | ||
370 | if ((cs->ich_hcr_el2 & ICH_HCR_EL2_VGRP1DIE) && | |
371 | !(cs->ich_vmcr_el2 & ICH_VMCR_EL2_VENG1)) { | |
372 | value |= ICH_MISR_EL2_VGRP1D; | |
373 | } | |
374 | ||
375 | return value; | |
376 | } | |
377 | ||
378 | static void gicv3_cpuif_virt_update(GICv3CPUState *cs) | |
379 | { | |
c5fc89b3 PM |
380 | /* Tell the CPU about any pending virtual interrupts or |
381 | * maintenance interrupts, following a change to the state | |
382 | * of the CPU interface relevant to virtual interrupts. | |
383 | * | |
384 | * CAUTION: this function will call qemu_set_irq() on the | |
385 | * CPU maintenance IRQ line, which is typically wired up | |
386 | * to the GIC as a per-CPU interrupt. This means that it | |
387 | * will recursively call back into the GIC code via | |
388 | * gicv3_redist_set_irq() and thus into the CPU interface code's | |
389 | * gicv3_cpuif_update(). It is therefore important that this | |
390 | * function is only called as the final action of a CPU interface | |
391 | * register write implementation, after all the GIC state | |
392 | * fields have been updated. gicv3_cpuif_update() also must | |
393 | * not cause this function to be called, but that happens | |
394 | * naturally as a result of there being no architectural | |
395 | * linkage between the physical and virtual GIC logic. | |
396 | */ | |
397 | int idx; | |
398 | int irqlevel = 0; | |
399 | int fiqlevel = 0; | |
400 | int maintlevel = 0; | |
401 | ||
402 | idx = hppvi_index(cs); | |
403 | trace_gicv3_cpuif_virt_update(gicv3_redist_affid(cs), idx); | |
404 | if (idx >= 0) { | |
405 | uint64_t lr = cs->ich_lr_el2[idx]; | |
406 | ||
407 | if (icv_hppi_can_preempt(cs, lr)) { | |
408 | /* Virtual interrupts are simple: G0 are always FIQ, and G1 IRQ */ | |
409 | if (lr & ICH_LR_EL2_GROUP) { | |
410 | irqlevel = 1; | |
411 | } else { | |
412 | fiqlevel = 1; | |
413 | } | |
414 | } | |
415 | } | |
416 | ||
417 | if (cs->ich_hcr_el2 & ICH_HCR_EL2_EN) { | |
418 | maintlevel = maintenance_interrupt_state(cs); | |
419 | } | |
420 | ||
421 | trace_gicv3_cpuif_virt_set_irqs(gicv3_redist_affid(cs), fiqlevel, | |
422 | irqlevel, maintlevel); | |
423 | ||
424 | qemu_set_irq(cs->parent_vfiq, fiqlevel); | |
425 | qemu_set_irq(cs->parent_virq, irqlevel); | |
426 | qemu_set_irq(cs->maintenance_irq, maintlevel); | |
83f036fe PM |
427 | } |
428 | ||
77620ba6 PM |
429 | static uint64_t icv_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) |
430 | { | |
431 | GICv3CPUState *cs = icc_cs_from_env(env); | |
432 | int regno = ri->opc2 & 3; | |
887aae10 | 433 | int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0; |
77620ba6 PM |
434 | uint64_t value = cs->ich_apr[grp][regno]; |
435 | ||
436 | trace_gicv3_icv_ap_read(ri->crm & 1, regno, gicv3_redist_affid(cs), value); | |
437 | return value; | |
438 | } | |
439 | ||
440 | static void icv_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
441 | uint64_t value) | |
442 | { | |
443 | GICv3CPUState *cs = icc_cs_from_env(env); | |
444 | int regno = ri->opc2 & 3; | |
887aae10 | 445 | int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0; |
77620ba6 PM |
446 | |
447 | trace_gicv3_icv_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value); | |
448 | ||
449 | cs->ich_apr[grp][regno] = value & 0xFFFFFFFFU; | |
450 | ||
451 | gicv3_cpuif_virt_update(cs); | |
452 | return; | |
453 | } | |
454 | ||
455 | static uint64_t icv_bpr_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
456 | { | |
457 | GICv3CPUState *cs = icc_cs_from_env(env); | |
458 | int grp = (ri->crm == 8) ? GICV3_G0 : GICV3_G1NS; | |
459 | uint64_t bpr; | |
460 | bool satinc = false; | |
461 | ||
462 | if (grp == GICV3_G1NS && (cs->ich_vmcr_el2 & ICH_VMCR_EL2_VCBPR)) { | |
463 | /* reads return bpr0 + 1 saturated to 7, writes ignored */ | |
464 | grp = GICV3_G0; | |
465 | satinc = true; | |
466 | } | |
467 | ||
468 | bpr = read_vbpr(cs, grp); | |
469 | ||
470 | if (satinc) { | |
471 | bpr++; | |
472 | bpr = MIN(bpr, 7); | |
473 | } | |
474 | ||
475 | trace_gicv3_icv_bpr_read(ri->crm == 8 ? 0 : 1, gicv3_redist_affid(cs), bpr); | |
476 | ||
477 | return bpr; | |
478 | } | |
479 | ||
480 | static void icv_bpr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
481 | uint64_t value) | |
482 | { | |
483 | GICv3CPUState *cs = icc_cs_from_env(env); | |
484 | int grp = (ri->crm == 8) ? GICV3_G0 : GICV3_G1NS; | |
485 | ||
486 | trace_gicv3_icv_bpr_write(ri->crm == 8 ? 0 : 1, | |
487 | gicv3_redist_affid(cs), value); | |
488 | ||
489 | if (grp == GICV3_G1NS && (cs->ich_vmcr_el2 & ICH_VMCR_EL2_VCBPR)) { | |
490 | /* reads return bpr0 + 1 saturated to 7, writes ignored */ | |
491 | return; | |
492 | } | |
493 | ||
494 | write_vbpr(cs, grp, value); | |
495 | ||
496 | gicv3_cpuif_virt_update(cs); | |
497 | } | |
498 | ||
499 | static uint64_t icv_pmr_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
500 | { | |
501 | GICv3CPUState *cs = icc_cs_from_env(env); | |
502 | uint64_t value; | |
503 | ||
504 | value = extract64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VPMR_SHIFT, | |
505 | ICH_VMCR_EL2_VPMR_LENGTH); | |
506 | ||
507 | trace_gicv3_icv_pmr_read(gicv3_redist_affid(cs), value); | |
508 | return value; | |
509 | } | |
510 | ||
511 | static void icv_pmr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
512 | uint64_t value) | |
513 | { | |
514 | GICv3CPUState *cs = icc_cs_from_env(env); | |
515 | ||
516 | trace_gicv3_icv_pmr_write(gicv3_redist_affid(cs), value); | |
517 | ||
518 | value &= icv_fullprio_mask(cs); | |
519 | ||
520 | cs->ich_vmcr_el2 = deposit64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VPMR_SHIFT, | |
521 | ICH_VMCR_EL2_VPMR_LENGTH, value); | |
522 | ||
523 | gicv3_cpuif_virt_update(cs); | |
524 | } | |
525 | ||
526 | static uint64_t icv_igrpen_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
527 | { | |
528 | GICv3CPUState *cs = icc_cs_from_env(env); | |
529 | int enbit; | |
530 | uint64_t value; | |
531 | ||
532 | enbit = ri->opc2 & 1 ? ICH_VMCR_EL2_VENG1_SHIFT : ICH_VMCR_EL2_VENG0_SHIFT; | |
533 | value = extract64(cs->ich_vmcr_el2, enbit, 1); | |
534 | ||
535 | trace_gicv3_icv_igrpen_read(ri->opc2 & 1 ? 1 : 0, | |
536 | gicv3_redist_affid(cs), value); | |
537 | return value; | |
538 | } | |
539 | ||
540 | static void icv_igrpen_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
541 | uint64_t value) | |
542 | { | |
543 | GICv3CPUState *cs = icc_cs_from_env(env); | |
544 | int enbit; | |
545 | ||
546 | trace_gicv3_icv_igrpen_write(ri->opc2 & 1 ? 1 : 0, | |
547 | gicv3_redist_affid(cs), value); | |
548 | ||
549 | enbit = ri->opc2 & 1 ? ICH_VMCR_EL2_VENG1_SHIFT : ICH_VMCR_EL2_VENG0_SHIFT; | |
550 | ||
551 | cs->ich_vmcr_el2 = deposit64(cs->ich_vmcr_el2, enbit, 1, value); | |
552 | gicv3_cpuif_virt_update(cs); | |
553 | } | |
554 | ||
555 | static uint64_t icv_ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
556 | { | |
557 | GICv3CPUState *cs = icc_cs_from_env(env); | |
558 | uint64_t value; | |
559 | ||
560 | /* Note that the fixed fields here (A3V, SEIS, IDbits, PRIbits) | |
561 | * should match the ones reported in ich_vtr_read(). | |
562 | */ | |
563 | value = ICC_CTLR_EL1_A3V | (1 << ICC_CTLR_EL1_IDBITS_SHIFT) | | |
564 | (7 << ICC_CTLR_EL1_PRIBITS_SHIFT); | |
565 | ||
566 | if (cs->ich_vmcr_el2 & ICH_VMCR_EL2_VEOIM) { | |
567 | value |= ICC_CTLR_EL1_EOIMODE; | |
568 | } | |
569 | ||
570 | if (cs->ich_vmcr_el2 & ICH_VMCR_EL2_VCBPR) { | |
571 | value |= ICC_CTLR_EL1_CBPR; | |
572 | } | |
573 | ||
574 | trace_gicv3_icv_ctlr_read(gicv3_redist_affid(cs), value); | |
575 | return value; | |
576 | } | |
577 | ||
578 | static void icv_ctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
579 | uint64_t value) | |
580 | { | |
581 | GICv3CPUState *cs = icc_cs_from_env(env); | |
582 | ||
583 | trace_gicv3_icv_ctlr_write(gicv3_redist_affid(cs), value); | |
584 | ||
585 | cs->ich_vmcr_el2 = deposit64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VCBPR_SHIFT, | |
586 | 1, value & ICC_CTLR_EL1_CBPR ? 1 : 0); | |
587 | cs->ich_vmcr_el2 = deposit64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VEOIM_SHIFT, | |
588 | 1, value & ICC_CTLR_EL1_EOIMODE ? 1 : 0); | |
589 | ||
590 | gicv3_cpuif_virt_update(cs); | |
591 | } | |
592 | ||
df313f48 PM |
593 | static uint64_t icv_rpr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
594 | { | |
595 | GICv3CPUState *cs = icc_cs_from_env(env); | |
596 | int prio = ich_highest_active_virt_prio(cs); | |
597 | ||
598 | trace_gicv3_icv_rpr_read(gicv3_redist_affid(cs), prio); | |
599 | return prio; | |
600 | } | |
601 | ||
602 | static uint64_t icv_hppir_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
603 | { | |
604 | GICv3CPUState *cs = icc_cs_from_env(env); | |
605 | int grp = ri->crm == 8 ? GICV3_G0 : GICV3_G1NS; | |
606 | int idx = hppvi_index(cs); | |
607 | uint64_t value = INTID_SPURIOUS; | |
608 | ||
609 | if (idx >= 0) { | |
610 | uint64_t lr = cs->ich_lr_el2[idx]; | |
611 | int thisgrp = (lr & ICH_LR_EL2_GROUP) ? GICV3_G1NS : GICV3_G0; | |
612 | ||
613 | if (grp == thisgrp) { | |
614 | value = ich_lr_vintid(lr); | |
615 | } | |
616 | } | |
617 | ||
618 | trace_gicv3_icv_hppir_read(grp, gicv3_redist_affid(cs), value); | |
619 | return value; | |
620 | } | |
621 | ||
b3b48f52 PM |
622 | static void icv_activate_irq(GICv3CPUState *cs, int idx, int grp) |
623 | { | |
624 | /* Activate the interrupt in the specified list register | |
625 | * by moving it from Pending to Active state, and update the | |
626 | * Active Priority Registers. | |
627 | */ | |
628 | uint32_t mask = icv_gprio_mask(cs, grp); | |
629 | int prio = ich_lr_prio(cs->ich_lr_el2[idx]) & mask; | |
630 | int aprbit = prio >> (8 - cs->vprebits); | |
631 | int regno = aprbit / 32; | |
632 | int regbit = aprbit % 32; | |
633 | ||
634 | cs->ich_lr_el2[idx] &= ~ICH_LR_EL2_STATE_PENDING_BIT; | |
635 | cs->ich_lr_el2[idx] |= ICH_LR_EL2_STATE_ACTIVE_BIT; | |
636 | cs->ich_apr[grp][regno] |= (1 << regbit); | |
637 | } | |
638 | ||
639 | static uint64_t icv_iar_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
640 | { | |
641 | GICv3CPUState *cs = icc_cs_from_env(env); | |
642 | int grp = ri->crm == 8 ? GICV3_G0 : GICV3_G1NS; | |
643 | int idx = hppvi_index(cs); | |
644 | uint64_t intid = INTID_SPURIOUS; | |
645 | ||
646 | if (idx >= 0) { | |
647 | uint64_t lr = cs->ich_lr_el2[idx]; | |
648 | int thisgrp = (lr & ICH_LR_EL2_GROUP) ? GICV3_G1NS : GICV3_G0; | |
649 | ||
650 | if (thisgrp == grp && icv_hppi_can_preempt(cs, lr)) { | |
651 | intid = ich_lr_vintid(lr); | |
652 | if (intid < INTID_SECURE) { | |
653 | icv_activate_irq(cs, idx, grp); | |
654 | } else { | |
655 | /* Interrupt goes from Pending to Invalid */ | |
656 | cs->ich_lr_el2[idx] &= ~ICH_LR_EL2_STATE_PENDING_BIT; | |
657 | /* We will now return the (bogus) ID from the list register, | |
658 | * as per the pseudocode. | |
659 | */ | |
660 | } | |
661 | } | |
662 | } | |
663 | ||
664 | trace_gicv3_icv_iar_read(ri->crm == 8 ? 0 : 1, | |
665 | gicv3_redist_affid(cs), intid); | |
666 | return intid; | |
667 | } | |
668 | ||
f7b9358e PM |
669 | static int icc_highest_active_prio(GICv3CPUState *cs) |
670 | { | |
671 | /* Calculate the current running priority based on the set bits | |
672 | * in the Active Priority Registers. | |
673 | */ | |
674 | int i; | |
675 | ||
676 | for (i = 0; i < ARRAY_SIZE(cs->icc_apr[0]); i++) { | |
677 | uint32_t apr = cs->icc_apr[GICV3_G0][i] | | |
678 | cs->icc_apr[GICV3_G1][i] | cs->icc_apr[GICV3_G1NS][i]; | |
679 | ||
680 | if (!apr) { | |
681 | continue; | |
682 | } | |
683 | return (i * 32 + ctz32(apr)) << (GIC_MIN_BPR + 1); | |
684 | } | |
685 | /* No current active interrupts: return idle priority */ | |
686 | return 0xff; | |
687 | } | |
688 | ||
689 | static uint32_t icc_gprio_mask(GICv3CPUState *cs, int group) | |
690 | { | |
691 | /* Return a mask word which clears the subpriority bits from | |
692 | * a priority value for an interrupt in the specified group. | |
a89ff39e | 693 | * This depends on the BPR value. For CBPR0 (S or NS): |
f7b9358e PM |
694 | * a BPR of 0 means the group priority bits are [7:1]; |
695 | * a BPR of 1 means they are [7:2], and so on down to | |
696 | * a BPR of 7 meaning no group priority bits at all. | |
a89ff39e PM |
697 | * For CBPR1 NS: |
698 | * a BPR of 0 is impossible (the minimum value is 1) | |
699 | * a BPR of 1 means the group priority bits are [7:1]; | |
700 | * a BPR of 2 means they are [7:2], and so on down to | |
701 | * a BPR of 7 meaning the group priority is [7]. | |
702 | * | |
f7b9358e PM |
703 | * Which BPR to use depends on the group of the interrupt and |
704 | * the current ICC_CTLR.CBPR settings. | |
a89ff39e PM |
705 | * |
706 | * This corresponds to the GroupBits() pseudocode. | |
f7b9358e | 707 | */ |
a89ff39e PM |
708 | int bpr; |
709 | ||
f7b9358e PM |
710 | if ((group == GICV3_G1 && cs->icc_ctlr_el1[GICV3_S] & ICC_CTLR_EL1_CBPR) || |
711 | (group == GICV3_G1NS && | |
712 | cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_CBPR)) { | |
713 | group = GICV3_G0; | |
714 | } | |
715 | ||
a89ff39e PM |
716 | bpr = cs->icc_bpr[group] & 7; |
717 | ||
718 | if (group == GICV3_G1NS) { | |
719 | assert(bpr > 0); | |
720 | bpr--; | |
721 | } | |
722 | ||
723 | return ~0U << (bpr + 1); | |
f7b9358e PM |
724 | } |
725 | ||
726 | static bool icc_no_enabled_hppi(GICv3CPUState *cs) | |
727 | { | |
728 | /* Return true if there is no pending interrupt, or the | |
729 | * highest priority pending interrupt is in a group which has been | |
730 | * disabled at the CPU interface by the ICC_IGRPEN* register enable bits. | |
731 | */ | |
732 | return cs->hppi.prio == 0xff || (cs->icc_igrpen[cs->hppi.grp] == 0); | |
733 | } | |
734 | ||
735 | static bool icc_hppi_can_preempt(GICv3CPUState *cs) | |
736 | { | |
737 | /* Return true if we have a pending interrupt of sufficient | |
738 | * priority to preempt. | |
739 | */ | |
740 | int rprio; | |
741 | uint32_t mask; | |
742 | ||
743 | if (icc_no_enabled_hppi(cs)) { | |
744 | return false; | |
745 | } | |
746 | ||
747 | if (cs->hppi.prio >= cs->icc_pmr_el1) { | |
748 | /* Priority mask masks this interrupt */ | |
749 | return false; | |
750 | } | |
751 | ||
752 | rprio = icc_highest_active_prio(cs); | |
753 | if (rprio == 0xff) { | |
754 | /* No currently running interrupt so we can preempt */ | |
755 | return true; | |
756 | } | |
757 | ||
758 | mask = icc_gprio_mask(cs, cs->hppi.grp); | |
759 | ||
760 | /* We only preempt a running interrupt if the pending interrupt's | |
761 | * group priority is sufficient (the subpriorities are not considered). | |
762 | */ | |
763 | if ((cs->hppi.prio & mask) < (rprio & mask)) { | |
764 | return true; | |
765 | } | |
766 | ||
767 | return false; | |
768 | } | |
769 | ||
770 | void gicv3_cpuif_update(GICv3CPUState *cs) | |
771 | { | |
772 | /* Tell the CPU about its highest priority pending interrupt */ | |
773 | int irqlevel = 0; | |
774 | int fiqlevel = 0; | |
775 | ARMCPU *cpu = ARM_CPU(cs->cpu); | |
776 | CPUARMState *env = &cpu->env; | |
777 | ||
8d04fb55 JK |
778 | g_assert(qemu_mutex_iothread_locked()); |
779 | ||
f7b9358e PM |
780 | trace_gicv3_cpuif_update(gicv3_redist_affid(cs), cs->hppi.irq, |
781 | cs->hppi.grp, cs->hppi.prio); | |
782 | ||
783 | if (cs->hppi.grp == GICV3_G1 && !arm_feature(env, ARM_FEATURE_EL3)) { | |
784 | /* If a Security-enabled GIC sends a G1S interrupt to a | |
785 | * Security-disabled CPU, we must treat it as if it were G0. | |
786 | */ | |
787 | cs->hppi.grp = GICV3_G0; | |
788 | } | |
789 | ||
790 | if (icc_hppi_can_preempt(cs)) { | |
791 | /* We have an interrupt: should we signal it as IRQ or FIQ? | |
792 | * This is described in the GICv3 spec section 4.6.2. | |
793 | */ | |
794 | bool isfiq; | |
795 | ||
796 | switch (cs->hppi.grp) { | |
797 | case GICV3_G0: | |
798 | isfiq = true; | |
799 | break; | |
800 | case GICV3_G1: | |
801 | isfiq = (!arm_is_secure(env) || | |
802 | (arm_current_el(env) == 3 && arm_el_is_aa64(env, 3))); | |
803 | break; | |
804 | case GICV3_G1NS: | |
805 | isfiq = arm_is_secure(env); | |
806 | break; | |
807 | default: | |
808 | g_assert_not_reached(); | |
809 | } | |
810 | ||
811 | if (isfiq) { | |
812 | fiqlevel = 1; | |
813 | } else { | |
814 | irqlevel = 1; | |
815 | } | |
816 | } | |
817 | ||
818 | trace_gicv3_cpuif_set_irqs(gicv3_redist_affid(cs), fiqlevel, irqlevel); | |
819 | ||
820 | qemu_set_irq(cs->parent_fiq, fiqlevel); | |
821 | qemu_set_irq(cs->parent_irq, irqlevel); | |
822 | } | |
823 | ||
359fbe65 PM |
824 | static uint64_t icc_pmr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
825 | { | |
826 | GICv3CPUState *cs = icc_cs_from_env(env); | |
827 | uint32_t value = cs->icc_pmr_el1; | |
828 | ||
77620ba6 PM |
829 | if (icv_access(env, HCR_FMO | HCR_IMO)) { |
830 | return icv_pmr_read(env, ri); | |
831 | } | |
832 | ||
359fbe65 PM |
833 | if (arm_feature(env, ARM_FEATURE_EL3) && !arm_is_secure(env) && |
834 | (env->cp15.scr_el3 & SCR_FIQ)) { | |
835 | /* NS access and Group 0 is inaccessible to NS: return the | |
836 | * NS view of the current priority | |
837 | */ | |
a2e2d7fc | 838 | if ((value & 0x80) == 0) { |
359fbe65 PM |
839 | /* Secure priorities not visible to NS */ |
840 | value = 0; | |
841 | } else if (value != 0xff) { | |
842 | value = (value << 1) & 0xff; | |
843 | } | |
844 | } | |
845 | ||
846 | trace_gicv3_icc_pmr_read(gicv3_redist_affid(cs), value); | |
847 | ||
848 | return value; | |
849 | } | |
850 | ||
851 | static void icc_pmr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
852 | uint64_t value) | |
853 | { | |
854 | GICv3CPUState *cs = icc_cs_from_env(env); | |
855 | ||
77620ba6 PM |
856 | if (icv_access(env, HCR_FMO | HCR_IMO)) { |
857 | return icv_pmr_write(env, ri, value); | |
858 | } | |
859 | ||
359fbe65 PM |
860 | trace_gicv3_icc_pmr_write(gicv3_redist_affid(cs), value); |
861 | ||
862 | value &= 0xff; | |
863 | ||
864 | if (arm_feature(env, ARM_FEATURE_EL3) && !arm_is_secure(env) && | |
865 | (env->cp15.scr_el3 & SCR_FIQ)) { | |
866 | /* NS access and Group 0 is inaccessible to NS: return the | |
867 | * NS view of the current priority | |
868 | */ | |
869 | if (!(cs->icc_pmr_el1 & 0x80)) { | |
870 | /* Current PMR in the secure range, don't allow NS to change it */ | |
871 | return; | |
872 | } | |
a2e2d7fc | 873 | value = (value >> 1) | 0x80; |
359fbe65 PM |
874 | } |
875 | cs->icc_pmr_el1 = value; | |
876 | gicv3_cpuif_update(cs); | |
877 | } | |
878 | ||
227a8653 PM |
879 | static void icc_activate_irq(GICv3CPUState *cs, int irq) |
880 | { | |
881 | /* Move the interrupt from the Pending state to Active, and update | |
882 | * the Active Priority Registers | |
883 | */ | |
884 | uint32_t mask = icc_gprio_mask(cs, cs->hppi.grp); | |
885 | int prio = cs->hppi.prio & mask; | |
886 | int aprbit = prio >> 1; | |
887 | int regno = aprbit / 32; | |
888 | int regbit = aprbit % 32; | |
889 | ||
890 | cs->icc_apr[cs->hppi.grp][regno] |= (1 << regbit); | |
891 | ||
892 | if (irq < GIC_INTERNAL) { | |
893 | cs->gicr_iactiver0 = deposit32(cs->gicr_iactiver0, irq, 1, 1); | |
894 | cs->gicr_ipendr0 = deposit32(cs->gicr_ipendr0, irq, 1, 0); | |
895 | gicv3_redist_update(cs); | |
896 | } else { | |
897 | gicv3_gicd_active_set(cs->gic, irq); | |
898 | gicv3_gicd_pending_clear(cs->gic, irq); | |
899 | gicv3_update(cs->gic, irq, 1); | |
900 | } | |
901 | } | |
902 | ||
903 | static uint64_t icc_hppir0_value(GICv3CPUState *cs, CPUARMState *env) | |
904 | { | |
905 | /* Return the highest priority pending interrupt register value | |
906 | * for group 0. | |
907 | */ | |
908 | bool irq_is_secure; | |
909 | ||
910 | if (cs->hppi.prio == 0xff) { | |
911 | return INTID_SPURIOUS; | |
912 | } | |
913 | ||
914 | /* Check whether we can return the interrupt or if we should return | |
915 | * a special identifier, as per the CheckGroup0ForSpecialIdentifiers | |
916 | * pseudocode. (We can simplify a little because for us ICC_SRE_EL1.RM | |
917 | * is always zero.) | |
918 | */ | |
919 | irq_is_secure = (!(cs->gic->gicd_ctlr & GICD_CTLR_DS) && | |
920 | (cs->hppi.grp != GICV3_G1NS)); | |
921 | ||
922 | if (cs->hppi.grp != GICV3_G0 && !arm_is_el3_or_mon(env)) { | |
923 | return INTID_SPURIOUS; | |
924 | } | |
925 | if (irq_is_secure && !arm_is_secure(env)) { | |
926 | /* Secure interrupts not visible to Nonsecure */ | |
927 | return INTID_SPURIOUS; | |
928 | } | |
929 | ||
930 | if (cs->hppi.grp != GICV3_G0) { | |
931 | /* Indicate to EL3 that there's a Group 1 interrupt for the other | |
932 | * state pending. | |
933 | */ | |
934 | return irq_is_secure ? INTID_SECURE : INTID_NONSECURE; | |
935 | } | |
936 | ||
937 | return cs->hppi.irq; | |
938 | } | |
939 | ||
940 | static uint64_t icc_hppir1_value(GICv3CPUState *cs, CPUARMState *env) | |
941 | { | |
942 | /* Return the highest priority pending interrupt register value | |
943 | * for group 1. | |
944 | */ | |
945 | bool irq_is_secure; | |
946 | ||
947 | if (cs->hppi.prio == 0xff) { | |
948 | return INTID_SPURIOUS; | |
949 | } | |
950 | ||
951 | /* Check whether we can return the interrupt or if we should return | |
952 | * a special identifier, as per the CheckGroup1ForSpecialIdentifiers | |
953 | * pseudocode. (We can simplify a little because for us ICC_SRE_EL1.RM | |
954 | * is always zero.) | |
955 | */ | |
956 | irq_is_secure = (!(cs->gic->gicd_ctlr & GICD_CTLR_DS) && | |
957 | (cs->hppi.grp != GICV3_G1NS)); | |
958 | ||
959 | if (cs->hppi.grp == GICV3_G0) { | |
960 | /* Group 0 interrupts not visible via HPPIR1 */ | |
961 | return INTID_SPURIOUS; | |
962 | } | |
963 | if (irq_is_secure) { | |
964 | if (!arm_is_secure(env)) { | |
965 | /* Secure interrupts not visible in Non-secure */ | |
966 | return INTID_SPURIOUS; | |
967 | } | |
968 | } else if (!arm_is_el3_or_mon(env) && arm_is_secure(env)) { | |
969 | /* Group 1 non-secure interrupts not visible in Secure EL1 */ | |
970 | return INTID_SPURIOUS; | |
971 | } | |
972 | ||
973 | return cs->hppi.irq; | |
974 | } | |
975 | ||
976 | static uint64_t icc_iar0_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
977 | { | |
978 | GICv3CPUState *cs = icc_cs_from_env(env); | |
979 | uint64_t intid; | |
980 | ||
b3b48f52 PM |
981 | if (icv_access(env, HCR_FMO)) { |
982 | return icv_iar_read(env, ri); | |
983 | } | |
984 | ||
227a8653 PM |
985 | if (!icc_hppi_can_preempt(cs)) { |
986 | intid = INTID_SPURIOUS; | |
987 | } else { | |
988 | intid = icc_hppir0_value(cs, env); | |
989 | } | |
990 | ||
991 | if (!(intid >= INTID_SECURE && intid <= INTID_SPURIOUS)) { | |
992 | icc_activate_irq(cs, intid); | |
993 | } | |
994 | ||
995 | trace_gicv3_icc_iar0_read(gicv3_redist_affid(cs), intid); | |
996 | return intid; | |
997 | } | |
998 | ||
999 | static uint64_t icc_iar1_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
1000 | { | |
1001 | GICv3CPUState *cs = icc_cs_from_env(env); | |
1002 | uint64_t intid; | |
1003 | ||
b3b48f52 PM |
1004 | if (icv_access(env, HCR_IMO)) { |
1005 | return icv_iar_read(env, ri); | |
1006 | } | |
1007 | ||
227a8653 PM |
1008 | if (!icc_hppi_can_preempt(cs)) { |
1009 | intid = INTID_SPURIOUS; | |
1010 | } else { | |
1011 | intid = icc_hppir1_value(cs, env); | |
1012 | } | |
1013 | ||
1014 | if (!(intid >= INTID_SECURE && intid <= INTID_SPURIOUS)) { | |
1015 | icc_activate_irq(cs, intid); | |
1016 | } | |
1017 | ||
1018 | trace_gicv3_icc_iar1_read(gicv3_redist_affid(cs), intid); | |
1019 | return intid; | |
1020 | } | |
1021 | ||
1022 | static void icc_drop_prio(GICv3CPUState *cs, int grp) | |
1023 | { | |
1024 | /* Drop the priority of the currently active interrupt in | |
1025 | * the specified group. | |
1026 | * | |
1027 | * Note that we can guarantee (because of the requirement to nest | |
1028 | * ICC_IAR reads [which activate an interrupt and raise priority] | |
1029 | * with ICC_EOIR writes [which drop the priority for the interrupt]) | |
1030 | * that the interrupt we're being called for is the highest priority | |
1031 | * active interrupt, meaning that it has the lowest set bit in the | |
1032 | * APR registers. | |
1033 | * | |
1034 | * If the guest does not honour the ordering constraints then the | |
1035 | * behaviour of the GIC is UNPREDICTABLE, which for us means that | |
1036 | * the values of the APR registers might become incorrect and the | |
1037 | * running priority will be wrong, so interrupts that should preempt | |
1038 | * might not do so, and interrupts that should not preempt might do so. | |
1039 | */ | |
1040 | int i; | |
1041 | ||
1042 | for (i = 0; i < ARRAY_SIZE(cs->icc_apr[grp]); i++) { | |
1043 | uint64_t *papr = &cs->icc_apr[grp][i]; | |
1044 | ||
1045 | if (!*papr) { | |
1046 | continue; | |
1047 | } | |
1048 | /* Clear the lowest set bit */ | |
1049 | *papr &= *papr - 1; | |
1050 | break; | |
1051 | } | |
1052 | ||
1053 | /* running priority change means we need an update for this cpu i/f */ | |
1054 | gicv3_cpuif_update(cs); | |
1055 | } | |
1056 | ||
1057 | static bool icc_eoi_split(CPUARMState *env, GICv3CPUState *cs) | |
1058 | { | |
1059 | /* Return true if we should split priority drop and interrupt | |
1060 | * deactivation, ie whether the relevant EOIMode bit is set. | |
1061 | */ | |
1062 | if (arm_is_el3_or_mon(env)) { | |
1063 | return cs->icc_ctlr_el3 & ICC_CTLR_EL3_EOIMODE_EL3; | |
1064 | } | |
1065 | if (arm_is_secure_below_el3(env)) { | |
1066 | return cs->icc_ctlr_el1[GICV3_S] & ICC_CTLR_EL1_EOIMODE; | |
1067 | } else { | |
1068 | return cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_EOIMODE; | |
1069 | } | |
1070 | } | |
1071 | ||
1072 | static int icc_highest_active_group(GICv3CPUState *cs) | |
1073 | { | |
1074 | /* Return the group with the highest priority active interrupt. | |
1075 | * We can do this by just comparing the APRs to see which one | |
1076 | * has the lowest set bit. | |
1077 | * (If more than one group is active at the same priority then | |
1078 | * we're in UNPREDICTABLE territory.) | |
1079 | */ | |
1080 | int i; | |
1081 | ||
1082 | for (i = 0; i < ARRAY_SIZE(cs->icc_apr[0]); i++) { | |
1083 | int g0ctz = ctz32(cs->icc_apr[GICV3_G0][i]); | |
1084 | int g1ctz = ctz32(cs->icc_apr[GICV3_G1][i]); | |
1085 | int g1nsctz = ctz32(cs->icc_apr[GICV3_G1NS][i]); | |
1086 | ||
1087 | if (g1nsctz < g0ctz && g1nsctz < g1ctz) { | |
1088 | return GICV3_G1NS; | |
1089 | } | |
1090 | if (g1ctz < g0ctz) { | |
1091 | return GICV3_G1; | |
1092 | } | |
1093 | if (g0ctz < 32) { | |
1094 | return GICV3_G0; | |
1095 | } | |
1096 | } | |
1097 | /* No set active bits? UNPREDICTABLE; return -1 so the caller | |
1098 | * ignores the spurious EOI attempt. | |
1099 | */ | |
1100 | return -1; | |
1101 | } | |
1102 | ||
1103 | static void icc_deactivate_irq(GICv3CPUState *cs, int irq) | |
1104 | { | |
1105 | if (irq < GIC_INTERNAL) { | |
1106 | cs->gicr_iactiver0 = deposit32(cs->gicr_iactiver0, irq, 1, 0); | |
1107 | gicv3_redist_update(cs); | |
1108 | } else { | |
1109 | gicv3_gicd_active_clear(cs->gic, irq); | |
1110 | gicv3_update(cs->gic, irq, 1); | |
1111 | } | |
1112 | } | |
1113 | ||
df313f48 PM |
1114 | static bool icv_eoi_split(CPUARMState *env, GICv3CPUState *cs) |
1115 | { | |
1116 | /* Return true if we should split priority drop and interrupt | |
1117 | * deactivation, ie whether the virtual EOIMode bit is set. | |
1118 | */ | |
1119 | return cs->ich_vmcr_el2 & ICH_VMCR_EL2_VEOIM; | |
1120 | } | |
1121 | ||
1122 | static int icv_find_active(GICv3CPUState *cs, int irq) | |
1123 | { | |
1124 | /* Given an interrupt number for an active interrupt, return the index | |
1125 | * of the corresponding list register, or -1 if there is no match. | |
1126 | * Corresponds to FindActiveVirtualInterrupt pseudocode. | |
1127 | */ | |
1128 | int i; | |
1129 | ||
1130 | for (i = 0; i < cs->num_list_regs; i++) { | |
1131 | uint64_t lr = cs->ich_lr_el2[i]; | |
1132 | ||
1133 | if ((lr & ICH_LR_EL2_STATE_ACTIVE_BIT) && ich_lr_vintid(lr) == irq) { | |
1134 | return i; | |
1135 | } | |
1136 | } | |
1137 | ||
1138 | return -1; | |
1139 | } | |
1140 | ||
1141 | static void icv_deactivate_irq(GICv3CPUState *cs, int idx) | |
1142 | { | |
1143 | /* Deactivate the interrupt in the specified list register index */ | |
1144 | uint64_t lr = cs->ich_lr_el2[idx]; | |
1145 | ||
1146 | if (lr & ICH_LR_EL2_HW) { | |
1147 | /* Deactivate the associated physical interrupt */ | |
1148 | int pirq = ich_lr_pintid(lr); | |
1149 | ||
1150 | if (pirq < INTID_SECURE) { | |
1151 | icc_deactivate_irq(cs, pirq); | |
1152 | } | |
1153 | } | |
1154 | ||
1155 | /* Clear the 'active' part of the state, so ActivePending->Pending | |
1156 | * and Active->Invalid. | |
1157 | */ | |
1158 | lr &= ~ICH_LR_EL2_STATE_ACTIVE_BIT; | |
1159 | cs->ich_lr_el2[idx] = lr; | |
1160 | } | |
1161 | ||
1162 | static void icv_increment_eoicount(GICv3CPUState *cs) | |
1163 | { | |
1164 | /* Increment the EOICOUNT field in ICH_HCR_EL2 */ | |
1165 | int eoicount = extract64(cs->ich_hcr_el2, ICH_HCR_EL2_EOICOUNT_SHIFT, | |
1166 | ICH_HCR_EL2_EOICOUNT_LENGTH); | |
1167 | ||
1168 | cs->ich_hcr_el2 = deposit64(cs->ich_hcr_el2, ICH_HCR_EL2_EOICOUNT_SHIFT, | |
1169 | ICH_HCR_EL2_EOICOUNT_LENGTH, eoicount + 1); | |
1170 | } | |
1171 | ||
b3b48f52 PM |
1172 | static int icv_drop_prio(GICv3CPUState *cs) |
1173 | { | |
1174 | /* Drop the priority of the currently active virtual interrupt | |
1175 | * (favouring group 0 if there is a set active bit at | |
1176 | * the same priority for both group 0 and group 1). | |
1177 | * Return the priority value for the bit we just cleared, | |
1178 | * or 0xff if no bits were set in the AP registers at all. | |
1179 | * Note that though the ich_apr[] are uint64_t only the low | |
1180 | * 32 bits are actually relevant. | |
1181 | */ | |
1182 | int i; | |
1183 | int aprmax = 1 << (cs->vprebits - 5); | |
1184 | ||
1185 | assert(aprmax <= ARRAY_SIZE(cs->ich_apr[0])); | |
1186 | ||
1187 | for (i = 0; i < aprmax; i++) { | |
1188 | uint64_t *papr0 = &cs->ich_apr[GICV3_G0][i]; | |
1189 | uint64_t *papr1 = &cs->ich_apr[GICV3_G1NS][i]; | |
1190 | int apr0count, apr1count; | |
1191 | ||
1192 | if (!*papr0 && !*papr1) { | |
1193 | continue; | |
1194 | } | |
1195 | ||
1196 | /* We can't just use the bit-twiddling hack icc_drop_prio() does | |
1197 | * because we need to return the bit number we cleared so | |
1198 | * it can be compared against the list register's priority field. | |
1199 | */ | |
1200 | apr0count = ctz32(*papr0); | |
1201 | apr1count = ctz32(*papr1); | |
1202 | ||
1203 | if (apr0count <= apr1count) { | |
1204 | *papr0 &= *papr0 - 1; | |
1205 | return (apr0count + i * 32) << (icv_min_vbpr(cs) + 1); | |
1206 | } else { | |
1207 | *papr1 &= *papr1 - 1; | |
1208 | return (apr1count + i * 32) << (icv_min_vbpr(cs) + 1); | |
1209 | } | |
1210 | } | |
1211 | return 0xff; | |
1212 | } | |
1213 | ||
df313f48 PM |
1214 | static void icv_dir_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1215 | uint64_t value) | |
1216 | { | |
1217 | /* Deactivate interrupt */ | |
1218 | GICv3CPUState *cs = icc_cs_from_env(env); | |
1219 | int idx; | |
1220 | int irq = value & 0xffffff; | |
1221 | ||
1222 | trace_gicv3_icv_dir_write(gicv3_redist_affid(cs), value); | |
1223 | ||
1224 | if (irq >= cs->gic->num_irq) { | |
1225 | /* Also catches special interrupt numbers and LPIs */ | |
1226 | return; | |
1227 | } | |
1228 | ||
1229 | if (!icv_eoi_split(env, cs)) { | |
1230 | return; | |
1231 | } | |
1232 | ||
1233 | idx = icv_find_active(cs, irq); | |
1234 | ||
1235 | if (idx < 0) { | |
1236 | /* No list register matching this, so increment the EOI count | |
1237 | * (might trigger a maintenance interrupt) | |
1238 | */ | |
1239 | icv_increment_eoicount(cs); | |
1240 | } else { | |
1241 | icv_deactivate_irq(cs, idx); | |
1242 | } | |
1243 | ||
1244 | gicv3_cpuif_virt_update(cs); | |
1245 | } | |
1246 | ||
b3b48f52 PM |
1247 | static void icv_eoir_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1248 | uint64_t value) | |
1249 | { | |
1250 | /* End of Interrupt */ | |
1251 | GICv3CPUState *cs = icc_cs_from_env(env); | |
1252 | int irq = value & 0xffffff; | |
1253 | int grp = ri->crm == 8 ? GICV3_G0 : GICV3_G1NS; | |
1254 | int idx, dropprio; | |
1255 | ||
1256 | trace_gicv3_icv_eoir_write(ri->crm == 8 ? 0 : 1, | |
1257 | gicv3_redist_affid(cs), value); | |
1258 | ||
1259 | if (irq >= cs->gic->num_irq) { | |
1260 | /* Also catches special interrupt numbers and LPIs */ | |
1261 | return; | |
1262 | } | |
1263 | ||
1264 | /* We implement the IMPDEF choice of "drop priority before doing | |
1265 | * error checks" (because that lets us avoid scanning the AP | |
1266 | * registers twice). | |
1267 | */ | |
1268 | dropprio = icv_drop_prio(cs); | |
1269 | if (dropprio == 0xff) { | |
1270 | /* No active interrupt. It is CONSTRAINED UNPREDICTABLE | |
1271 | * whether the list registers are checked in this | |
1272 | * situation; we choose not to. | |
1273 | */ | |
1274 | return; | |
1275 | } | |
1276 | ||
1277 | idx = icv_find_active(cs, irq); | |
1278 | ||
1279 | if (idx < 0) { | |
1280 | /* No valid list register corresponding to EOI ID */ | |
1281 | icv_increment_eoicount(cs); | |
1282 | } else { | |
1283 | uint64_t lr = cs->ich_lr_el2[idx]; | |
1284 | int thisgrp = (lr & ICH_LR_EL2_GROUP) ? GICV3_G1NS : GICV3_G0; | |
1285 | int lr_gprio = ich_lr_prio(lr) & icv_gprio_mask(cs, grp); | |
1286 | ||
1287 | if (thisgrp == grp && lr_gprio == dropprio) { | |
1288 | if (!icv_eoi_split(env, cs)) { | |
1289 | /* Priority drop and deactivate not split: deactivate irq now */ | |
1290 | icv_deactivate_irq(cs, idx); | |
1291 | } | |
1292 | } | |
1293 | } | |
1294 | ||
1295 | gicv3_cpuif_virt_update(cs); | |
1296 | } | |
1297 | ||
227a8653 PM |
1298 | static void icc_eoir_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1299 | uint64_t value) | |
1300 | { | |
1301 | /* End of Interrupt */ | |
1302 | GICv3CPUState *cs = icc_cs_from_env(env); | |
1303 | int irq = value & 0xffffff; | |
1304 | int grp; | |
1305 | ||
b3b48f52 PM |
1306 | if (icv_access(env, ri->crm == 8 ? HCR_FMO : HCR_IMO)) { |
1307 | icv_eoir_write(env, ri, value); | |
1308 | return; | |
1309 | } | |
1310 | ||
081b1b98 PM |
1311 | trace_gicv3_icc_eoir_write(ri->crm == 8 ? 0 : 1, |
1312 | gicv3_redist_affid(cs), value); | |
227a8653 PM |
1313 | |
1314 | if (ri->crm == 8) { | |
1315 | /* EOIR0 */ | |
1316 | grp = GICV3_G0; | |
1317 | } else { | |
1318 | /* EOIR1 */ | |
1319 | if (arm_is_secure(env)) { | |
1320 | grp = GICV3_G1; | |
1321 | } else { | |
1322 | grp = GICV3_G1NS; | |
1323 | } | |
1324 | } | |
1325 | ||
1326 | if (irq >= cs->gic->num_irq) { | |
1327 | /* This handles two cases: | |
1328 | * 1. If software writes the ID of a spurious interrupt [ie 1020-1023] | |
1329 | * to the GICC_EOIR, the GIC ignores that write. | |
1330 | * 2. If software writes the number of a non-existent interrupt | |
1331 | * this must be a subcase of "value written does not match the last | |
1332 | * valid interrupt value read from the Interrupt Acknowledge | |
1333 | * register" and so this is UNPREDICTABLE. We choose to ignore it. | |
1334 | */ | |
1335 | return; | |
1336 | } | |
1337 | ||
1338 | if (icc_highest_active_group(cs) != grp) { | |
1339 | return; | |
1340 | } | |
1341 | ||
1342 | icc_drop_prio(cs, grp); | |
1343 | ||
1344 | if (!icc_eoi_split(env, cs)) { | |
1345 | /* Priority drop and deactivate not split: deactivate irq now */ | |
1346 | icc_deactivate_irq(cs, irq); | |
1347 | } | |
1348 | } | |
1349 | ||
1350 | static uint64_t icc_hppir0_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
1351 | { | |
1352 | GICv3CPUState *cs = icc_cs_from_env(env); | |
df313f48 PM |
1353 | uint64_t value; |
1354 | ||
1355 | if (icv_access(env, HCR_FMO)) { | |
1356 | return icv_hppir_read(env, ri); | |
1357 | } | |
227a8653 | 1358 | |
df313f48 | 1359 | value = icc_hppir0_value(cs, env); |
227a8653 PM |
1360 | trace_gicv3_icc_hppir0_read(gicv3_redist_affid(cs), value); |
1361 | return value; | |
1362 | } | |
1363 | ||
1364 | static uint64_t icc_hppir1_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
1365 | { | |
1366 | GICv3CPUState *cs = icc_cs_from_env(env); | |
df313f48 PM |
1367 | uint64_t value; |
1368 | ||
1369 | if (icv_access(env, HCR_IMO)) { | |
1370 | return icv_hppir_read(env, ri); | |
1371 | } | |
227a8653 | 1372 | |
df313f48 | 1373 | value = icc_hppir1_value(cs, env); |
227a8653 PM |
1374 | trace_gicv3_icc_hppir1_read(gicv3_redist_affid(cs), value); |
1375 | return value; | |
1376 | } | |
1377 | ||
359fbe65 PM |
1378 | static uint64_t icc_bpr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
1379 | { | |
1380 | GICv3CPUState *cs = icc_cs_from_env(env); | |
1381 | int grp = (ri->crm == 8) ? GICV3_G0 : GICV3_G1; | |
1382 | bool satinc = false; | |
1383 | uint64_t bpr; | |
1384 | ||
77620ba6 PM |
1385 | if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) { |
1386 | return icv_bpr_read(env, ri); | |
1387 | } | |
1388 | ||
359fbe65 PM |
1389 | if (grp == GICV3_G1 && gicv3_use_ns_bank(env)) { |
1390 | grp = GICV3_G1NS; | |
1391 | } | |
1392 | ||
1393 | if (grp == GICV3_G1 && !arm_is_el3_or_mon(env) && | |
1394 | (cs->icc_ctlr_el1[GICV3_S] & ICC_CTLR_EL1_CBPR)) { | |
1395 | /* CBPR_EL1S means secure EL1 or AArch32 EL3 !Mon BPR1 accesses | |
1396 | * modify BPR0 | |
1397 | */ | |
1398 | grp = GICV3_G0; | |
1399 | } | |
1400 | ||
1401 | if (grp == GICV3_G1NS && arm_current_el(env) < 3 && | |
1402 | (cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_CBPR)) { | |
1403 | /* reads return bpr0 + 1 sat to 7, writes ignored */ | |
1404 | grp = GICV3_G0; | |
1405 | satinc = true; | |
1406 | } | |
1407 | ||
1408 | bpr = cs->icc_bpr[grp]; | |
1409 | if (satinc) { | |
1410 | bpr++; | |
1411 | bpr = MIN(bpr, 7); | |
1412 | } | |
1413 | ||
081b1b98 | 1414 | trace_gicv3_icc_bpr_read(ri->crm == 8 ? 0 : 1, gicv3_redist_affid(cs), bpr); |
359fbe65 PM |
1415 | |
1416 | return bpr; | |
1417 | } | |
1418 | ||
1419 | static void icc_bpr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1420 | uint64_t value) | |
1421 | { | |
1422 | GICv3CPUState *cs = icc_cs_from_env(env); | |
1423 | int grp = (ri->crm == 8) ? GICV3_G0 : GICV3_G1; | |
8193d461 | 1424 | uint64_t minval; |
359fbe65 | 1425 | |
77620ba6 PM |
1426 | if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) { |
1427 | icv_bpr_write(env, ri, value); | |
1428 | return; | |
1429 | } | |
1430 | ||
081b1b98 PM |
1431 | trace_gicv3_icc_bpr_write(ri->crm == 8 ? 0 : 1, |
1432 | gicv3_redist_affid(cs), value); | |
359fbe65 PM |
1433 | |
1434 | if (grp == GICV3_G1 && gicv3_use_ns_bank(env)) { | |
1435 | grp = GICV3_G1NS; | |
1436 | } | |
1437 | ||
1438 | if (grp == GICV3_G1 && !arm_is_el3_or_mon(env) && | |
1439 | (cs->icc_ctlr_el1[GICV3_S] & ICC_CTLR_EL1_CBPR)) { | |
1440 | /* CBPR_EL1S means secure EL1 or AArch32 EL3 !Mon BPR1 accesses | |
1441 | * modify BPR0 | |
1442 | */ | |
1443 | grp = GICV3_G0; | |
1444 | } | |
1445 | ||
1446 | if (grp == GICV3_G1NS && arm_current_el(env) < 3 && | |
1447 | (cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_CBPR)) { | |
1448 | /* reads return bpr0 + 1 sat to 7, writes ignored */ | |
1449 | return; | |
1450 | } | |
1451 | ||
8193d461 PM |
1452 | minval = (grp == GICV3_G1NS) ? GIC_MIN_BPR_NS : GIC_MIN_BPR; |
1453 | if (value < minval) { | |
1454 | value = minval; | |
1455 | } | |
1456 | ||
359fbe65 PM |
1457 | cs->icc_bpr[grp] = value & 7; |
1458 | gicv3_cpuif_update(cs); | |
1459 | } | |
1460 | ||
1461 | static uint64_t icc_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
1462 | { | |
1463 | GICv3CPUState *cs = icc_cs_from_env(env); | |
1464 | uint64_t value; | |
1465 | ||
1466 | int regno = ri->opc2 & 3; | |
887aae10 | 1467 | int grp = (ri->crm & 1) ? GICV3_G1 : GICV3_G0; |
359fbe65 | 1468 | |
77620ba6 PM |
1469 | if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) { |
1470 | return icv_ap_read(env, ri); | |
1471 | } | |
1472 | ||
359fbe65 PM |
1473 | if (grp == GICV3_G1 && gicv3_use_ns_bank(env)) { |
1474 | grp = GICV3_G1NS; | |
1475 | } | |
1476 | ||
1477 | value = cs->icc_apr[grp][regno]; | |
1478 | ||
081b1b98 | 1479 | trace_gicv3_icc_ap_read(ri->crm & 1, regno, gicv3_redist_affid(cs), value); |
359fbe65 PM |
1480 | return value; |
1481 | } | |
1482 | ||
1483 | static void icc_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1484 | uint64_t value) | |
1485 | { | |
1486 | GICv3CPUState *cs = icc_cs_from_env(env); | |
1487 | ||
1488 | int regno = ri->opc2 & 3; | |
887aae10 | 1489 | int grp = (ri->crm & 1) ? GICV3_G1 : GICV3_G0; |
359fbe65 | 1490 | |
77620ba6 PM |
1491 | if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) { |
1492 | icv_ap_write(env, ri, value); | |
1493 | return; | |
1494 | } | |
1495 | ||
081b1b98 | 1496 | trace_gicv3_icc_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value); |
359fbe65 PM |
1497 | |
1498 | if (grp == GICV3_G1 && gicv3_use_ns_bank(env)) { | |
1499 | grp = GICV3_G1NS; | |
1500 | } | |
1501 | ||
1502 | /* It's not possible to claim that a Non-secure interrupt is active | |
1503 | * at a priority outside the Non-secure range (128..255), since this | |
1504 | * would otherwise allow malicious NS code to block delivery of S interrupts | |
1505 | * by writing a bad value to these registers. | |
1506 | */ | |
1507 | if (grp == GICV3_G1NS && regno < 2 && arm_feature(env, ARM_FEATURE_EL3)) { | |
1508 | return; | |
1509 | } | |
1510 | ||
1511 | cs->icc_apr[grp][regno] = value & 0xFFFFFFFFU; | |
1512 | gicv3_cpuif_update(cs); | |
1513 | } | |
1514 | ||
227a8653 PM |
1515 | static void icc_dir_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1516 | uint64_t value) | |
1517 | { | |
1518 | /* Deactivate interrupt */ | |
1519 | GICv3CPUState *cs = icc_cs_from_env(env); | |
1520 | int irq = value & 0xffffff; | |
1521 | bool irq_is_secure, single_sec_state, irq_is_grp0; | |
1522 | bool route_fiq_to_el3, route_irq_to_el3, route_fiq_to_el2, route_irq_to_el2; | |
1523 | ||
df313f48 PM |
1524 | if (icv_access(env, HCR_FMO | HCR_IMO)) { |
1525 | icv_dir_write(env, ri, value); | |
1526 | return; | |
1527 | } | |
1528 | ||
227a8653 PM |
1529 | trace_gicv3_icc_dir_write(gicv3_redist_affid(cs), value); |
1530 | ||
1531 | if (irq >= cs->gic->num_irq) { | |
1532 | /* Also catches special interrupt numbers and LPIs */ | |
1533 | return; | |
1534 | } | |
1535 | ||
1536 | if (!icc_eoi_split(env, cs)) { | |
1537 | return; | |
1538 | } | |
1539 | ||
1540 | int grp = gicv3_irq_group(cs->gic, cs, irq); | |
1541 | ||
1542 | single_sec_state = cs->gic->gicd_ctlr & GICD_CTLR_DS; | |
1543 | irq_is_secure = !single_sec_state && (grp != GICV3_G1NS); | |
1544 | irq_is_grp0 = grp == GICV3_G0; | |
1545 | ||
1546 | /* Check whether we're allowed to deactivate this interrupt based | |
1547 | * on its group and the current CPU state. | |
1548 | * These checks are laid out to correspond to the spec's pseudocode. | |
1549 | */ | |
1550 | route_fiq_to_el3 = env->cp15.scr_el3 & SCR_FIQ; | |
1551 | route_irq_to_el3 = env->cp15.scr_el3 & SCR_IRQ; | |
1552 | /* No need to include !IsSecure in route_*_to_el2 as it's only | |
1553 | * tested in cases where we know !IsSecure is true. | |
1554 | */ | |
f7778444 RH |
1555 | uint64_t hcr_el2 = arm_hcr_el2_eff(env); |
1556 | route_fiq_to_el2 = hcr_el2 & HCR_FMO; | |
1557 | route_irq_to_el2 = hcr_el2 & HCR_IMO; | |
227a8653 PM |
1558 | |
1559 | switch (arm_current_el(env)) { | |
1560 | case 3: | |
1561 | break; | |
1562 | case 2: | |
1563 | if (single_sec_state && irq_is_grp0 && !route_fiq_to_el3) { | |
1564 | break; | |
1565 | } | |
1566 | if (!irq_is_secure && !irq_is_grp0 && !route_irq_to_el3) { | |
1567 | break; | |
1568 | } | |
1569 | return; | |
1570 | case 1: | |
1571 | if (!arm_is_secure_below_el3(env)) { | |
1572 | if (single_sec_state && irq_is_grp0 && | |
1573 | !route_fiq_to_el3 && !route_fiq_to_el2) { | |
1574 | break; | |
1575 | } | |
1576 | if (!irq_is_secure && !irq_is_grp0 && | |
1577 | !route_irq_to_el3 && !route_irq_to_el2) { | |
1578 | break; | |
1579 | } | |
1580 | } else { | |
1581 | if (irq_is_grp0 && !route_fiq_to_el3) { | |
1582 | break; | |
1583 | } | |
1584 | if (!irq_is_grp0 && | |
1585 | (!irq_is_secure || !single_sec_state) && | |
1586 | !route_irq_to_el3) { | |
1587 | break; | |
1588 | } | |
1589 | } | |
1590 | return; | |
1591 | default: | |
1592 | g_assert_not_reached(); | |
1593 | } | |
1594 | ||
1595 | icc_deactivate_irq(cs, irq); | |
1596 | } | |
1597 | ||
1598 | static uint64_t icc_rpr_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
1599 | { | |
1600 | GICv3CPUState *cs = icc_cs_from_env(env); | |
df313f48 PM |
1601 | int prio; |
1602 | ||
1603 | if (icv_access(env, HCR_FMO | HCR_IMO)) { | |
1604 | return icv_rpr_read(env, ri); | |
1605 | } | |
1606 | ||
1607 | prio = icc_highest_active_prio(cs); | |
227a8653 PM |
1608 | |
1609 | if (arm_feature(env, ARM_FEATURE_EL3) && | |
1610 | !arm_is_secure(env) && (env->cp15.scr_el3 & SCR_FIQ)) { | |
1611 | /* NS GIC access and Group 0 is inaccessible to NS */ | |
a2e2d7fc | 1612 | if ((prio & 0x80) == 0) { |
227a8653 PM |
1613 | /* NS mustn't see priorities in the Secure half of the range */ |
1614 | prio = 0; | |
1615 | } else if (prio != 0xff) { | |
1616 | /* Non-idle priority: show the Non-secure view of it */ | |
1617 | prio = (prio << 1) & 0xff; | |
1618 | } | |
1619 | } | |
1620 | ||
1621 | trace_gicv3_icc_rpr_read(gicv3_redist_affid(cs), prio); | |
1622 | return prio; | |
1623 | } | |
1624 | ||
b1a0eb77 PM |
1625 | static void icc_generate_sgi(CPUARMState *env, GICv3CPUState *cs, |
1626 | uint64_t value, int grp, bool ns) | |
1627 | { | |
1628 | GICv3State *s = cs->gic; | |
1629 | ||
1630 | /* Extract Aff3/Aff2/Aff1 and shift into the bottom 24 bits */ | |
1631 | uint64_t aff = extract64(value, 48, 8) << 16 | | |
1632 | extract64(value, 32, 8) << 8 | | |
1633 | extract64(value, 16, 8); | |
1634 | uint32_t targetlist = extract64(value, 0, 16); | |
1635 | uint32_t irq = extract64(value, 24, 4); | |
1636 | bool irm = extract64(value, 40, 1); | |
1637 | int i; | |
1638 | ||
1639 | if (grp == GICV3_G1 && s->gicd_ctlr & GICD_CTLR_DS) { | |
1640 | /* If GICD_CTLR.DS == 1, the Distributor treats Secure Group 1 | |
1641 | * interrupts as Group 0 interrupts and must send Secure Group 0 | |
1642 | * interrupts to the target CPUs. | |
1643 | */ | |
1644 | grp = GICV3_G0; | |
1645 | } | |
1646 | ||
1647 | trace_gicv3_icc_generate_sgi(gicv3_redist_affid(cs), irq, irm, | |
1648 | aff, targetlist); | |
1649 | ||
1650 | for (i = 0; i < s->num_cpu; i++) { | |
1651 | GICv3CPUState *ocs = &s->cpu[i]; | |
1652 | ||
1653 | if (irm) { | |
1654 | /* IRM == 1 : route to all CPUs except self */ | |
1655 | if (cs == ocs) { | |
1656 | continue; | |
1657 | } | |
1658 | } else { | |
1659 | /* IRM == 0 : route to Aff3.Aff2.Aff1.n for all n in [0..15] | |
1660 | * where the corresponding bit is set in targetlist | |
1661 | */ | |
1662 | int aff0; | |
1663 | ||
1664 | if (ocs->gicr_typer >> 40 != aff) { | |
1665 | continue; | |
1666 | } | |
1667 | aff0 = extract64(ocs->gicr_typer, 32, 8); | |
1668 | if (aff0 > 15 || extract32(targetlist, aff0, 1) == 0) { | |
1669 | continue; | |
1670 | } | |
1671 | } | |
1672 | ||
1673 | /* The redistributor will check against its own GICR_NSACR as needed */ | |
1674 | gicv3_redist_send_sgi(ocs, grp, irq, ns); | |
1675 | } | |
1676 | } | |
1677 | ||
1678 | static void icc_sgi0r_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1679 | uint64_t value) | |
1680 | { | |
1681 | /* Generate Secure Group 0 SGI. */ | |
1682 | GICv3CPUState *cs = icc_cs_from_env(env); | |
1683 | bool ns = !arm_is_secure(env); | |
1684 | ||
1685 | icc_generate_sgi(env, cs, value, GICV3_G0, ns); | |
1686 | } | |
1687 | ||
1688 | static void icc_sgi1r_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1689 | uint64_t value) | |
1690 | { | |
1691 | /* Generate Group 1 SGI for the current Security state */ | |
1692 | GICv3CPUState *cs = icc_cs_from_env(env); | |
1693 | int grp; | |
1694 | bool ns = !arm_is_secure(env); | |
1695 | ||
1696 | grp = ns ? GICV3_G1NS : GICV3_G1; | |
1697 | icc_generate_sgi(env, cs, value, grp, ns); | |
1698 | } | |
1699 | ||
1700 | static void icc_asgi1r_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1701 | uint64_t value) | |
1702 | { | |
1703 | /* Generate Group 1 SGI for the Security state that is not | |
1704 | * the current state | |
1705 | */ | |
1706 | GICv3CPUState *cs = icc_cs_from_env(env); | |
1707 | int grp; | |
1708 | bool ns = !arm_is_secure(env); | |
1709 | ||
1710 | grp = ns ? GICV3_G1 : GICV3_G1NS; | |
1711 | icc_generate_sgi(env, cs, value, grp, ns); | |
1712 | } | |
1713 | ||
359fbe65 PM |
1714 | static uint64_t icc_igrpen_read(CPUARMState *env, const ARMCPRegInfo *ri) |
1715 | { | |
1716 | GICv3CPUState *cs = icc_cs_from_env(env); | |
1717 | int grp = ri->opc2 & 1 ? GICV3_G1 : GICV3_G0; | |
1718 | uint64_t value; | |
1719 | ||
77620ba6 PM |
1720 | if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) { |
1721 | return icv_igrpen_read(env, ri); | |
1722 | } | |
1723 | ||
359fbe65 PM |
1724 | if (grp == GICV3_G1 && gicv3_use_ns_bank(env)) { |
1725 | grp = GICV3_G1NS; | |
1726 | } | |
1727 | ||
1728 | value = cs->icc_igrpen[grp]; | |
081b1b98 PM |
1729 | trace_gicv3_icc_igrpen_read(ri->opc2 & 1 ? 1 : 0, |
1730 | gicv3_redist_affid(cs), value); | |
359fbe65 PM |
1731 | return value; |
1732 | } | |
1733 | ||
1734 | static void icc_igrpen_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1735 | uint64_t value) | |
1736 | { | |
1737 | GICv3CPUState *cs = icc_cs_from_env(env); | |
1738 | int grp = ri->opc2 & 1 ? GICV3_G1 : GICV3_G0; | |
1739 | ||
77620ba6 PM |
1740 | if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) { |
1741 | icv_igrpen_write(env, ri, value); | |
1742 | return; | |
1743 | } | |
1744 | ||
081b1b98 PM |
1745 | trace_gicv3_icc_igrpen_write(ri->opc2 & 1 ? 1 : 0, |
1746 | gicv3_redist_affid(cs), value); | |
359fbe65 PM |
1747 | |
1748 | if (grp == GICV3_G1 && gicv3_use_ns_bank(env)) { | |
1749 | grp = GICV3_G1NS; | |
1750 | } | |
1751 | ||
1752 | cs->icc_igrpen[grp] = value & ICC_IGRPEN_ENABLE; | |
1753 | gicv3_cpuif_update(cs); | |
1754 | } | |
1755 | ||
1756 | static uint64_t icc_igrpen1_el3_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
1757 | { | |
1758 | GICv3CPUState *cs = icc_cs_from_env(env); | |
081b1b98 | 1759 | uint64_t value; |
359fbe65 PM |
1760 | |
1761 | /* IGRPEN1_EL3 bits 0 and 1 are r/w aliases into IGRPEN1_EL1 NS and S */ | |
081b1b98 PM |
1762 | value = cs->icc_igrpen[GICV3_G1NS] | (cs->icc_igrpen[GICV3_G1] << 1); |
1763 | trace_gicv3_icc_igrpen1_el3_read(gicv3_redist_affid(cs), value); | |
1764 | return value; | |
359fbe65 PM |
1765 | } |
1766 | ||
1767 | static void icc_igrpen1_el3_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1768 | uint64_t value) | |
1769 | { | |
1770 | GICv3CPUState *cs = icc_cs_from_env(env); | |
1771 | ||
1772 | trace_gicv3_icc_igrpen1_el3_write(gicv3_redist_affid(cs), value); | |
1773 | ||
1774 | /* IGRPEN1_EL3 bits 0 and 1 are r/w aliases into IGRPEN1_EL1 NS and S */ | |
1775 | cs->icc_igrpen[GICV3_G1NS] = extract32(value, 0, 1); | |
1776 | cs->icc_igrpen[GICV3_G1] = extract32(value, 1, 1); | |
1777 | gicv3_cpuif_update(cs); | |
1778 | } | |
1779 | ||
1780 | static uint64_t icc_ctlr_el1_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
1781 | { | |
1782 | GICv3CPUState *cs = icc_cs_from_env(env); | |
1783 | int bank = gicv3_use_ns_bank(env) ? GICV3_NS : GICV3_S; | |
1784 | uint64_t value; | |
1785 | ||
77620ba6 PM |
1786 | if (icv_access(env, HCR_FMO | HCR_IMO)) { |
1787 | return icv_ctlr_read(env, ri); | |
1788 | } | |
1789 | ||
359fbe65 PM |
1790 | value = cs->icc_ctlr_el1[bank]; |
1791 | trace_gicv3_icc_ctlr_read(gicv3_redist_affid(cs), value); | |
1792 | return value; | |
1793 | } | |
1794 | ||
1795 | static void icc_ctlr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1796 | uint64_t value) | |
1797 | { | |
1798 | GICv3CPUState *cs = icc_cs_from_env(env); | |
1799 | int bank = gicv3_use_ns_bank(env) ? GICV3_NS : GICV3_S; | |
1800 | uint64_t mask; | |
1801 | ||
77620ba6 PM |
1802 | if (icv_access(env, HCR_FMO | HCR_IMO)) { |
1803 | icv_ctlr_write(env, ri, value); | |
1804 | return; | |
1805 | } | |
1806 | ||
359fbe65 PM |
1807 | trace_gicv3_icc_ctlr_write(gicv3_redist_affid(cs), value); |
1808 | ||
1809 | /* Only CBPR and EOIMODE can be RW; | |
1810 | * for us PMHE is RAZ/WI (we don't implement 1-of-N interrupts or | |
1811 | * the asseciated priority-based routing of them); | |
1812 | * if EL3 is implemented and GICD_CTLR.DS == 0, then PMHE and CBPR are RO. | |
1813 | */ | |
1814 | if (arm_feature(env, ARM_FEATURE_EL3) && | |
1815 | ((cs->gic->gicd_ctlr & GICD_CTLR_DS) == 0)) { | |
1816 | mask = ICC_CTLR_EL1_EOIMODE; | |
1817 | } else { | |
1818 | mask = ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE; | |
1819 | } | |
1820 | ||
1821 | cs->icc_ctlr_el1[bank] &= ~mask; | |
1822 | cs->icc_ctlr_el1[bank] |= (value & mask); | |
1823 | gicv3_cpuif_update(cs); | |
1824 | } | |
1825 | ||
1826 | ||
1827 | static uint64_t icc_ctlr_el3_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
1828 | { | |
1829 | GICv3CPUState *cs = icc_cs_from_env(env); | |
1830 | uint64_t value; | |
1831 | ||
1832 | value = cs->icc_ctlr_el3; | |
1833 | if (cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_EOIMODE) { | |
1834 | value |= ICC_CTLR_EL3_EOIMODE_EL1NS; | |
1835 | } | |
1836 | if (cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_CBPR) { | |
1837 | value |= ICC_CTLR_EL3_CBPR_EL1NS; | |
1838 | } | |
1839 | if (cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_EOIMODE) { | |
1840 | value |= ICC_CTLR_EL3_EOIMODE_EL1S; | |
1841 | } | |
1842 | if (cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_CBPR) { | |
1843 | value |= ICC_CTLR_EL3_CBPR_EL1S; | |
1844 | } | |
1845 | ||
1846 | trace_gicv3_icc_ctlr_el3_read(gicv3_redist_affid(cs), value); | |
1847 | return value; | |
1848 | } | |
1849 | ||
1850 | static void icc_ctlr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1851 | uint64_t value) | |
1852 | { | |
1853 | GICv3CPUState *cs = icc_cs_from_env(env); | |
1854 | uint64_t mask; | |
1855 | ||
1856 | trace_gicv3_icc_ctlr_el3_write(gicv3_redist_affid(cs), value); | |
1857 | ||
1858 | /* *_EL1NS and *_EL1S bits are aliases into the ICC_CTLR_EL1 bits. */ | |
09380dd1 | 1859 | cs->icc_ctlr_el1[GICV3_NS] &= ~(ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE); |
359fbe65 PM |
1860 | if (value & ICC_CTLR_EL3_EOIMODE_EL1NS) { |
1861 | cs->icc_ctlr_el1[GICV3_NS] |= ICC_CTLR_EL1_EOIMODE; | |
1862 | } | |
1863 | if (value & ICC_CTLR_EL3_CBPR_EL1NS) { | |
1864 | cs->icc_ctlr_el1[GICV3_NS] |= ICC_CTLR_EL1_CBPR; | |
1865 | } | |
1866 | ||
09380dd1 | 1867 | cs->icc_ctlr_el1[GICV3_S] &= ~(ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE); |
359fbe65 PM |
1868 | if (value & ICC_CTLR_EL3_EOIMODE_EL1S) { |
1869 | cs->icc_ctlr_el1[GICV3_S] |= ICC_CTLR_EL1_EOIMODE; | |
1870 | } | |
1871 | if (value & ICC_CTLR_EL3_CBPR_EL1S) { | |
1872 | cs->icc_ctlr_el1[GICV3_S] |= ICC_CTLR_EL1_CBPR; | |
1873 | } | |
1874 | ||
1875 | /* The only bit stored in icc_ctlr_el3 which is writeable is EOIMODE_EL3: */ | |
1876 | mask = ICC_CTLR_EL3_EOIMODE_EL3; | |
1877 | ||
1878 | cs->icc_ctlr_el3 &= ~mask; | |
1879 | cs->icc_ctlr_el3 |= (value & mask); | |
1880 | gicv3_cpuif_update(cs); | |
1881 | } | |
1882 | ||
1883 | static CPAccessResult gicv3_irqfiq_access(CPUARMState *env, | |
1884 | const ARMCPRegInfo *ri, bool isread) | |
1885 | { | |
1886 | CPAccessResult r = CP_ACCESS_OK; | |
86830554 PM |
1887 | GICv3CPUState *cs = icc_cs_from_env(env); |
1888 | int el = arm_current_el(env); | |
1889 | ||
1890 | if ((cs->ich_hcr_el2 & ICH_HCR_EL2_TC) && | |
1891 | el == 1 && !arm_is_secure_below_el3(env)) { | |
1892 | /* Takes priority over a possible EL3 trap */ | |
1893 | return CP_ACCESS_TRAP_EL2; | |
1894 | } | |
359fbe65 PM |
1895 | |
1896 | if ((env->cp15.scr_el3 & (SCR_FIQ | SCR_IRQ)) == (SCR_FIQ | SCR_IRQ)) { | |
86830554 | 1897 | switch (el) { |
359fbe65 | 1898 | case 1: |
f7778444 RH |
1899 | /* Note that arm_hcr_el2_eff takes secure state into account. */ |
1900 | if ((arm_hcr_el2_eff(env) & (HCR_IMO | HCR_FMO)) == 0) { | |
359fbe65 PM |
1901 | r = CP_ACCESS_TRAP_EL3; |
1902 | } | |
1903 | break; | |
1904 | case 2: | |
1905 | r = CP_ACCESS_TRAP_EL3; | |
1906 | break; | |
1907 | case 3: | |
1908 | if (!is_a64(env) && !arm_is_el3_or_mon(env)) { | |
1909 | r = CP_ACCESS_TRAP_EL3; | |
1910 | } | |
92b30c2f | 1911 | break; |
359fbe65 PM |
1912 | default: |
1913 | g_assert_not_reached(); | |
1914 | } | |
1915 | } | |
1916 | ||
1917 | if (r == CP_ACCESS_TRAP_EL3 && !arm_el_is_aa64(env, 3)) { | |
1918 | r = CP_ACCESS_TRAP; | |
1919 | } | |
1920 | return r; | |
1921 | } | |
1922 | ||
86830554 PM |
1923 | static CPAccessResult gicv3_dir_access(CPUARMState *env, |
1924 | const ARMCPRegInfo *ri, bool isread) | |
1925 | { | |
1926 | GICv3CPUState *cs = icc_cs_from_env(env); | |
1927 | ||
1928 | if ((cs->ich_hcr_el2 & ICH_HCR_EL2_TDIR) && | |
1929 | arm_current_el(env) == 1 && !arm_is_secure_below_el3(env)) { | |
1930 | /* Takes priority over a possible EL3 trap */ | |
1931 | return CP_ACCESS_TRAP_EL2; | |
1932 | } | |
1933 | ||
1934 | return gicv3_irqfiq_access(env, ri, isread); | |
1935 | } | |
1936 | ||
1937 | static CPAccessResult gicv3_sgi_access(CPUARMState *env, | |
1938 | const ARMCPRegInfo *ri, bool isread) | |
1939 | { | |
f7778444 RH |
1940 | if (arm_current_el(env) == 1 && |
1941 | (arm_hcr_el2_eff(env) & (HCR_IMO | HCR_FMO)) != 0) { | |
86830554 PM |
1942 | /* Takes priority over a possible EL3 trap */ |
1943 | return CP_ACCESS_TRAP_EL2; | |
1944 | } | |
1945 | ||
1946 | return gicv3_irqfiq_access(env, ri, isread); | |
1947 | } | |
1948 | ||
359fbe65 PM |
1949 | static CPAccessResult gicv3_fiq_access(CPUARMState *env, |
1950 | const ARMCPRegInfo *ri, bool isread) | |
1951 | { | |
1952 | CPAccessResult r = CP_ACCESS_OK; | |
86830554 PM |
1953 | GICv3CPUState *cs = icc_cs_from_env(env); |
1954 | int el = arm_current_el(env); | |
1955 | ||
1956 | if ((cs->ich_hcr_el2 & ICH_HCR_EL2_TALL0) && | |
1957 | el == 1 && !arm_is_secure_below_el3(env)) { | |
1958 | /* Takes priority over a possible EL3 trap */ | |
1959 | return CP_ACCESS_TRAP_EL2; | |
1960 | } | |
359fbe65 PM |
1961 | |
1962 | if (env->cp15.scr_el3 & SCR_FIQ) { | |
86830554 | 1963 | switch (el) { |
359fbe65 | 1964 | case 1: |
f7778444 | 1965 | if ((arm_hcr_el2_eff(env) & HCR_FMO) == 0) { |
359fbe65 PM |
1966 | r = CP_ACCESS_TRAP_EL3; |
1967 | } | |
1968 | break; | |
1969 | case 2: | |
1970 | r = CP_ACCESS_TRAP_EL3; | |
1971 | break; | |
1972 | case 3: | |
1973 | if (!is_a64(env) && !arm_is_el3_or_mon(env)) { | |
1974 | r = CP_ACCESS_TRAP_EL3; | |
1975 | } | |
92b30c2f | 1976 | break; |
359fbe65 PM |
1977 | default: |
1978 | g_assert_not_reached(); | |
1979 | } | |
1980 | } | |
1981 | ||
1982 | if (r == CP_ACCESS_TRAP_EL3 && !arm_el_is_aa64(env, 3)) { | |
1983 | r = CP_ACCESS_TRAP; | |
1984 | } | |
1985 | return r; | |
1986 | } | |
1987 | ||
1988 | static CPAccessResult gicv3_irq_access(CPUARMState *env, | |
1989 | const ARMCPRegInfo *ri, bool isread) | |
1990 | { | |
1991 | CPAccessResult r = CP_ACCESS_OK; | |
86830554 PM |
1992 | GICv3CPUState *cs = icc_cs_from_env(env); |
1993 | int el = arm_current_el(env); | |
1994 | ||
1995 | if ((cs->ich_hcr_el2 & ICH_HCR_EL2_TALL1) && | |
1996 | el == 1 && !arm_is_secure_below_el3(env)) { | |
1997 | /* Takes priority over a possible EL3 trap */ | |
1998 | return CP_ACCESS_TRAP_EL2; | |
1999 | } | |
359fbe65 PM |
2000 | |
2001 | if (env->cp15.scr_el3 & SCR_IRQ) { | |
86830554 | 2002 | switch (el) { |
359fbe65 | 2003 | case 1: |
f7778444 | 2004 | if ((arm_hcr_el2_eff(env) & HCR_IMO) == 0) { |
359fbe65 PM |
2005 | r = CP_ACCESS_TRAP_EL3; |
2006 | } | |
2007 | break; | |
2008 | case 2: | |
2009 | r = CP_ACCESS_TRAP_EL3; | |
2010 | break; | |
2011 | case 3: | |
2012 | if (!is_a64(env) && !arm_is_el3_or_mon(env)) { | |
2013 | r = CP_ACCESS_TRAP_EL3; | |
2014 | } | |
2015 | break; | |
2016 | default: | |
2017 | g_assert_not_reached(); | |
2018 | } | |
2019 | } | |
2020 | ||
2021 | if (r == CP_ACCESS_TRAP_EL3 && !arm_el_is_aa64(env, 3)) { | |
2022 | r = CP_ACCESS_TRAP; | |
2023 | } | |
2024 | return r; | |
2025 | } | |
2026 | ||
2027 | static void icc_reset(CPUARMState *env, const ARMCPRegInfo *ri) | |
2028 | { | |
2029 | GICv3CPUState *cs = icc_cs_from_env(env); | |
2030 | ||
2031 | cs->icc_ctlr_el1[GICV3_S] = ICC_CTLR_EL1_A3V | | |
2032 | (1 << ICC_CTLR_EL1_IDBITS_SHIFT) | | |
2033 | (7 << ICC_CTLR_EL1_PRIBITS_SHIFT); | |
2034 | cs->icc_ctlr_el1[GICV3_NS] = ICC_CTLR_EL1_A3V | | |
2035 | (1 << ICC_CTLR_EL1_IDBITS_SHIFT) | | |
2036 | (7 << ICC_CTLR_EL1_PRIBITS_SHIFT); | |
2037 | cs->icc_pmr_el1 = 0; | |
2038 | cs->icc_bpr[GICV3_G0] = GIC_MIN_BPR; | |
2039 | cs->icc_bpr[GICV3_G1] = GIC_MIN_BPR; | |
64175afc | 2040 | cs->icc_bpr[GICV3_G1NS] = GIC_MIN_BPR_NS; |
359fbe65 PM |
2041 | memset(cs->icc_apr, 0, sizeof(cs->icc_apr)); |
2042 | memset(cs->icc_igrpen, 0, sizeof(cs->icc_igrpen)); | |
2043 | cs->icc_ctlr_el3 = ICC_CTLR_EL3_NDS | ICC_CTLR_EL3_A3V | | |
2044 | (1 << ICC_CTLR_EL3_IDBITS_SHIFT) | | |
2045 | (7 << ICC_CTLR_EL3_PRIBITS_SHIFT); | |
4eb833b5 PM |
2046 | |
2047 | memset(cs->ich_apr, 0, sizeof(cs->ich_apr)); | |
2048 | cs->ich_hcr_el2 = 0; | |
2049 | memset(cs->ich_lr_el2, 0, sizeof(cs->ich_lr_el2)); | |
2050 | cs->ich_vmcr_el2 = ICH_VMCR_EL2_VFIQEN | | |
f5dc1b77 | 2051 | ((icv_min_vbpr(cs) + 1) << ICH_VMCR_EL2_VBPR1_SHIFT) | |
4eb833b5 | 2052 | (icv_min_vbpr(cs) << ICH_VMCR_EL2_VBPR0_SHIFT); |
359fbe65 PM |
2053 | } |
2054 | ||
2055 | static const ARMCPRegInfo gicv3_cpuif_reginfo[] = { | |
2056 | { .name = "ICC_PMR_EL1", .state = ARM_CP_STATE_BOTH, | |
2057 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 6, .opc2 = 0, | |
2058 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2059 | .access = PL1_RW, .accessfn = gicv3_irqfiq_access, | |
2060 | .readfn = icc_pmr_read, | |
2061 | .writefn = icc_pmr_write, | |
2062 | /* We hang the whole cpu interface reset routine off here | |
2063 | * rather than parcelling it out into one little function | |
2064 | * per register | |
2065 | */ | |
2066 | .resetfn = icc_reset, | |
2067 | }, | |
227a8653 PM |
2068 | { .name = "ICC_IAR0_EL1", .state = ARM_CP_STATE_BOTH, |
2069 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 0, | |
2070 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2071 | .access = PL1_R, .accessfn = gicv3_fiq_access, | |
2072 | .readfn = icc_iar0_read, | |
2073 | }, | |
2074 | { .name = "ICC_EOIR0_EL1", .state = ARM_CP_STATE_BOTH, | |
2075 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 1, | |
2076 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2077 | .access = PL1_W, .accessfn = gicv3_fiq_access, | |
2078 | .writefn = icc_eoir_write, | |
2079 | }, | |
2080 | { .name = "ICC_HPPIR0_EL1", .state = ARM_CP_STATE_BOTH, | |
2081 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 2, | |
2082 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2083 | .access = PL1_R, .accessfn = gicv3_fiq_access, | |
2084 | .readfn = icc_hppir0_read, | |
2085 | }, | |
359fbe65 PM |
2086 | { .name = "ICC_BPR0_EL1", .state = ARM_CP_STATE_BOTH, |
2087 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 3, | |
2088 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2089 | .access = PL1_RW, .accessfn = gicv3_fiq_access, | |
e971fa04 | 2090 | .readfn = icc_bpr_read, |
359fbe65 PM |
2091 | .writefn = icc_bpr_write, |
2092 | }, | |
2093 | { .name = "ICC_AP0R0_EL1", .state = ARM_CP_STATE_BOTH, | |
2094 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 4, | |
2095 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2096 | .access = PL1_RW, .accessfn = gicv3_fiq_access, | |
e971fa04 | 2097 | .readfn = icc_ap_read, |
359fbe65 PM |
2098 | .writefn = icc_ap_write, |
2099 | }, | |
2100 | { .name = "ICC_AP0R1_EL1", .state = ARM_CP_STATE_BOTH, | |
2101 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 5, | |
2102 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2103 | .access = PL1_RW, .accessfn = gicv3_fiq_access, | |
e971fa04 | 2104 | .readfn = icc_ap_read, |
359fbe65 PM |
2105 | .writefn = icc_ap_write, |
2106 | }, | |
2107 | { .name = "ICC_AP0R2_EL1", .state = ARM_CP_STATE_BOTH, | |
2108 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 6, | |
2109 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2110 | .access = PL1_RW, .accessfn = gicv3_fiq_access, | |
e971fa04 | 2111 | .readfn = icc_ap_read, |
359fbe65 PM |
2112 | .writefn = icc_ap_write, |
2113 | }, | |
2114 | { .name = "ICC_AP0R3_EL1", .state = ARM_CP_STATE_BOTH, | |
2115 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 7, | |
2116 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2117 | .access = PL1_RW, .accessfn = gicv3_fiq_access, | |
e971fa04 | 2118 | .readfn = icc_ap_read, |
359fbe65 PM |
2119 | .writefn = icc_ap_write, |
2120 | }, | |
2121 | /* All the ICC_AP1R*_EL1 registers are banked */ | |
2122 | { .name = "ICC_AP1R0_EL1", .state = ARM_CP_STATE_BOTH, | |
2123 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 9, .opc2 = 0, | |
2124 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2125 | .access = PL1_RW, .accessfn = gicv3_irq_access, | |
2126 | .readfn = icc_ap_read, | |
2127 | .writefn = icc_ap_write, | |
2128 | }, | |
2129 | { .name = "ICC_AP1R1_EL1", .state = ARM_CP_STATE_BOTH, | |
2130 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 9, .opc2 = 1, | |
2131 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2132 | .access = PL1_RW, .accessfn = gicv3_irq_access, | |
2133 | .readfn = icc_ap_read, | |
2134 | .writefn = icc_ap_write, | |
2135 | }, | |
2136 | { .name = "ICC_AP1R2_EL1", .state = ARM_CP_STATE_BOTH, | |
2137 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 9, .opc2 = 2, | |
2138 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2139 | .access = PL1_RW, .accessfn = gicv3_irq_access, | |
2140 | .readfn = icc_ap_read, | |
2141 | .writefn = icc_ap_write, | |
2142 | }, | |
2143 | { .name = "ICC_AP1R3_EL1", .state = ARM_CP_STATE_BOTH, | |
2144 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 9, .opc2 = 3, | |
2145 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2146 | .access = PL1_RW, .accessfn = gicv3_irq_access, | |
2147 | .readfn = icc_ap_read, | |
2148 | .writefn = icc_ap_write, | |
2149 | }, | |
227a8653 PM |
2150 | { .name = "ICC_DIR_EL1", .state = ARM_CP_STATE_BOTH, |
2151 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 11, .opc2 = 1, | |
2152 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
86830554 | 2153 | .access = PL1_W, .accessfn = gicv3_dir_access, |
227a8653 PM |
2154 | .writefn = icc_dir_write, |
2155 | }, | |
2156 | { .name = "ICC_RPR_EL1", .state = ARM_CP_STATE_BOTH, | |
2157 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 11, .opc2 = 3, | |
2158 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2159 | .access = PL1_R, .accessfn = gicv3_irqfiq_access, | |
2160 | .readfn = icc_rpr_read, | |
2161 | }, | |
b1a0eb77 PM |
2162 | { .name = "ICC_SGI1R_EL1", .state = ARM_CP_STATE_AA64, |
2163 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 11, .opc2 = 5, | |
2164 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
86830554 | 2165 | .access = PL1_W, .accessfn = gicv3_sgi_access, |
b1a0eb77 PM |
2166 | .writefn = icc_sgi1r_write, |
2167 | }, | |
2168 | { .name = "ICC_SGI1R", | |
2169 | .cp = 15, .opc1 = 0, .crm = 12, | |
2170 | .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_RAW, | |
86830554 | 2171 | .access = PL1_W, .accessfn = gicv3_sgi_access, |
b1a0eb77 PM |
2172 | .writefn = icc_sgi1r_write, |
2173 | }, | |
2174 | { .name = "ICC_ASGI1R_EL1", .state = ARM_CP_STATE_AA64, | |
2175 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 11, .opc2 = 6, | |
2176 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
86830554 | 2177 | .access = PL1_W, .accessfn = gicv3_sgi_access, |
b1a0eb77 PM |
2178 | .writefn = icc_asgi1r_write, |
2179 | }, | |
2180 | { .name = "ICC_ASGI1R", | |
2181 | .cp = 15, .opc1 = 1, .crm = 12, | |
2182 | .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_RAW, | |
86830554 | 2183 | .access = PL1_W, .accessfn = gicv3_sgi_access, |
b1a0eb77 PM |
2184 | .writefn = icc_asgi1r_write, |
2185 | }, | |
2186 | { .name = "ICC_SGI0R_EL1", .state = ARM_CP_STATE_AA64, | |
2187 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 11, .opc2 = 7, | |
2188 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
86830554 | 2189 | .access = PL1_W, .accessfn = gicv3_sgi_access, |
b1a0eb77 PM |
2190 | .writefn = icc_sgi0r_write, |
2191 | }, | |
2192 | { .name = "ICC_SGI0R", | |
2193 | .cp = 15, .opc1 = 2, .crm = 12, | |
2194 | .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_RAW, | |
86830554 | 2195 | .access = PL1_W, .accessfn = gicv3_sgi_access, |
b1a0eb77 PM |
2196 | .writefn = icc_sgi0r_write, |
2197 | }, | |
227a8653 PM |
2198 | { .name = "ICC_IAR1_EL1", .state = ARM_CP_STATE_BOTH, |
2199 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 0, | |
2200 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2201 | .access = PL1_R, .accessfn = gicv3_irq_access, | |
2202 | .readfn = icc_iar1_read, | |
2203 | }, | |
2204 | { .name = "ICC_EOIR1_EL1", .state = ARM_CP_STATE_BOTH, | |
2205 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 1, | |
2206 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2207 | .access = PL1_W, .accessfn = gicv3_irq_access, | |
2208 | .writefn = icc_eoir_write, | |
2209 | }, | |
2210 | { .name = "ICC_HPPIR1_EL1", .state = ARM_CP_STATE_BOTH, | |
2211 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 2, | |
2212 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2213 | .access = PL1_R, .accessfn = gicv3_irq_access, | |
2214 | .readfn = icc_hppir1_read, | |
2215 | }, | |
359fbe65 PM |
2216 | /* This register is banked */ |
2217 | { .name = "ICC_BPR1_EL1", .state = ARM_CP_STATE_BOTH, | |
2218 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 3, | |
2219 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2220 | .access = PL1_RW, .accessfn = gicv3_irq_access, | |
2221 | .readfn = icc_bpr_read, | |
2222 | .writefn = icc_bpr_write, | |
2223 | }, | |
2224 | /* This register is banked */ | |
2225 | { .name = "ICC_CTLR_EL1", .state = ARM_CP_STATE_BOTH, | |
2226 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 4, | |
2227 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2228 | .access = PL1_RW, .accessfn = gicv3_irqfiq_access, | |
2229 | .readfn = icc_ctlr_el1_read, | |
2230 | .writefn = icc_ctlr_el1_write, | |
2231 | }, | |
2232 | { .name = "ICC_SRE_EL1", .state = ARM_CP_STATE_BOTH, | |
2233 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 5, | |
2234 | .type = ARM_CP_NO_RAW | ARM_CP_CONST, | |
2235 | .access = PL1_RW, | |
2236 | /* We don't support IRQ/FIQ bypass and system registers are | |
2237 | * always enabled, so all our bits are RAZ/WI or RAO/WI. | |
2238 | * This register is banked but since it's constant we don't | |
2239 | * need to do anything special. | |
2240 | */ | |
2241 | .resetvalue = 0x7, | |
2242 | }, | |
2243 | { .name = "ICC_IGRPEN0_EL1", .state = ARM_CP_STATE_BOTH, | |
2244 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 6, | |
2245 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2246 | .access = PL1_RW, .accessfn = gicv3_fiq_access, | |
e971fa04 | 2247 | .readfn = icc_igrpen_read, |
359fbe65 PM |
2248 | .writefn = icc_igrpen_write, |
2249 | }, | |
2250 | /* This register is banked */ | |
2251 | { .name = "ICC_IGRPEN1_EL1", .state = ARM_CP_STATE_BOTH, | |
2252 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 7, | |
2253 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2254 | .access = PL1_RW, .accessfn = gicv3_irq_access, | |
2255 | .readfn = icc_igrpen_read, | |
2256 | .writefn = icc_igrpen_write, | |
2257 | }, | |
2258 | { .name = "ICC_SRE_EL2", .state = ARM_CP_STATE_BOTH, | |
2259 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 9, .opc2 = 5, | |
2260 | .type = ARM_CP_NO_RAW | ARM_CP_CONST, | |
2261 | .access = PL2_RW, | |
2262 | /* We don't support IRQ/FIQ bypass and system registers are | |
2263 | * always enabled, so all our bits are RAZ/WI or RAO/WI. | |
2264 | */ | |
2265 | .resetvalue = 0xf, | |
2266 | }, | |
2267 | { .name = "ICC_CTLR_EL3", .state = ARM_CP_STATE_BOTH, | |
2268 | .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 12, .opc2 = 4, | |
2269 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2270 | .access = PL3_RW, | |
359fbe65 PM |
2271 | .readfn = icc_ctlr_el3_read, |
2272 | .writefn = icc_ctlr_el3_write, | |
2273 | }, | |
2274 | { .name = "ICC_SRE_EL3", .state = ARM_CP_STATE_BOTH, | |
2275 | .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 12, .opc2 = 5, | |
2276 | .type = ARM_CP_NO_RAW | ARM_CP_CONST, | |
2277 | .access = PL3_RW, | |
2278 | /* We don't support IRQ/FIQ bypass and system registers are | |
2279 | * always enabled, so all our bits are RAZ/WI or RAO/WI. | |
2280 | */ | |
2281 | .resetvalue = 0xf, | |
2282 | }, | |
2283 | { .name = "ICC_IGRPEN1_EL3", .state = ARM_CP_STATE_BOTH, | |
2284 | .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 12, .opc2 = 7, | |
2285 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2286 | .access = PL3_RW, | |
2287 | .readfn = icc_igrpen1_el3_read, | |
2288 | .writefn = icc_igrpen1_el3_write, | |
2289 | }, | |
2290 | REGINFO_SENTINEL | |
2291 | }; | |
2292 | ||
83f036fe PM |
2293 | static uint64_t ich_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) |
2294 | { | |
2295 | GICv3CPUState *cs = icc_cs_from_env(env); | |
2296 | int regno = ri->opc2 & 3; | |
887aae10 | 2297 | int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0; |
83f036fe PM |
2298 | uint64_t value; |
2299 | ||
2300 | value = cs->ich_apr[grp][regno]; | |
2301 | trace_gicv3_ich_ap_read(ri->crm & 1, regno, gicv3_redist_affid(cs), value); | |
2302 | return value; | |
2303 | } | |
2304 | ||
2305 | static void ich_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2306 | uint64_t value) | |
2307 | { | |
2308 | GICv3CPUState *cs = icc_cs_from_env(env); | |
2309 | int regno = ri->opc2 & 3; | |
887aae10 | 2310 | int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0; |
83f036fe PM |
2311 | |
2312 | trace_gicv3_ich_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value); | |
2313 | ||
2314 | cs->ich_apr[grp][regno] = value & 0xFFFFFFFFU; | |
2315 | gicv3_cpuif_virt_update(cs); | |
2316 | } | |
2317 | ||
2318 | static uint64_t ich_hcr_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2319 | { | |
2320 | GICv3CPUState *cs = icc_cs_from_env(env); | |
2321 | uint64_t value = cs->ich_hcr_el2; | |
2322 | ||
2323 | trace_gicv3_ich_hcr_read(gicv3_redist_affid(cs), value); | |
2324 | return value; | |
2325 | } | |
2326 | ||
2327 | static void ich_hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2328 | uint64_t value) | |
2329 | { | |
2330 | GICv3CPUState *cs = icc_cs_from_env(env); | |
2331 | ||
2332 | trace_gicv3_ich_hcr_write(gicv3_redist_affid(cs), value); | |
2333 | ||
2334 | value &= ICH_HCR_EL2_EN | ICH_HCR_EL2_UIE | ICH_HCR_EL2_LRENPIE | | |
2335 | ICH_HCR_EL2_NPIE | ICH_HCR_EL2_VGRP0EIE | ICH_HCR_EL2_VGRP0DIE | | |
2336 | ICH_HCR_EL2_VGRP1EIE | ICH_HCR_EL2_VGRP1DIE | ICH_HCR_EL2_TC | | |
2337 | ICH_HCR_EL2_TALL0 | ICH_HCR_EL2_TALL1 | ICH_HCR_EL2_TSEI | | |
2338 | ICH_HCR_EL2_TDIR | ICH_HCR_EL2_EOICOUNT_MASK; | |
2339 | ||
2340 | cs->ich_hcr_el2 = value; | |
2341 | gicv3_cpuif_virt_update(cs); | |
2342 | } | |
2343 | ||
2344 | static uint64_t ich_vmcr_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2345 | { | |
2346 | GICv3CPUState *cs = icc_cs_from_env(env); | |
2347 | uint64_t value = cs->ich_vmcr_el2; | |
2348 | ||
2349 | trace_gicv3_ich_vmcr_read(gicv3_redist_affid(cs), value); | |
2350 | return value; | |
2351 | } | |
2352 | ||
2353 | static void ich_vmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2354 | uint64_t value) | |
2355 | { | |
2356 | GICv3CPUState *cs = icc_cs_from_env(env); | |
2357 | ||
2358 | trace_gicv3_ich_vmcr_write(gicv3_redist_affid(cs), value); | |
2359 | ||
2360 | value &= ICH_VMCR_EL2_VENG0 | ICH_VMCR_EL2_VENG1 | ICH_VMCR_EL2_VCBPR | | |
2361 | ICH_VMCR_EL2_VEOIM | ICH_VMCR_EL2_VBPR1_MASK | | |
2362 | ICH_VMCR_EL2_VBPR0_MASK | ICH_VMCR_EL2_VPMR_MASK; | |
2363 | value |= ICH_VMCR_EL2_VFIQEN; | |
2364 | ||
2365 | cs->ich_vmcr_el2 = value; | |
2366 | /* Enforce "writing BPRs to less than minimum sets them to the minimum" | |
2367 | * by reading and writing back the fields. | |
2368 | */ | |
8b7fbd6c | 2369 | write_vbpr(cs, GICV3_G0, read_vbpr(cs, GICV3_G0)); |
83f036fe PM |
2370 | write_vbpr(cs, GICV3_G1, read_vbpr(cs, GICV3_G1)); |
2371 | ||
2372 | gicv3_cpuif_virt_update(cs); | |
2373 | } | |
2374 | ||
2375 | static uint64_t ich_lr_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2376 | { | |
2377 | GICv3CPUState *cs = icc_cs_from_env(env); | |
2378 | int regno = ri->opc2 | ((ri->crm & 1) << 3); | |
2379 | uint64_t value; | |
2380 | ||
2381 | /* This read function handles all of: | |
2382 | * 64-bit reads of the whole LR | |
2383 | * 32-bit reads of the low half of the LR | |
2384 | * 32-bit reads of the high half of the LR | |
2385 | */ | |
2386 | if (ri->state == ARM_CP_STATE_AA32) { | |
2387 | if (ri->crm >= 14) { | |
2388 | value = extract64(cs->ich_lr_el2[regno], 32, 32); | |
2389 | trace_gicv3_ich_lrc_read(regno, gicv3_redist_affid(cs), value); | |
2390 | } else { | |
2391 | value = extract64(cs->ich_lr_el2[regno], 0, 32); | |
2392 | trace_gicv3_ich_lr32_read(regno, gicv3_redist_affid(cs), value); | |
2393 | } | |
2394 | } else { | |
2395 | value = cs->ich_lr_el2[regno]; | |
2396 | trace_gicv3_ich_lr_read(regno, gicv3_redist_affid(cs), value); | |
2397 | } | |
2398 | ||
2399 | return value; | |
2400 | } | |
2401 | ||
2402 | static void ich_lr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2403 | uint64_t value) | |
2404 | { | |
2405 | GICv3CPUState *cs = icc_cs_from_env(env); | |
2406 | int regno = ri->opc2 | ((ri->crm & 1) << 3); | |
2407 | ||
2408 | /* This write function handles all of: | |
2409 | * 64-bit writes to the whole LR | |
2410 | * 32-bit writes to the low half of the LR | |
2411 | * 32-bit writes to the high half of the LR | |
2412 | */ | |
2413 | if (ri->state == ARM_CP_STATE_AA32) { | |
2414 | if (ri->crm >= 14) { | |
2415 | trace_gicv3_ich_lrc_write(regno, gicv3_redist_affid(cs), value); | |
2416 | value = deposit64(cs->ich_lr_el2[regno], 32, 32, value); | |
2417 | } else { | |
2418 | trace_gicv3_ich_lr32_write(regno, gicv3_redist_affid(cs), value); | |
2419 | value = deposit64(cs->ich_lr_el2[regno], 0, 32, value); | |
2420 | } | |
2421 | } else { | |
2422 | trace_gicv3_ich_lr_write(regno, gicv3_redist_affid(cs), value); | |
2423 | } | |
2424 | ||
2425 | /* Enforce RES0 bits in priority field */ | |
2426 | if (cs->vpribits < 8) { | |
2427 | value = deposit64(value, ICH_LR_EL2_PRIORITY_SHIFT, | |
2428 | 8 - cs->vpribits, 0); | |
2429 | } | |
2430 | ||
2431 | cs->ich_lr_el2[regno] = value; | |
2432 | gicv3_cpuif_virt_update(cs); | |
2433 | } | |
2434 | ||
2435 | static uint64_t ich_vtr_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2436 | { | |
2437 | GICv3CPUState *cs = icc_cs_from_env(env); | |
2438 | uint64_t value; | |
2439 | ||
2440 | value = ((cs->num_list_regs - 1) << ICH_VTR_EL2_LISTREGS_SHIFT) | |
2441 | | ICH_VTR_EL2_TDS | ICH_VTR_EL2_NV4 | ICH_VTR_EL2_A3V | |
2442 | | (1 << ICH_VTR_EL2_IDBITS_SHIFT) | |
2443 | | ((cs->vprebits - 1) << ICH_VTR_EL2_PREBITS_SHIFT) | |
2444 | | ((cs->vpribits - 1) << ICH_VTR_EL2_PRIBITS_SHIFT); | |
2445 | ||
2446 | trace_gicv3_ich_vtr_read(gicv3_redist_affid(cs), value); | |
2447 | return value; | |
2448 | } | |
2449 | ||
2450 | static uint64_t ich_misr_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2451 | { | |
2452 | GICv3CPUState *cs = icc_cs_from_env(env); | |
2453 | uint64_t value = maintenance_interrupt_state(cs); | |
2454 | ||
2455 | trace_gicv3_ich_misr_read(gicv3_redist_affid(cs), value); | |
2456 | return value; | |
2457 | } | |
2458 | ||
2459 | static uint64_t ich_eisr_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2460 | { | |
2461 | GICv3CPUState *cs = icc_cs_from_env(env); | |
2462 | uint64_t value = eoi_maintenance_interrupt_state(cs, NULL); | |
2463 | ||
2464 | trace_gicv3_ich_eisr_read(gicv3_redist_affid(cs), value); | |
2465 | return value; | |
2466 | } | |
2467 | ||
2468 | static uint64_t ich_elrsr_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2469 | { | |
2470 | GICv3CPUState *cs = icc_cs_from_env(env); | |
2471 | uint64_t value = 0; | |
2472 | int i; | |
2473 | ||
2474 | for (i = 0; i < cs->num_list_regs; i++) { | |
2475 | uint64_t lr = cs->ich_lr_el2[i]; | |
2476 | ||
2477 | if ((lr & ICH_LR_EL2_STATE_MASK) == 0 && | |
d87576e3 | 2478 | ((lr & ICH_LR_EL2_HW) != 0 || (lr & ICH_LR_EL2_EOI) == 0)) { |
83f036fe PM |
2479 | value |= (1 << i); |
2480 | } | |
2481 | } | |
2482 | ||
2483 | trace_gicv3_ich_elrsr_read(gicv3_redist_affid(cs), value); | |
2484 | return value; | |
2485 | } | |
2486 | ||
2487 | static const ARMCPRegInfo gicv3_cpuif_hcr_reginfo[] = { | |
2488 | { .name = "ICH_AP0R0_EL2", .state = ARM_CP_STATE_BOTH, | |
2489 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 8, .opc2 = 0, | |
2490 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2491 | .access = PL2_RW, | |
2492 | .readfn = ich_ap_read, | |
2493 | .writefn = ich_ap_write, | |
2494 | }, | |
2495 | { .name = "ICH_AP1R0_EL2", .state = ARM_CP_STATE_BOTH, | |
2496 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 9, .opc2 = 0, | |
2497 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2498 | .access = PL2_RW, | |
2499 | .readfn = ich_ap_read, | |
2500 | .writefn = ich_ap_write, | |
2501 | }, | |
2502 | { .name = "ICH_HCR_EL2", .state = ARM_CP_STATE_BOTH, | |
2503 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 11, .opc2 = 0, | |
2504 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2505 | .access = PL2_RW, | |
2506 | .readfn = ich_hcr_read, | |
2507 | .writefn = ich_hcr_write, | |
2508 | }, | |
2509 | { .name = "ICH_VTR_EL2", .state = ARM_CP_STATE_BOTH, | |
2510 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 11, .opc2 = 1, | |
2511 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2512 | .access = PL2_R, | |
2513 | .readfn = ich_vtr_read, | |
2514 | }, | |
2515 | { .name = "ICH_MISR_EL2", .state = ARM_CP_STATE_BOTH, | |
2516 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 11, .opc2 = 2, | |
2517 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2518 | .access = PL2_R, | |
2519 | .readfn = ich_misr_read, | |
2520 | }, | |
2521 | { .name = "ICH_EISR_EL2", .state = ARM_CP_STATE_BOTH, | |
2522 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 11, .opc2 = 3, | |
2523 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2524 | .access = PL2_R, | |
2525 | .readfn = ich_eisr_read, | |
2526 | }, | |
2527 | { .name = "ICH_ELRSR_EL2", .state = ARM_CP_STATE_BOTH, | |
2528 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 11, .opc2 = 5, | |
2529 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2530 | .access = PL2_R, | |
2531 | .readfn = ich_elrsr_read, | |
2532 | }, | |
2533 | { .name = "ICH_VMCR_EL2", .state = ARM_CP_STATE_BOTH, | |
2534 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 11, .opc2 = 7, | |
2535 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2536 | .access = PL2_RW, | |
2537 | .readfn = ich_vmcr_read, | |
2538 | .writefn = ich_vmcr_write, | |
2539 | }, | |
2540 | REGINFO_SENTINEL | |
2541 | }; | |
2542 | ||
2543 | static const ARMCPRegInfo gicv3_cpuif_ich_apxr1_reginfo[] = { | |
2544 | { .name = "ICH_AP0R1_EL2", .state = ARM_CP_STATE_BOTH, | |
2545 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 8, .opc2 = 1, | |
2546 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2547 | .access = PL2_RW, | |
2548 | .readfn = ich_ap_read, | |
2549 | .writefn = ich_ap_write, | |
2550 | }, | |
2551 | { .name = "ICH_AP1R1_EL2", .state = ARM_CP_STATE_BOTH, | |
2552 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 9, .opc2 = 1, | |
2553 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2554 | .access = PL2_RW, | |
2555 | .readfn = ich_ap_read, | |
2556 | .writefn = ich_ap_write, | |
2557 | }, | |
2558 | REGINFO_SENTINEL | |
2559 | }; | |
2560 | ||
2561 | static const ARMCPRegInfo gicv3_cpuif_ich_apxr23_reginfo[] = { | |
2562 | { .name = "ICH_AP0R2_EL2", .state = ARM_CP_STATE_BOTH, | |
2563 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 8, .opc2 = 2, | |
2564 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2565 | .access = PL2_RW, | |
2566 | .readfn = ich_ap_read, | |
2567 | .writefn = ich_ap_write, | |
2568 | }, | |
2569 | { .name = "ICH_AP0R3_EL2", .state = ARM_CP_STATE_BOTH, | |
2570 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 8, .opc2 = 3, | |
2571 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2572 | .access = PL2_RW, | |
2573 | .readfn = ich_ap_read, | |
2574 | .writefn = ich_ap_write, | |
2575 | }, | |
2576 | { .name = "ICH_AP1R2_EL2", .state = ARM_CP_STATE_BOTH, | |
2577 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 9, .opc2 = 2, | |
2578 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2579 | .access = PL2_RW, | |
2580 | .readfn = ich_ap_read, | |
2581 | .writefn = ich_ap_write, | |
2582 | }, | |
2583 | { .name = "ICH_AP1R3_EL2", .state = ARM_CP_STATE_BOTH, | |
2584 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 9, .opc2 = 3, | |
2585 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2586 | .access = PL2_RW, | |
2587 | .readfn = ich_ap_read, | |
2588 | .writefn = ich_ap_write, | |
2589 | }, | |
2590 | REGINFO_SENTINEL | |
2591 | }; | |
2592 | ||
359fbe65 PM |
2593 | static void gicv3_cpuif_el_change_hook(ARMCPU *cpu, void *opaque) |
2594 | { | |
f7b9358e PM |
2595 | GICv3CPUState *cs = opaque; |
2596 | ||
2597 | gicv3_cpuif_update(cs); | |
359fbe65 PM |
2598 | } |
2599 | ||
2600 | void gicv3_init_cpuif(GICv3State *s) | |
2601 | { | |
2602 | /* Called from the GICv3 realize function; register our system | |
2603 | * registers with the CPU | |
2604 | */ | |
2605 | int i; | |
2606 | ||
2607 | for (i = 0; i < s->num_cpu; i++) { | |
2608 | ARMCPU *cpu = ARM_CPU(qemu_get_cpu(i)); | |
2609 | GICv3CPUState *cs = &s->cpu[i]; | |
2610 | ||
2611 | /* Note that we can't just use the GICv3CPUState as an opaque pointer | |
2612 | * in define_arm_cp_regs_with_opaque(), because when we're called back | |
2613 | * it might be with code translated by CPU 0 but run by CPU 1, in | |
2614 | * which case we'd get the wrong value. | |
2615 | * So instead we define the regs with no ri->opaque info, and | |
d5a5e4c9 | 2616 | * get back to the GICv3CPUState from the CPUARMState. |
359fbe65 PM |
2617 | */ |
2618 | define_arm_cp_regs(cpu, gicv3_cpuif_reginfo); | |
83f036fe PM |
2619 | if (arm_feature(&cpu->env, ARM_FEATURE_EL2) |
2620 | && cpu->gic_num_lrs) { | |
2621 | int j; | |
2622 | ||
c5fc89b3 PM |
2623 | cs->maintenance_irq = cpu->gicv3_maintenance_interrupt; |
2624 | ||
83f036fe PM |
2625 | cs->num_list_regs = cpu->gic_num_lrs; |
2626 | cs->vpribits = cpu->gic_vpribits; | |
2627 | cs->vprebits = cpu->gic_vprebits; | |
2628 | ||
2629 | /* Check against architectural constraints: getting these | |
2630 | * wrong would be a bug in the CPU code defining these, | |
2631 | * and the implementation relies on them holding. | |
2632 | */ | |
2633 | g_assert(cs->vprebits <= cs->vpribits); | |
2634 | g_assert(cs->vprebits >= 5 && cs->vprebits <= 7); | |
2635 | g_assert(cs->vpribits >= 5 && cs->vpribits <= 8); | |
2636 | ||
2637 | define_arm_cp_regs(cpu, gicv3_cpuif_hcr_reginfo); | |
2638 | ||
2639 | for (j = 0; j < cs->num_list_regs; j++) { | |
2640 | /* Note that the AArch64 LRs are 64-bit; the AArch32 LRs | |
2641 | * are split into two cp15 regs, LR (the low part, with the | |
2642 | * same encoding as the AArch64 LR) and LRC (the high part). | |
2643 | */ | |
2644 | ARMCPRegInfo lr_regset[] = { | |
2645 | { .name = "ICH_LRn_EL2", .state = ARM_CP_STATE_BOTH, | |
2646 | .opc0 = 3, .opc1 = 4, .crn = 12, | |
2647 | .crm = 12 + (j >> 3), .opc2 = j & 7, | |
2648 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2649 | .access = PL2_RW, | |
2650 | .readfn = ich_lr_read, | |
2651 | .writefn = ich_lr_write, | |
2652 | }, | |
2653 | { .name = "ICH_LRCn_EL2", .state = ARM_CP_STATE_AA32, | |
2654 | .cp = 15, .opc1 = 4, .crn = 12, | |
2655 | .crm = 14 + (j >> 3), .opc2 = j & 7, | |
2656 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2657 | .access = PL2_RW, | |
2658 | .readfn = ich_lr_read, | |
2659 | .writefn = ich_lr_write, | |
2660 | }, | |
2661 | REGINFO_SENTINEL | |
2662 | }; | |
2663 | define_arm_cp_regs(cpu, lr_regset); | |
2664 | } | |
2665 | if (cs->vprebits >= 6) { | |
2666 | define_arm_cp_regs(cpu, gicv3_cpuif_ich_apxr1_reginfo); | |
2667 | } | |
2668 | if (cs->vprebits == 7) { | |
2669 | define_arm_cp_regs(cpu, gicv3_cpuif_ich_apxr23_reginfo); | |
2670 | } | |
2671 | } | |
359fbe65 PM |
2672 | arm_register_el_change_hook(cpu, gicv3_cpuif_el_change_hook, cs); |
2673 | } | |
2674 | } |