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359fbe65 | 1 | /* |
a1d742d8 | 2 | * ARM Generic Interrupt Controller v3 (emulation) |
359fbe65 PM |
3 | * |
4 | * Copyright (c) 2016 Linaro Limited | |
5 | * Written by Peter Maydell | |
6 | * | |
7 | * This code is licensed under the GPL, version 2 or (at your option) | |
8 | * any later version. | |
9 | */ | |
10 | ||
11 | /* This file contains the code for the system register interface | |
12 | * portions of the GICv3. | |
13 | */ | |
14 | ||
15 | #include "qemu/osdep.h" | |
77620ba6 | 16 | #include "qemu/bitops.h" |
96a664d0 | 17 | #include "qemu/log.h" |
8d04fb55 | 18 | #include "qemu/main-loop.h" |
359fbe65 PM |
19 | #include "trace.h" |
20 | #include "gicv3_internal.h" | |
64552b6b | 21 | #include "hw/irq.h" |
359fbe65 | 22 | #include "cpu.h" |
cf7c6d10 | 23 | #include "target/arm/cpregs.h" |
a2260983 AG |
24 | #include "sysemu/tcg.h" |
25 | #include "sysemu/qtest.h" | |
359fbe65 | 26 | |
c3f21b06 PM |
27 | /* |
28 | * Special case return value from hppvi_index(); must be larger than | |
29 | * the architecturally maximum possible list register index (which is 15) | |
30 | */ | |
31 | #define HPPVI_INDEX_VLPI 16 | |
32 | ||
359fbe65 PM |
33 | static GICv3CPUState *icc_cs_from_env(CPUARMState *env) |
34 | { | |
d5a5e4c9 | 35 | return env->gicv3state; |
359fbe65 PM |
36 | } |
37 | ||
38 | static bool gicv3_use_ns_bank(CPUARMState *env) | |
39 | { | |
40 | /* Return true if we should use the NonSecure bank for a banked GIC | |
41 | * CPU interface register. Note that this differs from the | |
42 | * access_secure_reg() function because GICv3 banked registers are | |
43 | * banked even for AArch64, unlike the other CPU system registers. | |
44 | */ | |
45 | return !arm_is_secure_below_el3(env); | |
46 | } | |
47 | ||
4eb833b5 PM |
48 | /* The minimum BPR for the virtual interface is a configurable property */ |
49 | static inline int icv_min_vbpr(GICv3CPUState *cs) | |
50 | { | |
51 | return 7 - cs->vprebits; | |
52 | } | |
53 | ||
5d55f827 PM |
54 | static inline int ich_num_aprs(GICv3CPUState *cs) |
55 | { | |
56 | /* Return the number of virtual APR registers (1, 2, or 4) */ | |
57 | int aprmax = 1 << (cs->vprebits - 5); | |
58 | assert(aprmax <= ARRAY_SIZE(cs->ich_apr[0])); | |
59 | return aprmax; | |
60 | } | |
61 | ||
83f036fe | 62 | /* Simple accessor functions for LR fields */ |
df313f48 PM |
63 | static uint32_t ich_lr_vintid(uint64_t lr) |
64 | { | |
65 | return extract64(lr, ICH_LR_EL2_VINTID_SHIFT, ICH_LR_EL2_VINTID_LENGTH); | |
66 | } | |
67 | ||
68 | static uint32_t ich_lr_pintid(uint64_t lr) | |
69 | { | |
70 | return extract64(lr, ICH_LR_EL2_PINTID_SHIFT, ICH_LR_EL2_PINTID_LENGTH); | |
71 | } | |
72 | ||
73 | static uint32_t ich_lr_prio(uint64_t lr) | |
74 | { | |
75 | return extract64(lr, ICH_LR_EL2_PRIORITY_SHIFT, ICH_LR_EL2_PRIORITY_LENGTH); | |
76 | } | |
77 | ||
83f036fe PM |
78 | static int ich_lr_state(uint64_t lr) |
79 | { | |
80 | return extract64(lr, ICH_LR_EL2_STATE_SHIFT, ICH_LR_EL2_STATE_LENGTH); | |
81 | } | |
82 | ||
77620ba6 PM |
83 | static bool icv_access(CPUARMState *env, int hcr_flags) |
84 | { | |
85 | /* Return true if this ICC_ register access should really be | |
86 | * directed to an ICV_ access. hcr_flags is a mask of | |
87 | * HCR_EL2 bits to check: we treat this as an ICV_ access | |
88 | * if we are in NS EL1 and at least one of the specified | |
89 | * HCR_EL2 bits is set. | |
90 | * | |
91 | * ICV registers fall into four categories: | |
92 | * * access if NS EL1 and HCR_EL2.FMO == 1: | |
93 | * all ICV regs with '0' in their name | |
94 | * * access if NS EL1 and HCR_EL2.IMO == 1: | |
95 | * all ICV regs with '1' in their name | |
96 | * * access if NS EL1 and either IMO or FMO == 1: | |
97 | * CTLR, DIR, PMR, RPR | |
98 | */ | |
f7778444 RH |
99 | uint64_t hcr_el2 = arm_hcr_el2_eff(env); |
100 | bool flagmatch = hcr_el2 & hcr_flags & (HCR_IMO | HCR_FMO); | |
ac656b16 PM |
101 | |
102 | return flagmatch && arm_current_el(env) == 1 | |
77620ba6 PM |
103 | && !arm_is_secure_below_el3(env); |
104 | } | |
105 | ||
83f036fe PM |
106 | static int read_vbpr(GICv3CPUState *cs, int grp) |
107 | { | |
108 | /* Read VBPR value out of the VMCR field (caller must handle | |
109 | * VCBPR effects if required) | |
110 | */ | |
111 | if (grp == GICV3_G0) { | |
112 | return extract64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VBPR0_SHIFT, | |
113 | ICH_VMCR_EL2_VBPR0_LENGTH); | |
114 | } else { | |
115 | return extract64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VBPR1_SHIFT, | |
116 | ICH_VMCR_EL2_VBPR1_LENGTH); | |
117 | } | |
118 | } | |
119 | ||
120 | static void write_vbpr(GICv3CPUState *cs, int grp, int value) | |
121 | { | |
122 | /* Write new VBPR1 value, handling the "writing a value less than | |
123 | * the minimum sets it to the minimum" semantics. | |
124 | */ | |
125 | int min = icv_min_vbpr(cs); | |
126 | ||
127 | if (grp != GICV3_G0) { | |
128 | min++; | |
129 | } | |
130 | ||
131 | value = MAX(value, min); | |
132 | ||
133 | if (grp == GICV3_G0) { | |
134 | cs->ich_vmcr_el2 = deposit64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VBPR0_SHIFT, | |
135 | ICH_VMCR_EL2_VBPR0_LENGTH, value); | |
136 | } else { | |
137 | cs->ich_vmcr_el2 = deposit64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VBPR1_SHIFT, | |
138 | ICH_VMCR_EL2_VBPR1_LENGTH, value); | |
139 | } | |
140 | } | |
141 | ||
77620ba6 PM |
142 | static uint32_t icv_fullprio_mask(GICv3CPUState *cs) |
143 | { | |
144 | /* Return a mask word which clears the unimplemented priority bits | |
145 | * from a priority value for a virtual interrupt. (Not to be confused | |
146 | * with the group priority, whose mask depends on the value of VBPR | |
147 | * for the interrupt group.) | |
148 | */ | |
70726a15 | 149 | return (~0U << (8 - cs->vpribits)) & 0xff; |
77620ba6 PM |
150 | } |
151 | ||
df313f48 PM |
152 | static int ich_highest_active_virt_prio(GICv3CPUState *cs) |
153 | { | |
154 | /* Calculate the current running priority based on the set bits | |
155 | * in the ICH Active Priority Registers. | |
156 | */ | |
157 | int i; | |
5d55f827 | 158 | int aprmax = ich_num_aprs(cs); |
df313f48 PM |
159 | |
160 | for (i = 0; i < aprmax; i++) { | |
161 | uint32_t apr = cs->ich_apr[GICV3_G0][i] | | |
162 | cs->ich_apr[GICV3_G1NS][i]; | |
163 | ||
164 | if (!apr) { | |
165 | continue; | |
166 | } | |
167 | return (i * 32 + ctz32(apr)) << (icv_min_vbpr(cs) + 1); | |
168 | } | |
169 | /* No current active interrupts: return idle priority */ | |
170 | return 0xff; | |
171 | } | |
172 | ||
173 | static int hppvi_index(GICv3CPUState *cs) | |
174 | { | |
c3f21b06 PM |
175 | /* |
176 | * Return the list register index of the highest priority pending | |
df313f48 PM |
177 | * virtual interrupt, as per the HighestPriorityVirtualInterrupt |
178 | * pseudocode. If no pending virtual interrupts, return -1. | |
c3f21b06 PM |
179 | * If the highest priority pending virtual interrupt is a vLPI, |
180 | * return HPPVI_INDEX_VLPI. | |
181 | * (The pseudocode handles checking whether the vLPI is higher | |
182 | * priority than the highest priority list register at every | |
183 | * callsite of HighestPriorityVirtualInterrupt; we check it here.) | |
df313f48 | 184 | */ |
c3f21b06 PM |
185 | ARMCPU *cpu = ARM_CPU(cs->cpu); |
186 | CPUARMState *env = &cpu->env; | |
df313f48 PM |
187 | int idx = -1; |
188 | int i; | |
189 | /* Note that a list register entry with a priority of 0xff will | |
190 | * never be reported by this function; this is the architecturally | |
191 | * correct behaviour. | |
192 | */ | |
193 | int prio = 0xff; | |
194 | ||
195 | if (!(cs->ich_vmcr_el2 & (ICH_VMCR_EL2_VENG0 | ICH_VMCR_EL2_VENG1))) { | |
196 | /* Both groups disabled, definitely nothing to do */ | |
197 | return idx; | |
198 | } | |
199 | ||
200 | for (i = 0; i < cs->num_list_regs; i++) { | |
201 | uint64_t lr = cs->ich_lr_el2[i]; | |
202 | int thisprio; | |
203 | ||
204 | if (ich_lr_state(lr) != ICH_LR_EL2_STATE_PENDING) { | |
205 | /* Not Pending */ | |
206 | continue; | |
207 | } | |
208 | ||
209 | /* Ignore interrupts if relevant group enable not set */ | |
210 | if (lr & ICH_LR_EL2_GROUP) { | |
211 | if (!(cs->ich_vmcr_el2 & ICH_VMCR_EL2_VENG1)) { | |
212 | continue; | |
213 | } | |
214 | } else { | |
215 | if (!(cs->ich_vmcr_el2 & ICH_VMCR_EL2_VENG0)) { | |
216 | continue; | |
217 | } | |
218 | } | |
219 | ||
220 | thisprio = ich_lr_prio(lr); | |
221 | ||
222 | if (thisprio < prio) { | |
223 | prio = thisprio; | |
224 | idx = i; | |
225 | } | |
226 | } | |
227 | ||
c3f21b06 PM |
228 | /* |
229 | * "no pending vLPI" is indicated with prio = 0xff, which always | |
230 | * fails the priority check here. vLPIs are only considered | |
231 | * when we are in Non-Secure state. | |
232 | */ | |
233 | if (cs->hppvlpi.prio < prio && !arm_is_secure(env)) { | |
234 | if (cs->hppvlpi.grp == GICV3_G0) { | |
235 | if (cs->ich_vmcr_el2 & ICH_VMCR_EL2_VENG0) { | |
236 | return HPPVI_INDEX_VLPI; | |
237 | } | |
238 | } else { | |
239 | if (cs->ich_vmcr_el2 & ICH_VMCR_EL2_VENG1) { | |
240 | return HPPVI_INDEX_VLPI; | |
241 | } | |
242 | } | |
243 | } | |
244 | ||
df313f48 PM |
245 | return idx; |
246 | } | |
247 | ||
b3b48f52 PM |
248 | static uint32_t icv_gprio_mask(GICv3CPUState *cs, int group) |
249 | { | |
250 | /* Return a mask word which clears the subpriority bits from | |
251 | * a priority value for a virtual interrupt in the specified group. | |
a89ff39e PM |
252 | * This depends on the VBPR value. |
253 | * If using VBPR0 then: | |
b3b48f52 PM |
254 | * a BPR of 0 means the group priority bits are [7:1]; |
255 | * a BPR of 1 means they are [7:2], and so on down to | |
256 | * a BPR of 7 meaning no group priority bits at all. | |
a89ff39e PM |
257 | * If using VBPR1 then: |
258 | * a BPR of 0 is impossible (the minimum value is 1) | |
259 | * a BPR of 1 means the group priority bits are [7:1]; | |
260 | * a BPR of 2 means they are [7:2], and so on down to | |
261 | * a BPR of 7 meaning the group priority is [7]. | |
262 | * | |
b3b48f52 PM |
263 | * Which BPR to use depends on the group of the interrupt and |
264 | * the current ICH_VMCR_EL2.VCBPR settings. | |
a89ff39e PM |
265 | * |
266 | * This corresponds to the VGroupBits() pseudocode. | |
b3b48f52 | 267 | */ |
a89ff39e PM |
268 | int bpr; |
269 | ||
b3b48f52 PM |
270 | if (group == GICV3_G1NS && cs->ich_vmcr_el2 & ICH_VMCR_EL2_VCBPR) { |
271 | group = GICV3_G0; | |
272 | } | |
273 | ||
a89ff39e PM |
274 | bpr = read_vbpr(cs, group); |
275 | if (group == GICV3_G1NS) { | |
276 | assert(bpr > 0); | |
277 | bpr--; | |
278 | } | |
279 | ||
280 | return ~0U << (bpr + 1); | |
b3b48f52 PM |
281 | } |
282 | ||
283 | static bool icv_hppi_can_preempt(GICv3CPUState *cs, uint64_t lr) | |
284 | { | |
285 | /* Return true if we can signal this virtual interrupt defined by | |
286 | * the given list register value; see the pseudocode functions | |
287 | * CanSignalVirtualInterrupt and CanSignalVirtualInt. | |
288 | * Compare also icc_hppi_can_preempt() which is the non-virtual | |
289 | * equivalent of these checks. | |
290 | */ | |
291 | int grp; | |
292 | uint32_t mask, prio, rprio, vpmr; | |
293 | ||
294 | if (!(cs->ich_hcr_el2 & ICH_HCR_EL2_EN)) { | |
295 | /* Virtual interface disabled */ | |
296 | return false; | |
297 | } | |
298 | ||
299 | /* We don't need to check that this LR is in Pending state because | |
300 | * that has already been done in hppvi_index(). | |
301 | */ | |
302 | ||
303 | prio = ich_lr_prio(lr); | |
304 | vpmr = extract64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VPMR_SHIFT, | |
305 | ICH_VMCR_EL2_VPMR_LENGTH); | |
306 | ||
307 | if (prio >= vpmr) { | |
308 | /* Priority mask masks this interrupt */ | |
309 | return false; | |
310 | } | |
311 | ||
312 | rprio = ich_highest_active_virt_prio(cs); | |
313 | if (rprio == 0xff) { | |
314 | /* No running interrupt so we can preempt */ | |
315 | return true; | |
316 | } | |
317 | ||
318 | grp = (lr & ICH_LR_EL2_GROUP) ? GICV3_G1NS : GICV3_G0; | |
319 | ||
320 | mask = icv_gprio_mask(cs, grp); | |
321 | ||
322 | /* We only preempt a running interrupt if the pending interrupt's | |
323 | * group priority is sufficient (the subpriorities are not considered). | |
324 | */ | |
325 | if ((prio & mask) < (rprio & mask)) { | |
326 | return true; | |
327 | } | |
328 | ||
329 | return false; | |
330 | } | |
331 | ||
c3f21b06 PM |
332 | static bool icv_hppvlpi_can_preempt(GICv3CPUState *cs) |
333 | { | |
334 | /* | |
335 | * Return true if we can signal the highest priority pending vLPI. | |
336 | * We can assume we're Non-secure because hppvi_index() already | |
337 | * tested for that. | |
338 | */ | |
339 | uint32_t mask, rprio, vpmr; | |
340 | ||
341 | if (!(cs->ich_hcr_el2 & ICH_HCR_EL2_EN)) { | |
342 | /* Virtual interface disabled */ | |
343 | return false; | |
344 | } | |
345 | ||
346 | vpmr = extract64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VPMR_SHIFT, | |
347 | ICH_VMCR_EL2_VPMR_LENGTH); | |
348 | ||
349 | if (cs->hppvlpi.prio >= vpmr) { | |
350 | /* Priority mask masks this interrupt */ | |
351 | return false; | |
352 | } | |
353 | ||
354 | rprio = ich_highest_active_virt_prio(cs); | |
355 | if (rprio == 0xff) { | |
356 | /* No running interrupt so we can preempt */ | |
357 | return true; | |
358 | } | |
359 | ||
360 | mask = icv_gprio_mask(cs, cs->hppvlpi.grp); | |
361 | ||
362 | /* | |
363 | * We only preempt a running interrupt if the pending interrupt's | |
364 | * group priority is sufficient (the subpriorities are not considered). | |
365 | */ | |
366 | if ((cs->hppvlpi.prio & mask) < (rprio & mask)) { | |
367 | return true; | |
368 | } | |
369 | ||
370 | return false; | |
371 | } | |
372 | ||
83f036fe PM |
373 | static uint32_t eoi_maintenance_interrupt_state(GICv3CPUState *cs, |
374 | uint32_t *misr) | |
375 | { | |
376 | /* Return a set of bits indicating the EOI maintenance interrupt status | |
377 | * for each list register. The EOI maintenance interrupt status is | |
378 | * 1 if LR.State == 0 && LR.HW == 0 && LR.EOI == 1 | |
379 | * (see the GICv3 spec for the ICH_EISR_EL2 register). | |
380 | * If misr is not NULL then we should also collect the information | |
381 | * about the MISR.EOI, MISR.NP and MISR.U bits. | |
382 | */ | |
383 | uint32_t value = 0; | |
384 | int validcount = 0; | |
385 | bool seenpending = false; | |
386 | int i; | |
387 | ||
388 | for (i = 0; i < cs->num_list_regs; i++) { | |
389 | uint64_t lr = cs->ich_lr_el2[i]; | |
390 | ||
391 | if ((lr & (ICH_LR_EL2_STATE_MASK | ICH_LR_EL2_HW | ICH_LR_EL2_EOI)) | |
392 | == ICH_LR_EL2_EOI) { | |
393 | value |= (1 << i); | |
394 | } | |
395 | if ((lr & ICH_LR_EL2_STATE_MASK)) { | |
396 | validcount++; | |
397 | } | |
398 | if (ich_lr_state(lr) == ICH_LR_EL2_STATE_PENDING) { | |
399 | seenpending = true; | |
400 | } | |
401 | } | |
402 | ||
403 | if (misr) { | |
404 | if (validcount < 2 && (cs->ich_hcr_el2 & ICH_HCR_EL2_UIE)) { | |
405 | *misr |= ICH_MISR_EL2_U; | |
406 | } | |
407 | if (!seenpending && (cs->ich_hcr_el2 & ICH_HCR_EL2_NPIE)) { | |
408 | *misr |= ICH_MISR_EL2_NP; | |
409 | } | |
410 | if (value) { | |
411 | *misr |= ICH_MISR_EL2_EOI; | |
412 | } | |
413 | } | |
414 | return value; | |
415 | } | |
416 | ||
417 | static uint32_t maintenance_interrupt_state(GICv3CPUState *cs) | |
418 | { | |
419 | /* Return a set of bits indicating the maintenance interrupt status | |
420 | * (as seen in the ICH_MISR_EL2 register). | |
421 | */ | |
422 | uint32_t value = 0; | |
423 | ||
424 | /* Scan list registers and fill in the U, NP and EOI bits */ | |
425 | eoi_maintenance_interrupt_state(cs, &value); | |
426 | ||
2958e515 DH |
427 | if ((cs->ich_hcr_el2 & ICH_HCR_EL2_LRENPIE) && |
428 | (cs->ich_hcr_el2 & ICH_HCR_EL2_EOICOUNT_MASK)) { | |
83f036fe PM |
429 | value |= ICH_MISR_EL2_LRENP; |
430 | } | |
431 | ||
432 | if ((cs->ich_hcr_el2 & ICH_HCR_EL2_VGRP0EIE) && | |
433 | (cs->ich_vmcr_el2 & ICH_VMCR_EL2_VENG0)) { | |
434 | value |= ICH_MISR_EL2_VGRP0E; | |
435 | } | |
436 | ||
437 | if ((cs->ich_hcr_el2 & ICH_HCR_EL2_VGRP0DIE) && | |
438 | !(cs->ich_vmcr_el2 & ICH_VMCR_EL2_VENG1)) { | |
439 | value |= ICH_MISR_EL2_VGRP0D; | |
440 | } | |
441 | if ((cs->ich_hcr_el2 & ICH_HCR_EL2_VGRP1EIE) && | |
442 | (cs->ich_vmcr_el2 & ICH_VMCR_EL2_VENG1)) { | |
443 | value |= ICH_MISR_EL2_VGRP1E; | |
444 | } | |
445 | ||
446 | if ((cs->ich_hcr_el2 & ICH_HCR_EL2_VGRP1DIE) && | |
447 | !(cs->ich_vmcr_el2 & ICH_VMCR_EL2_VENG1)) { | |
448 | value |= ICH_MISR_EL2_VGRP1D; | |
449 | } | |
450 | ||
451 | return value; | |
452 | } | |
453 | ||
10337638 | 454 | void gicv3_cpuif_virt_irq_fiq_update(GICv3CPUState *cs) |
83f036fe | 455 | { |
10337638 PM |
456 | /* |
457 | * Tell the CPU about any pending virtual interrupts. | |
458 | * This should only be called for changes that affect the | |
459 | * vIRQ and vFIQ status and do not change the maintenance | |
460 | * interrupt status. This means that unlike gicv3_cpuif_virt_update() | |
461 | * this function won't recursively call back into the GIC code. | |
462 | * The main use of this is when the redistributor has changed the | |
463 | * highest priority pending virtual LPI. | |
c5fc89b3 PM |
464 | */ |
465 | int idx; | |
466 | int irqlevel = 0; | |
467 | int fiqlevel = 0; | |
c5fc89b3 PM |
468 | |
469 | idx = hppvi_index(cs); | |
c3f21b06 PM |
470 | trace_gicv3_cpuif_virt_update(gicv3_redist_affid(cs), idx, |
471 | cs->hppvlpi.irq, cs->hppvlpi.grp, | |
472 | cs->hppvlpi.prio); | |
473 | if (idx == HPPVI_INDEX_VLPI) { | |
474 | if (icv_hppvlpi_can_preempt(cs)) { | |
475 | if (cs->hppvlpi.grp == GICV3_G0) { | |
476 | fiqlevel = 1; | |
477 | } else { | |
478 | irqlevel = 1; | |
479 | } | |
480 | } | |
481 | } else if (idx >= 0) { | |
c5fc89b3 PM |
482 | uint64_t lr = cs->ich_lr_el2[idx]; |
483 | ||
484 | if (icv_hppi_can_preempt(cs, lr)) { | |
485 | /* Virtual interrupts are simple: G0 are always FIQ, and G1 IRQ */ | |
486 | if (lr & ICH_LR_EL2_GROUP) { | |
487 | irqlevel = 1; | |
488 | } else { | |
489 | fiqlevel = 1; | |
490 | } | |
491 | } | |
492 | } | |
493 | ||
10337638 PM |
494 | trace_gicv3_cpuif_virt_set_irqs(gicv3_redist_affid(cs), fiqlevel, irqlevel); |
495 | qemu_set_irq(cs->parent_vfiq, fiqlevel); | |
496 | qemu_set_irq(cs->parent_virq, irqlevel); | |
497 | } | |
498 | ||
499 | static void gicv3_cpuif_virt_update(GICv3CPUState *cs) | |
500 | { | |
501 | /* | |
502 | * Tell the CPU about any pending virtual interrupts or | |
503 | * maintenance interrupts, following a change to the state | |
504 | * of the CPU interface relevant to virtual interrupts. | |
505 | * | |
506 | * CAUTION: this function will call qemu_set_irq() on the | |
507 | * CPU maintenance IRQ line, which is typically wired up | |
508 | * to the GIC as a per-CPU interrupt. This means that it | |
509 | * will recursively call back into the GIC code via | |
510 | * gicv3_redist_set_irq() and thus into the CPU interface code's | |
511 | * gicv3_cpuif_update(). It is therefore important that this | |
512 | * function is only called as the final action of a CPU interface | |
513 | * register write implementation, after all the GIC state | |
514 | * fields have been updated. gicv3_cpuif_update() also must | |
515 | * not cause this function to be called, but that happens | |
516 | * naturally as a result of there being no architectural | |
517 | * linkage between the physical and virtual GIC logic. | |
518 | */ | |
519 | ARMCPU *cpu = ARM_CPU(cs->cpu); | |
520 | int maintlevel = 0; | |
521 | ||
522 | gicv3_cpuif_virt_irq_fiq_update(cs); | |
523 | ||
9cee1efe SM |
524 | if ((cs->ich_hcr_el2 & ICH_HCR_EL2_EN) && |
525 | maintenance_interrupt_state(cs) != 0) { | |
526 | maintlevel = 1; | |
c5fc89b3 PM |
527 | } |
528 | ||
10337638 | 529 | trace_gicv3_cpuif_virt_set_maint_irq(gicv3_redist_affid(cs), maintlevel); |
c20a135a | 530 | qemu_set_irq(cpu->gicv3_maintenance_interrupt, maintlevel); |
83f036fe PM |
531 | } |
532 | ||
77620ba6 PM |
533 | static uint64_t icv_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) |
534 | { | |
535 | GICv3CPUState *cs = icc_cs_from_env(env); | |
536 | int regno = ri->opc2 & 3; | |
887aae10 | 537 | int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0; |
77620ba6 PM |
538 | uint64_t value = cs->ich_apr[grp][regno]; |
539 | ||
540 | trace_gicv3_icv_ap_read(ri->crm & 1, regno, gicv3_redist_affid(cs), value); | |
541 | return value; | |
542 | } | |
543 | ||
544 | static void icv_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
545 | uint64_t value) | |
546 | { | |
547 | GICv3CPUState *cs = icc_cs_from_env(env); | |
548 | int regno = ri->opc2 & 3; | |
887aae10 | 549 | int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0; |
77620ba6 PM |
550 | |
551 | trace_gicv3_icv_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value); | |
552 | ||
553 | cs->ich_apr[grp][regno] = value & 0xFFFFFFFFU; | |
554 | ||
189d1d9d | 555 | gicv3_cpuif_virt_irq_fiq_update(cs); |
77620ba6 PM |
556 | return; |
557 | } | |
558 | ||
559 | static uint64_t icv_bpr_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
560 | { | |
561 | GICv3CPUState *cs = icc_cs_from_env(env); | |
562 | int grp = (ri->crm == 8) ? GICV3_G0 : GICV3_G1NS; | |
563 | uint64_t bpr; | |
564 | bool satinc = false; | |
565 | ||
566 | if (grp == GICV3_G1NS && (cs->ich_vmcr_el2 & ICH_VMCR_EL2_VCBPR)) { | |
567 | /* reads return bpr0 + 1 saturated to 7, writes ignored */ | |
568 | grp = GICV3_G0; | |
569 | satinc = true; | |
570 | } | |
571 | ||
572 | bpr = read_vbpr(cs, grp); | |
573 | ||
574 | if (satinc) { | |
575 | bpr++; | |
576 | bpr = MIN(bpr, 7); | |
577 | } | |
578 | ||
579 | trace_gicv3_icv_bpr_read(ri->crm == 8 ? 0 : 1, gicv3_redist_affid(cs), bpr); | |
580 | ||
581 | return bpr; | |
582 | } | |
583 | ||
584 | static void icv_bpr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
585 | uint64_t value) | |
586 | { | |
587 | GICv3CPUState *cs = icc_cs_from_env(env); | |
588 | int grp = (ri->crm == 8) ? GICV3_G0 : GICV3_G1NS; | |
589 | ||
590 | trace_gicv3_icv_bpr_write(ri->crm == 8 ? 0 : 1, | |
591 | gicv3_redist_affid(cs), value); | |
592 | ||
593 | if (grp == GICV3_G1NS && (cs->ich_vmcr_el2 & ICH_VMCR_EL2_VCBPR)) { | |
594 | /* reads return bpr0 + 1 saturated to 7, writes ignored */ | |
595 | return; | |
596 | } | |
597 | ||
598 | write_vbpr(cs, grp, value); | |
599 | ||
189d1d9d | 600 | gicv3_cpuif_virt_irq_fiq_update(cs); |
77620ba6 PM |
601 | } |
602 | ||
603 | static uint64_t icv_pmr_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
604 | { | |
605 | GICv3CPUState *cs = icc_cs_from_env(env); | |
606 | uint64_t value; | |
607 | ||
608 | value = extract64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VPMR_SHIFT, | |
609 | ICH_VMCR_EL2_VPMR_LENGTH); | |
610 | ||
611 | trace_gicv3_icv_pmr_read(gicv3_redist_affid(cs), value); | |
612 | return value; | |
613 | } | |
614 | ||
615 | static void icv_pmr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
616 | uint64_t value) | |
617 | { | |
618 | GICv3CPUState *cs = icc_cs_from_env(env); | |
619 | ||
620 | trace_gicv3_icv_pmr_write(gicv3_redist_affid(cs), value); | |
621 | ||
622 | value &= icv_fullprio_mask(cs); | |
623 | ||
624 | cs->ich_vmcr_el2 = deposit64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VPMR_SHIFT, | |
625 | ICH_VMCR_EL2_VPMR_LENGTH, value); | |
626 | ||
189d1d9d | 627 | gicv3_cpuif_virt_irq_fiq_update(cs); |
77620ba6 PM |
628 | } |
629 | ||
630 | static uint64_t icv_igrpen_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
631 | { | |
632 | GICv3CPUState *cs = icc_cs_from_env(env); | |
633 | int enbit; | |
634 | uint64_t value; | |
635 | ||
636 | enbit = ri->opc2 & 1 ? ICH_VMCR_EL2_VENG1_SHIFT : ICH_VMCR_EL2_VENG0_SHIFT; | |
637 | value = extract64(cs->ich_vmcr_el2, enbit, 1); | |
638 | ||
639 | trace_gicv3_icv_igrpen_read(ri->opc2 & 1 ? 1 : 0, | |
640 | gicv3_redist_affid(cs), value); | |
641 | return value; | |
642 | } | |
643 | ||
644 | static void icv_igrpen_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
645 | uint64_t value) | |
646 | { | |
647 | GICv3CPUState *cs = icc_cs_from_env(env); | |
648 | int enbit; | |
649 | ||
650 | trace_gicv3_icv_igrpen_write(ri->opc2 & 1 ? 1 : 0, | |
651 | gicv3_redist_affid(cs), value); | |
652 | ||
653 | enbit = ri->opc2 & 1 ? ICH_VMCR_EL2_VENG1_SHIFT : ICH_VMCR_EL2_VENG0_SHIFT; | |
654 | ||
655 | cs->ich_vmcr_el2 = deposit64(cs->ich_vmcr_el2, enbit, 1, value); | |
656 | gicv3_cpuif_virt_update(cs); | |
657 | } | |
658 | ||
659 | static uint64_t icv_ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
660 | { | |
661 | GICv3CPUState *cs = icc_cs_from_env(env); | |
662 | uint64_t value; | |
663 | ||
664 | /* Note that the fixed fields here (A3V, SEIS, IDbits, PRIbits) | |
665 | * should match the ones reported in ich_vtr_read(). | |
666 | */ | |
667 | value = ICC_CTLR_EL1_A3V | (1 << ICC_CTLR_EL1_IDBITS_SHIFT) | | |
9c6f933e | 668 | ((cs->vpribits - 1) << ICC_CTLR_EL1_PRIBITS_SHIFT); |
77620ba6 PM |
669 | |
670 | if (cs->ich_vmcr_el2 & ICH_VMCR_EL2_VEOIM) { | |
671 | value |= ICC_CTLR_EL1_EOIMODE; | |
672 | } | |
673 | ||
674 | if (cs->ich_vmcr_el2 & ICH_VMCR_EL2_VCBPR) { | |
675 | value |= ICC_CTLR_EL1_CBPR; | |
676 | } | |
677 | ||
678 | trace_gicv3_icv_ctlr_read(gicv3_redist_affid(cs), value); | |
679 | return value; | |
680 | } | |
681 | ||
682 | static void icv_ctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
683 | uint64_t value) | |
684 | { | |
685 | GICv3CPUState *cs = icc_cs_from_env(env); | |
686 | ||
687 | trace_gicv3_icv_ctlr_write(gicv3_redist_affid(cs), value); | |
688 | ||
689 | cs->ich_vmcr_el2 = deposit64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VCBPR_SHIFT, | |
690 | 1, value & ICC_CTLR_EL1_CBPR ? 1 : 0); | |
691 | cs->ich_vmcr_el2 = deposit64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VEOIM_SHIFT, | |
692 | 1, value & ICC_CTLR_EL1_EOIMODE ? 1 : 0); | |
693 | ||
189d1d9d | 694 | gicv3_cpuif_virt_irq_fiq_update(cs); |
77620ba6 PM |
695 | } |
696 | ||
df313f48 PM |
697 | static uint64_t icv_rpr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
698 | { | |
699 | GICv3CPUState *cs = icc_cs_from_env(env); | |
700 | int prio = ich_highest_active_virt_prio(cs); | |
701 | ||
702 | trace_gicv3_icv_rpr_read(gicv3_redist_affid(cs), prio); | |
703 | return prio; | |
704 | } | |
705 | ||
706 | static uint64_t icv_hppir_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
707 | { | |
708 | GICv3CPUState *cs = icc_cs_from_env(env); | |
709 | int grp = ri->crm == 8 ? GICV3_G0 : GICV3_G1NS; | |
710 | int idx = hppvi_index(cs); | |
711 | uint64_t value = INTID_SPURIOUS; | |
712 | ||
c3f21b06 PM |
713 | if (idx == HPPVI_INDEX_VLPI) { |
714 | if (cs->hppvlpi.grp == grp) { | |
715 | value = cs->hppvlpi.irq; | |
716 | } | |
717 | } else if (idx >= 0) { | |
df313f48 PM |
718 | uint64_t lr = cs->ich_lr_el2[idx]; |
719 | int thisgrp = (lr & ICH_LR_EL2_GROUP) ? GICV3_G1NS : GICV3_G0; | |
720 | ||
721 | if (grp == thisgrp) { | |
722 | value = ich_lr_vintid(lr); | |
723 | } | |
724 | } | |
725 | ||
cf734c2a PM |
726 | trace_gicv3_icv_hppir_read(ri->crm == 8 ? 0 : 1, |
727 | gicv3_redist_affid(cs), value); | |
df313f48 PM |
728 | return value; |
729 | } | |
730 | ||
b3b48f52 PM |
731 | static void icv_activate_irq(GICv3CPUState *cs, int idx, int grp) |
732 | { | |
733 | /* Activate the interrupt in the specified list register | |
734 | * by moving it from Pending to Active state, and update the | |
735 | * Active Priority Registers. | |
736 | */ | |
737 | uint32_t mask = icv_gprio_mask(cs, grp); | |
738 | int prio = ich_lr_prio(cs->ich_lr_el2[idx]) & mask; | |
739 | int aprbit = prio >> (8 - cs->vprebits); | |
740 | int regno = aprbit / 32; | |
741 | int regbit = aprbit % 32; | |
742 | ||
743 | cs->ich_lr_el2[idx] &= ~ICH_LR_EL2_STATE_PENDING_BIT; | |
744 | cs->ich_lr_el2[idx] |= ICH_LR_EL2_STATE_ACTIVE_BIT; | |
745 | cs->ich_apr[grp][regno] |= (1 << regbit); | |
746 | } | |
747 | ||
c3f21b06 PM |
748 | static void icv_activate_vlpi(GICv3CPUState *cs) |
749 | { | |
750 | uint32_t mask = icv_gprio_mask(cs, cs->hppvlpi.grp); | |
751 | int prio = cs->hppvlpi.prio & mask; | |
752 | int aprbit = prio >> (8 - cs->vprebits); | |
753 | int regno = aprbit / 32; | |
754 | int regbit = aprbit % 32; | |
755 | ||
756 | cs->ich_apr[cs->hppvlpi.grp][regno] |= (1 << regbit); | |
757 | gicv3_redist_vlpi_pending(cs, cs->hppvlpi.irq, 0); | |
758 | } | |
759 | ||
b3b48f52 PM |
760 | static uint64_t icv_iar_read(CPUARMState *env, const ARMCPRegInfo *ri) |
761 | { | |
762 | GICv3CPUState *cs = icc_cs_from_env(env); | |
763 | int grp = ri->crm == 8 ? GICV3_G0 : GICV3_G1NS; | |
764 | int idx = hppvi_index(cs); | |
765 | uint64_t intid = INTID_SPURIOUS; | |
766 | ||
c3f21b06 PM |
767 | if (idx == HPPVI_INDEX_VLPI) { |
768 | if (cs->hppvlpi.grp == grp && icv_hppvlpi_can_preempt(cs)) { | |
769 | intid = cs->hppvlpi.irq; | |
770 | icv_activate_vlpi(cs); | |
771 | } | |
772 | } else if (idx >= 0) { | |
b3b48f52 PM |
773 | uint64_t lr = cs->ich_lr_el2[idx]; |
774 | int thisgrp = (lr & ICH_LR_EL2_GROUP) ? GICV3_G1NS : GICV3_G0; | |
775 | ||
776 | if (thisgrp == grp && icv_hppi_can_preempt(cs, lr)) { | |
777 | intid = ich_lr_vintid(lr); | |
90feffad | 778 | if (!gicv3_intid_is_special(intid)) { |
b3b48f52 PM |
779 | icv_activate_irq(cs, idx, grp); |
780 | } else { | |
781 | /* Interrupt goes from Pending to Invalid */ | |
782 | cs->ich_lr_el2[idx] &= ~ICH_LR_EL2_STATE_PENDING_BIT; | |
783 | /* We will now return the (bogus) ID from the list register, | |
784 | * as per the pseudocode. | |
785 | */ | |
786 | } | |
787 | } | |
788 | } | |
789 | ||
790 | trace_gicv3_icv_iar_read(ri->crm == 8 ? 0 : 1, | |
791 | gicv3_redist_affid(cs), intid); | |
ef125521 JK |
792 | |
793 | gicv3_cpuif_virt_update(cs); | |
794 | ||
b3b48f52 PM |
795 | return intid; |
796 | } | |
797 | ||
84597ff3 PM |
798 | static uint32_t icc_fullprio_mask(GICv3CPUState *cs) |
799 | { | |
800 | /* | |
801 | * Return a mask word which clears the unimplemented priority bits | |
802 | * from a priority value for a physical interrupt. (Not to be confused | |
803 | * with the group priority, whose mask depends on the value of BPR | |
804 | * for the interrupt group.) | |
805 | */ | |
70726a15 | 806 | return (~0U << (8 - cs->pribits)) & 0xff; |
84597ff3 PM |
807 | } |
808 | ||
809 | static inline int icc_min_bpr(GICv3CPUState *cs) | |
810 | { | |
811 | /* The minimum BPR for the physical interface. */ | |
812 | return 7 - cs->prebits; | |
813 | } | |
814 | ||
815 | static inline int icc_min_bpr_ns(GICv3CPUState *cs) | |
816 | { | |
817 | return icc_min_bpr(cs) + 1; | |
818 | } | |
819 | ||
820 | static inline int icc_num_aprs(GICv3CPUState *cs) | |
821 | { | |
822 | /* Return the number of APR registers (1, 2, or 4) */ | |
823 | int aprmax = 1 << MAX(cs->prebits - 5, 0); | |
824 | assert(aprmax <= ARRAY_SIZE(cs->icc_apr[0])); | |
825 | return aprmax; | |
826 | } | |
827 | ||
f7b9358e PM |
828 | static int icc_highest_active_prio(GICv3CPUState *cs) |
829 | { | |
830 | /* Calculate the current running priority based on the set bits | |
831 | * in the Active Priority Registers. | |
832 | */ | |
833 | int i; | |
834 | ||
84597ff3 | 835 | for (i = 0; i < icc_num_aprs(cs); i++) { |
f7b9358e PM |
836 | uint32_t apr = cs->icc_apr[GICV3_G0][i] | |
837 | cs->icc_apr[GICV3_G1][i] | cs->icc_apr[GICV3_G1NS][i]; | |
838 | ||
839 | if (!apr) { | |
840 | continue; | |
841 | } | |
84597ff3 | 842 | return (i * 32 + ctz32(apr)) << (icc_min_bpr(cs) + 1); |
f7b9358e PM |
843 | } |
844 | /* No current active interrupts: return idle priority */ | |
845 | return 0xff; | |
846 | } | |
847 | ||
848 | static uint32_t icc_gprio_mask(GICv3CPUState *cs, int group) | |
849 | { | |
850 | /* Return a mask word which clears the subpriority bits from | |
851 | * a priority value for an interrupt in the specified group. | |
a89ff39e | 852 | * This depends on the BPR value. For CBPR0 (S or NS): |
f7b9358e PM |
853 | * a BPR of 0 means the group priority bits are [7:1]; |
854 | * a BPR of 1 means they are [7:2], and so on down to | |
855 | * a BPR of 7 meaning no group priority bits at all. | |
a89ff39e PM |
856 | * For CBPR1 NS: |
857 | * a BPR of 0 is impossible (the minimum value is 1) | |
858 | * a BPR of 1 means the group priority bits are [7:1]; | |
859 | * a BPR of 2 means they are [7:2], and so on down to | |
860 | * a BPR of 7 meaning the group priority is [7]. | |
861 | * | |
f7b9358e PM |
862 | * Which BPR to use depends on the group of the interrupt and |
863 | * the current ICC_CTLR.CBPR settings. | |
a89ff39e PM |
864 | * |
865 | * This corresponds to the GroupBits() pseudocode. | |
f7b9358e | 866 | */ |
a89ff39e PM |
867 | int bpr; |
868 | ||
f7b9358e PM |
869 | if ((group == GICV3_G1 && cs->icc_ctlr_el1[GICV3_S] & ICC_CTLR_EL1_CBPR) || |
870 | (group == GICV3_G1NS && | |
871 | cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_CBPR)) { | |
872 | group = GICV3_G0; | |
873 | } | |
874 | ||
a89ff39e PM |
875 | bpr = cs->icc_bpr[group] & 7; |
876 | ||
877 | if (group == GICV3_G1NS) { | |
878 | assert(bpr > 0); | |
879 | bpr--; | |
880 | } | |
881 | ||
882 | return ~0U << (bpr + 1); | |
f7b9358e PM |
883 | } |
884 | ||
885 | static bool icc_no_enabled_hppi(GICv3CPUState *cs) | |
886 | { | |
887 | /* Return true if there is no pending interrupt, or the | |
888 | * highest priority pending interrupt is in a group which has been | |
889 | * disabled at the CPU interface by the ICC_IGRPEN* register enable bits. | |
890 | */ | |
891 | return cs->hppi.prio == 0xff || (cs->icc_igrpen[cs->hppi.grp] == 0); | |
892 | } | |
893 | ||
894 | static bool icc_hppi_can_preempt(GICv3CPUState *cs) | |
895 | { | |
896 | /* Return true if we have a pending interrupt of sufficient | |
897 | * priority to preempt. | |
898 | */ | |
899 | int rprio; | |
900 | uint32_t mask; | |
901 | ||
902 | if (icc_no_enabled_hppi(cs)) { | |
903 | return false; | |
904 | } | |
905 | ||
906 | if (cs->hppi.prio >= cs->icc_pmr_el1) { | |
907 | /* Priority mask masks this interrupt */ | |
908 | return false; | |
909 | } | |
910 | ||
911 | rprio = icc_highest_active_prio(cs); | |
912 | if (rprio == 0xff) { | |
913 | /* No currently running interrupt so we can preempt */ | |
914 | return true; | |
915 | } | |
916 | ||
917 | mask = icc_gprio_mask(cs, cs->hppi.grp); | |
918 | ||
919 | /* We only preempt a running interrupt if the pending interrupt's | |
920 | * group priority is sufficient (the subpriorities are not considered). | |
921 | */ | |
922 | if ((cs->hppi.prio & mask) < (rprio & mask)) { | |
923 | return true; | |
924 | } | |
925 | ||
926 | return false; | |
927 | } | |
928 | ||
929 | void gicv3_cpuif_update(GICv3CPUState *cs) | |
930 | { | |
931 | /* Tell the CPU about its highest priority pending interrupt */ | |
932 | int irqlevel = 0; | |
933 | int fiqlevel = 0; | |
934 | ARMCPU *cpu = ARM_CPU(cs->cpu); | |
935 | CPUARMState *env = &cpu->env; | |
936 | ||
195801d7 | 937 | g_assert(bql_locked()); |
8d04fb55 | 938 | |
f7b9358e PM |
939 | trace_gicv3_cpuif_update(gicv3_redist_affid(cs), cs->hppi.irq, |
940 | cs->hppi.grp, cs->hppi.prio); | |
941 | ||
942 | if (cs->hppi.grp == GICV3_G1 && !arm_feature(env, ARM_FEATURE_EL3)) { | |
943 | /* If a Security-enabled GIC sends a G1S interrupt to a | |
944 | * Security-disabled CPU, we must treat it as if it were G0. | |
945 | */ | |
946 | cs->hppi.grp = GICV3_G0; | |
947 | } | |
948 | ||
949 | if (icc_hppi_can_preempt(cs)) { | |
950 | /* We have an interrupt: should we signal it as IRQ or FIQ? | |
951 | * This is described in the GICv3 spec section 4.6.2. | |
952 | */ | |
953 | bool isfiq; | |
954 | ||
955 | switch (cs->hppi.grp) { | |
956 | case GICV3_G0: | |
957 | isfiq = true; | |
958 | break; | |
959 | case GICV3_G1: | |
960 | isfiq = (!arm_is_secure(env) || | |
961 | (arm_current_el(env) == 3 && arm_el_is_aa64(env, 3))); | |
962 | break; | |
963 | case GICV3_G1NS: | |
964 | isfiq = arm_is_secure(env); | |
965 | break; | |
966 | default: | |
967 | g_assert_not_reached(); | |
968 | } | |
969 | ||
970 | if (isfiq) { | |
971 | fiqlevel = 1; | |
972 | } else { | |
973 | irqlevel = 1; | |
974 | } | |
975 | } | |
976 | ||
977 | trace_gicv3_cpuif_set_irqs(gicv3_redist_affid(cs), fiqlevel, irqlevel); | |
978 | ||
979 | qemu_set_irq(cs->parent_fiq, fiqlevel); | |
980 | qemu_set_irq(cs->parent_irq, irqlevel); | |
981 | } | |
982 | ||
359fbe65 PM |
983 | static uint64_t icc_pmr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
984 | { | |
985 | GICv3CPUState *cs = icc_cs_from_env(env); | |
986 | uint32_t value = cs->icc_pmr_el1; | |
987 | ||
77620ba6 PM |
988 | if (icv_access(env, HCR_FMO | HCR_IMO)) { |
989 | return icv_pmr_read(env, ri); | |
990 | } | |
991 | ||
359fbe65 PM |
992 | if (arm_feature(env, ARM_FEATURE_EL3) && !arm_is_secure(env) && |
993 | (env->cp15.scr_el3 & SCR_FIQ)) { | |
994 | /* NS access and Group 0 is inaccessible to NS: return the | |
995 | * NS view of the current priority | |
996 | */ | |
a2e2d7fc | 997 | if ((value & 0x80) == 0) { |
359fbe65 PM |
998 | /* Secure priorities not visible to NS */ |
999 | value = 0; | |
1000 | } else if (value != 0xff) { | |
1001 | value = (value << 1) & 0xff; | |
1002 | } | |
1003 | } | |
1004 | ||
1005 | trace_gicv3_icc_pmr_read(gicv3_redist_affid(cs), value); | |
1006 | ||
1007 | return value; | |
1008 | } | |
1009 | ||
1010 | static void icc_pmr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1011 | uint64_t value) | |
1012 | { | |
1013 | GICv3CPUState *cs = icc_cs_from_env(env); | |
1014 | ||
77620ba6 PM |
1015 | if (icv_access(env, HCR_FMO | HCR_IMO)) { |
1016 | return icv_pmr_write(env, ri, value); | |
1017 | } | |
1018 | ||
359fbe65 PM |
1019 | trace_gicv3_icc_pmr_write(gicv3_redist_affid(cs), value); |
1020 | ||
359fbe65 PM |
1021 | if (arm_feature(env, ARM_FEATURE_EL3) && !arm_is_secure(env) && |
1022 | (env->cp15.scr_el3 & SCR_FIQ)) { | |
1023 | /* NS access and Group 0 is inaccessible to NS: return the | |
1024 | * NS view of the current priority | |
1025 | */ | |
1026 | if (!(cs->icc_pmr_el1 & 0x80)) { | |
1027 | /* Current PMR in the secure range, don't allow NS to change it */ | |
1028 | return; | |
1029 | } | |
a2e2d7fc | 1030 | value = (value >> 1) | 0x80; |
359fbe65 | 1031 | } |
d9721f19 | 1032 | value &= icc_fullprio_mask(cs); |
359fbe65 PM |
1033 | cs->icc_pmr_el1 = value; |
1034 | gicv3_cpuif_update(cs); | |
1035 | } | |
1036 | ||
227a8653 PM |
1037 | static void icc_activate_irq(GICv3CPUState *cs, int irq) |
1038 | { | |
1039 | /* Move the interrupt from the Pending state to Active, and update | |
1040 | * the Active Priority Registers | |
1041 | */ | |
1042 | uint32_t mask = icc_gprio_mask(cs, cs->hppi.grp); | |
1043 | int prio = cs->hppi.prio & mask; | |
84597ff3 | 1044 | int aprbit = prio >> (8 - cs->prebits); |
227a8653 PM |
1045 | int regno = aprbit / 32; |
1046 | int regbit = aprbit % 32; | |
1047 | ||
1048 | cs->icc_apr[cs->hppi.grp][regno] |= (1 << regbit); | |
1049 | ||
1050 | if (irq < GIC_INTERNAL) { | |
1051 | cs->gicr_iactiver0 = deposit32(cs->gicr_iactiver0, irq, 1, 1); | |
1052 | cs->gicr_ipendr0 = deposit32(cs->gicr_ipendr0, irq, 1, 0); | |
1053 | gicv3_redist_update(cs); | |
17fb5e36 | 1054 | } else if (irq < GICV3_LPI_INTID_START) { |
227a8653 PM |
1055 | gicv3_gicd_active_set(cs->gic, irq); |
1056 | gicv3_gicd_pending_clear(cs->gic, irq); | |
1057 | gicv3_update(cs->gic, irq, 1); | |
17fb5e36 SM |
1058 | } else { |
1059 | gicv3_redist_lpi_pending(cs, irq, 0); | |
227a8653 PM |
1060 | } |
1061 | } | |
1062 | ||
1063 | static uint64_t icc_hppir0_value(GICv3CPUState *cs, CPUARMState *env) | |
1064 | { | |
1065 | /* Return the highest priority pending interrupt register value | |
1066 | * for group 0. | |
1067 | */ | |
1068 | bool irq_is_secure; | |
1069 | ||
1070 | if (cs->hppi.prio == 0xff) { | |
1071 | return INTID_SPURIOUS; | |
1072 | } | |
1073 | ||
1074 | /* Check whether we can return the interrupt or if we should return | |
1075 | * a special identifier, as per the CheckGroup0ForSpecialIdentifiers | |
1076 | * pseudocode. (We can simplify a little because for us ICC_SRE_EL1.RM | |
1077 | * is always zero.) | |
1078 | */ | |
1079 | irq_is_secure = (!(cs->gic->gicd_ctlr & GICD_CTLR_DS) && | |
1080 | (cs->hppi.grp != GICV3_G1NS)); | |
1081 | ||
1082 | if (cs->hppi.grp != GICV3_G0 && !arm_is_el3_or_mon(env)) { | |
1083 | return INTID_SPURIOUS; | |
1084 | } | |
1085 | if (irq_is_secure && !arm_is_secure(env)) { | |
1086 | /* Secure interrupts not visible to Nonsecure */ | |
1087 | return INTID_SPURIOUS; | |
1088 | } | |
1089 | ||
1090 | if (cs->hppi.grp != GICV3_G0) { | |
1091 | /* Indicate to EL3 that there's a Group 1 interrupt for the other | |
1092 | * state pending. | |
1093 | */ | |
1094 | return irq_is_secure ? INTID_SECURE : INTID_NONSECURE; | |
1095 | } | |
1096 | ||
1097 | return cs->hppi.irq; | |
1098 | } | |
1099 | ||
1100 | static uint64_t icc_hppir1_value(GICv3CPUState *cs, CPUARMState *env) | |
1101 | { | |
1102 | /* Return the highest priority pending interrupt register value | |
1103 | * for group 1. | |
1104 | */ | |
1105 | bool irq_is_secure; | |
1106 | ||
1107 | if (cs->hppi.prio == 0xff) { | |
1108 | return INTID_SPURIOUS; | |
1109 | } | |
1110 | ||
1111 | /* Check whether we can return the interrupt or if we should return | |
1112 | * a special identifier, as per the CheckGroup1ForSpecialIdentifiers | |
1113 | * pseudocode. (We can simplify a little because for us ICC_SRE_EL1.RM | |
1114 | * is always zero.) | |
1115 | */ | |
1116 | irq_is_secure = (!(cs->gic->gicd_ctlr & GICD_CTLR_DS) && | |
1117 | (cs->hppi.grp != GICV3_G1NS)); | |
1118 | ||
1119 | if (cs->hppi.grp == GICV3_G0) { | |
1120 | /* Group 0 interrupts not visible via HPPIR1 */ | |
1121 | return INTID_SPURIOUS; | |
1122 | } | |
1123 | if (irq_is_secure) { | |
1124 | if (!arm_is_secure(env)) { | |
1125 | /* Secure interrupts not visible in Non-secure */ | |
1126 | return INTID_SPURIOUS; | |
1127 | } | |
1128 | } else if (!arm_is_el3_or_mon(env) && arm_is_secure(env)) { | |
1129 | /* Group 1 non-secure interrupts not visible in Secure EL1 */ | |
1130 | return INTID_SPURIOUS; | |
1131 | } | |
1132 | ||
1133 | return cs->hppi.irq; | |
1134 | } | |
1135 | ||
1136 | static uint64_t icc_iar0_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
1137 | { | |
1138 | GICv3CPUState *cs = icc_cs_from_env(env); | |
1139 | uint64_t intid; | |
1140 | ||
b3b48f52 PM |
1141 | if (icv_access(env, HCR_FMO)) { |
1142 | return icv_iar_read(env, ri); | |
1143 | } | |
1144 | ||
227a8653 PM |
1145 | if (!icc_hppi_can_preempt(cs)) { |
1146 | intid = INTID_SPURIOUS; | |
1147 | } else { | |
1148 | intid = icc_hppir0_value(cs, env); | |
1149 | } | |
1150 | ||
b74d7c0e | 1151 | if (!gicv3_intid_is_special(intid)) { |
227a8653 PM |
1152 | icc_activate_irq(cs, intid); |
1153 | } | |
1154 | ||
1155 | trace_gicv3_icc_iar0_read(gicv3_redist_affid(cs), intid); | |
1156 | return intid; | |
1157 | } | |
1158 | ||
1159 | static uint64_t icc_iar1_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
1160 | { | |
1161 | GICv3CPUState *cs = icc_cs_from_env(env); | |
1162 | uint64_t intid; | |
1163 | ||
b3b48f52 PM |
1164 | if (icv_access(env, HCR_IMO)) { |
1165 | return icv_iar_read(env, ri); | |
1166 | } | |
1167 | ||
227a8653 PM |
1168 | if (!icc_hppi_can_preempt(cs)) { |
1169 | intid = INTID_SPURIOUS; | |
1170 | } else { | |
1171 | intid = icc_hppir1_value(cs, env); | |
1172 | } | |
1173 | ||
b74d7c0e | 1174 | if (!gicv3_intid_is_special(intid)) { |
227a8653 PM |
1175 | icc_activate_irq(cs, intid); |
1176 | } | |
1177 | ||
1178 | trace_gicv3_icc_iar1_read(gicv3_redist_affid(cs), intid); | |
1179 | return intid; | |
1180 | } | |
1181 | ||
1182 | static void icc_drop_prio(GICv3CPUState *cs, int grp) | |
1183 | { | |
1184 | /* Drop the priority of the currently active interrupt in | |
1185 | * the specified group. | |
1186 | * | |
1187 | * Note that we can guarantee (because of the requirement to nest | |
1188 | * ICC_IAR reads [which activate an interrupt and raise priority] | |
1189 | * with ICC_EOIR writes [which drop the priority for the interrupt]) | |
1190 | * that the interrupt we're being called for is the highest priority | |
1191 | * active interrupt, meaning that it has the lowest set bit in the | |
1192 | * APR registers. | |
1193 | * | |
1194 | * If the guest does not honour the ordering constraints then the | |
1195 | * behaviour of the GIC is UNPREDICTABLE, which for us means that | |
1196 | * the values of the APR registers might become incorrect and the | |
1197 | * running priority will be wrong, so interrupts that should preempt | |
1198 | * might not do so, and interrupts that should not preempt might do so. | |
1199 | */ | |
1200 | int i; | |
1201 | ||
84597ff3 | 1202 | for (i = 0; i < icc_num_aprs(cs); i++) { |
227a8653 PM |
1203 | uint64_t *papr = &cs->icc_apr[grp][i]; |
1204 | ||
1205 | if (!*papr) { | |
1206 | continue; | |
1207 | } | |
1208 | /* Clear the lowest set bit */ | |
1209 | *papr &= *papr - 1; | |
1210 | break; | |
1211 | } | |
1212 | ||
1213 | /* running priority change means we need an update for this cpu i/f */ | |
1214 | gicv3_cpuif_update(cs); | |
1215 | } | |
1216 | ||
1217 | static bool icc_eoi_split(CPUARMState *env, GICv3CPUState *cs) | |
1218 | { | |
1219 | /* Return true if we should split priority drop and interrupt | |
1220 | * deactivation, ie whether the relevant EOIMode bit is set. | |
1221 | */ | |
1222 | if (arm_is_el3_or_mon(env)) { | |
1223 | return cs->icc_ctlr_el3 & ICC_CTLR_EL3_EOIMODE_EL3; | |
1224 | } | |
1225 | if (arm_is_secure_below_el3(env)) { | |
1226 | return cs->icc_ctlr_el1[GICV3_S] & ICC_CTLR_EL1_EOIMODE; | |
1227 | } else { | |
1228 | return cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_EOIMODE; | |
1229 | } | |
1230 | } | |
1231 | ||
1232 | static int icc_highest_active_group(GICv3CPUState *cs) | |
1233 | { | |
1234 | /* Return the group with the highest priority active interrupt. | |
1235 | * We can do this by just comparing the APRs to see which one | |
1236 | * has the lowest set bit. | |
1237 | * (If more than one group is active at the same priority then | |
1238 | * we're in UNPREDICTABLE territory.) | |
1239 | */ | |
1240 | int i; | |
1241 | ||
1242 | for (i = 0; i < ARRAY_SIZE(cs->icc_apr[0]); i++) { | |
1243 | int g0ctz = ctz32(cs->icc_apr[GICV3_G0][i]); | |
1244 | int g1ctz = ctz32(cs->icc_apr[GICV3_G1][i]); | |
1245 | int g1nsctz = ctz32(cs->icc_apr[GICV3_G1NS][i]); | |
1246 | ||
1247 | if (g1nsctz < g0ctz && g1nsctz < g1ctz) { | |
1248 | return GICV3_G1NS; | |
1249 | } | |
1250 | if (g1ctz < g0ctz) { | |
1251 | return GICV3_G1; | |
1252 | } | |
1253 | if (g0ctz < 32) { | |
1254 | return GICV3_G0; | |
1255 | } | |
1256 | } | |
1257 | /* No set active bits? UNPREDICTABLE; return -1 so the caller | |
1258 | * ignores the spurious EOI attempt. | |
1259 | */ | |
1260 | return -1; | |
1261 | } | |
1262 | ||
1263 | static void icc_deactivate_irq(GICv3CPUState *cs, int irq) | |
1264 | { | |
1265 | if (irq < GIC_INTERNAL) { | |
1266 | cs->gicr_iactiver0 = deposit32(cs->gicr_iactiver0, irq, 1, 0); | |
1267 | gicv3_redist_update(cs); | |
1268 | } else { | |
1269 | gicv3_gicd_active_clear(cs->gic, irq); | |
1270 | gicv3_update(cs->gic, irq, 1); | |
1271 | } | |
1272 | } | |
1273 | ||
df313f48 PM |
1274 | static bool icv_eoi_split(CPUARMState *env, GICv3CPUState *cs) |
1275 | { | |
1276 | /* Return true if we should split priority drop and interrupt | |
1277 | * deactivation, ie whether the virtual EOIMode bit is set. | |
1278 | */ | |
1279 | return cs->ich_vmcr_el2 & ICH_VMCR_EL2_VEOIM; | |
1280 | } | |
1281 | ||
1282 | static int icv_find_active(GICv3CPUState *cs, int irq) | |
1283 | { | |
1284 | /* Given an interrupt number for an active interrupt, return the index | |
1285 | * of the corresponding list register, or -1 if there is no match. | |
1286 | * Corresponds to FindActiveVirtualInterrupt pseudocode. | |
1287 | */ | |
1288 | int i; | |
1289 | ||
1290 | for (i = 0; i < cs->num_list_regs; i++) { | |
1291 | uint64_t lr = cs->ich_lr_el2[i]; | |
1292 | ||
1293 | if ((lr & ICH_LR_EL2_STATE_ACTIVE_BIT) && ich_lr_vintid(lr) == irq) { | |
1294 | return i; | |
1295 | } | |
1296 | } | |
1297 | ||
1298 | return -1; | |
1299 | } | |
1300 | ||
1301 | static void icv_deactivate_irq(GICv3CPUState *cs, int idx) | |
1302 | { | |
1303 | /* Deactivate the interrupt in the specified list register index */ | |
1304 | uint64_t lr = cs->ich_lr_el2[idx]; | |
1305 | ||
1306 | if (lr & ICH_LR_EL2_HW) { | |
1307 | /* Deactivate the associated physical interrupt */ | |
1308 | int pirq = ich_lr_pintid(lr); | |
1309 | ||
1310 | if (pirq < INTID_SECURE) { | |
1311 | icc_deactivate_irq(cs, pirq); | |
1312 | } | |
1313 | } | |
1314 | ||
1315 | /* Clear the 'active' part of the state, so ActivePending->Pending | |
1316 | * and Active->Invalid. | |
1317 | */ | |
1318 | lr &= ~ICH_LR_EL2_STATE_ACTIVE_BIT; | |
1319 | cs->ich_lr_el2[idx] = lr; | |
1320 | } | |
1321 | ||
1322 | static void icv_increment_eoicount(GICv3CPUState *cs) | |
1323 | { | |
1324 | /* Increment the EOICOUNT field in ICH_HCR_EL2 */ | |
1325 | int eoicount = extract64(cs->ich_hcr_el2, ICH_HCR_EL2_EOICOUNT_SHIFT, | |
1326 | ICH_HCR_EL2_EOICOUNT_LENGTH); | |
1327 | ||
1328 | cs->ich_hcr_el2 = deposit64(cs->ich_hcr_el2, ICH_HCR_EL2_EOICOUNT_SHIFT, | |
1329 | ICH_HCR_EL2_EOICOUNT_LENGTH, eoicount + 1); | |
1330 | } | |
1331 | ||
b3b48f52 PM |
1332 | static int icv_drop_prio(GICv3CPUState *cs) |
1333 | { | |
1334 | /* Drop the priority of the currently active virtual interrupt | |
1335 | * (favouring group 0 if there is a set active bit at | |
1336 | * the same priority for both group 0 and group 1). | |
1337 | * Return the priority value for the bit we just cleared, | |
1338 | * or 0xff if no bits were set in the AP registers at all. | |
1339 | * Note that though the ich_apr[] are uint64_t only the low | |
1340 | * 32 bits are actually relevant. | |
1341 | */ | |
1342 | int i; | |
5d55f827 | 1343 | int aprmax = ich_num_aprs(cs); |
b3b48f52 PM |
1344 | |
1345 | for (i = 0; i < aprmax; i++) { | |
1346 | uint64_t *papr0 = &cs->ich_apr[GICV3_G0][i]; | |
1347 | uint64_t *papr1 = &cs->ich_apr[GICV3_G1NS][i]; | |
1348 | int apr0count, apr1count; | |
1349 | ||
1350 | if (!*papr0 && !*papr1) { | |
1351 | continue; | |
1352 | } | |
1353 | ||
1354 | /* We can't just use the bit-twiddling hack icc_drop_prio() does | |
1355 | * because we need to return the bit number we cleared so | |
1356 | * it can be compared against the list register's priority field. | |
1357 | */ | |
1358 | apr0count = ctz32(*papr0); | |
1359 | apr1count = ctz32(*papr1); | |
1360 | ||
1361 | if (apr0count <= apr1count) { | |
1362 | *papr0 &= *papr0 - 1; | |
1363 | return (apr0count + i * 32) << (icv_min_vbpr(cs) + 1); | |
1364 | } else { | |
1365 | *papr1 &= *papr1 - 1; | |
1366 | return (apr1count + i * 32) << (icv_min_vbpr(cs) + 1); | |
1367 | } | |
1368 | } | |
1369 | return 0xff; | |
1370 | } | |
1371 | ||
df313f48 PM |
1372 | static void icv_dir_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1373 | uint64_t value) | |
1374 | { | |
1375 | /* Deactivate interrupt */ | |
1376 | GICv3CPUState *cs = icc_cs_from_env(env); | |
1377 | int idx; | |
1378 | int irq = value & 0xffffff; | |
1379 | ||
1380 | trace_gicv3_icv_dir_write(gicv3_redist_affid(cs), value); | |
1381 | ||
f4ec71d0 | 1382 | if (irq >= GICV3_MAXIRQ) { |
df313f48 PM |
1383 | /* Also catches special interrupt numbers and LPIs */ |
1384 | return; | |
1385 | } | |
1386 | ||
1387 | if (!icv_eoi_split(env, cs)) { | |
1388 | return; | |
1389 | } | |
1390 | ||
1391 | idx = icv_find_active(cs, irq); | |
1392 | ||
1393 | if (idx < 0) { | |
1394 | /* No list register matching this, so increment the EOI count | |
1395 | * (might trigger a maintenance interrupt) | |
1396 | */ | |
1397 | icv_increment_eoicount(cs); | |
1398 | } else { | |
1399 | icv_deactivate_irq(cs, idx); | |
1400 | } | |
1401 | ||
1402 | gicv3_cpuif_virt_update(cs); | |
1403 | } | |
1404 | ||
b3b48f52 PM |
1405 | static void icv_eoir_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1406 | uint64_t value) | |
1407 | { | |
1408 | /* End of Interrupt */ | |
1409 | GICv3CPUState *cs = icc_cs_from_env(env); | |
1410 | int irq = value & 0xffffff; | |
1411 | int grp = ri->crm == 8 ? GICV3_G0 : GICV3_G1NS; | |
1412 | int idx, dropprio; | |
1413 | ||
1414 | trace_gicv3_icv_eoir_write(ri->crm == 8 ? 0 : 1, | |
1415 | gicv3_redist_affid(cs), value); | |
1416 | ||
90feffad | 1417 | if (gicv3_intid_is_special(irq)) { |
b3b48f52 PM |
1418 | return; |
1419 | } | |
1420 | ||
1421 | /* We implement the IMPDEF choice of "drop priority before doing | |
1422 | * error checks" (because that lets us avoid scanning the AP | |
1423 | * registers twice). | |
1424 | */ | |
1425 | dropprio = icv_drop_prio(cs); | |
1426 | if (dropprio == 0xff) { | |
1427 | /* No active interrupt. It is CONSTRAINED UNPREDICTABLE | |
1428 | * whether the list registers are checked in this | |
1429 | * situation; we choose not to. | |
1430 | */ | |
1431 | return; | |
1432 | } | |
1433 | ||
1434 | idx = icv_find_active(cs, irq); | |
1435 | ||
1436 | if (idx < 0) { | |
1437 | /* No valid list register corresponding to EOI ID */ | |
1438 | icv_increment_eoicount(cs); | |
1439 | } else { | |
1440 | uint64_t lr = cs->ich_lr_el2[idx]; | |
1441 | int thisgrp = (lr & ICH_LR_EL2_GROUP) ? GICV3_G1NS : GICV3_G0; | |
1442 | int lr_gprio = ich_lr_prio(lr) & icv_gprio_mask(cs, grp); | |
1443 | ||
1444 | if (thisgrp == grp && lr_gprio == dropprio) { | |
1445 | if (!icv_eoi_split(env, cs)) { | |
1446 | /* Priority drop and deactivate not split: deactivate irq now */ | |
1447 | icv_deactivate_irq(cs, idx); | |
1448 | } | |
1449 | } | |
1450 | } | |
1451 | ||
1452 | gicv3_cpuif_virt_update(cs); | |
1453 | } | |
1454 | ||
227a8653 PM |
1455 | static void icc_eoir_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1456 | uint64_t value) | |
1457 | { | |
1458 | /* End of Interrupt */ | |
1459 | GICv3CPUState *cs = icc_cs_from_env(env); | |
1460 | int irq = value & 0xffffff; | |
1461 | int grp; | |
382c7160 | 1462 | bool is_eoir0 = ri->crm == 8; |
227a8653 | 1463 | |
382c7160 | 1464 | if (icv_access(env, is_eoir0 ? HCR_FMO : HCR_IMO)) { |
b3b48f52 PM |
1465 | icv_eoir_write(env, ri, value); |
1466 | return; | |
1467 | } | |
1468 | ||
382c7160 | 1469 | trace_gicv3_icc_eoir_write(is_eoir0 ? 0 : 1, |
081b1b98 | 1470 | gicv3_redist_affid(cs), value); |
227a8653 | 1471 | |
17fb5e36 SM |
1472 | if ((irq >= cs->gic->num_irq) && |
1473 | !(cs->gic->lpi_enable && (irq >= GICV3_LPI_INTID_START))) { | |
227a8653 PM |
1474 | /* This handles two cases: |
1475 | * 1. If software writes the ID of a spurious interrupt [ie 1020-1023] | |
1476 | * to the GICC_EOIR, the GIC ignores that write. | |
1477 | * 2. If software writes the number of a non-existent interrupt | |
1478 | * this must be a subcase of "value written does not match the last | |
1479 | * valid interrupt value read from the Interrupt Acknowledge | |
1480 | * register" and so this is UNPREDICTABLE. We choose to ignore it. | |
1481 | */ | |
1482 | return; | |
1483 | } | |
1484 | ||
382c7160 PM |
1485 | grp = icc_highest_active_group(cs); |
1486 | switch (grp) { | |
1487 | case GICV3_G0: | |
1488 | if (!is_eoir0) { | |
1489 | return; | |
1490 | } | |
1491 | if (!(cs->gic->gicd_ctlr & GICD_CTLR_DS) | |
1492 | && arm_feature(env, ARM_FEATURE_EL3) && !arm_is_secure(env)) { | |
1493 | return; | |
1494 | } | |
1495 | break; | |
1496 | case GICV3_G1: | |
1497 | if (is_eoir0) { | |
1498 | return; | |
1499 | } | |
1500 | if (!arm_is_secure(env)) { | |
1501 | return; | |
1502 | } | |
1503 | break; | |
1504 | case GICV3_G1NS: | |
1505 | if (is_eoir0) { | |
1506 | return; | |
1507 | } | |
1508 | if (!arm_is_el3_or_mon(env) && arm_is_secure(env)) { | |
1509 | return; | |
1510 | } | |
1511 | break; | |
1512 | default: | |
96a664d0 JPB |
1513 | qemu_log_mask(LOG_GUEST_ERROR, |
1514 | "%s: IRQ %d isn't active\n", __func__, irq); | |
1515 | return; | |
227a8653 PM |
1516 | } |
1517 | ||
1518 | icc_drop_prio(cs, grp); | |
1519 | ||
1520 | if (!icc_eoi_split(env, cs)) { | |
1521 | /* Priority drop and deactivate not split: deactivate irq now */ | |
1522 | icc_deactivate_irq(cs, irq); | |
1523 | } | |
1524 | } | |
1525 | ||
1526 | static uint64_t icc_hppir0_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
1527 | { | |
1528 | GICv3CPUState *cs = icc_cs_from_env(env); | |
df313f48 PM |
1529 | uint64_t value; |
1530 | ||
1531 | if (icv_access(env, HCR_FMO)) { | |
1532 | return icv_hppir_read(env, ri); | |
1533 | } | |
227a8653 | 1534 | |
df313f48 | 1535 | value = icc_hppir0_value(cs, env); |
227a8653 PM |
1536 | trace_gicv3_icc_hppir0_read(gicv3_redist_affid(cs), value); |
1537 | return value; | |
1538 | } | |
1539 | ||
1540 | static uint64_t icc_hppir1_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
1541 | { | |
1542 | GICv3CPUState *cs = icc_cs_from_env(env); | |
df313f48 PM |
1543 | uint64_t value; |
1544 | ||
1545 | if (icv_access(env, HCR_IMO)) { | |
1546 | return icv_hppir_read(env, ri); | |
1547 | } | |
227a8653 | 1548 | |
df313f48 | 1549 | value = icc_hppir1_value(cs, env); |
227a8653 PM |
1550 | trace_gicv3_icc_hppir1_read(gicv3_redist_affid(cs), value); |
1551 | return value; | |
1552 | } | |
1553 | ||
359fbe65 PM |
1554 | static uint64_t icc_bpr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
1555 | { | |
1556 | GICv3CPUState *cs = icc_cs_from_env(env); | |
1557 | int grp = (ri->crm == 8) ? GICV3_G0 : GICV3_G1; | |
1558 | bool satinc = false; | |
1559 | uint64_t bpr; | |
1560 | ||
77620ba6 PM |
1561 | if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) { |
1562 | return icv_bpr_read(env, ri); | |
1563 | } | |
1564 | ||
359fbe65 PM |
1565 | if (grp == GICV3_G1 && gicv3_use_ns_bank(env)) { |
1566 | grp = GICV3_G1NS; | |
1567 | } | |
1568 | ||
1569 | if (grp == GICV3_G1 && !arm_is_el3_or_mon(env) && | |
1570 | (cs->icc_ctlr_el1[GICV3_S] & ICC_CTLR_EL1_CBPR)) { | |
1571 | /* CBPR_EL1S means secure EL1 or AArch32 EL3 !Mon BPR1 accesses | |
1572 | * modify BPR0 | |
1573 | */ | |
1574 | grp = GICV3_G0; | |
1575 | } | |
1576 | ||
1577 | if (grp == GICV3_G1NS && arm_current_el(env) < 3 && | |
1578 | (cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_CBPR)) { | |
1579 | /* reads return bpr0 + 1 sat to 7, writes ignored */ | |
1580 | grp = GICV3_G0; | |
1581 | satinc = true; | |
1582 | } | |
1583 | ||
1584 | bpr = cs->icc_bpr[grp]; | |
1585 | if (satinc) { | |
1586 | bpr++; | |
1587 | bpr = MIN(bpr, 7); | |
1588 | } | |
1589 | ||
081b1b98 | 1590 | trace_gicv3_icc_bpr_read(ri->crm == 8 ? 0 : 1, gicv3_redist_affid(cs), bpr); |
359fbe65 PM |
1591 | |
1592 | return bpr; | |
1593 | } | |
1594 | ||
1595 | static void icc_bpr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1596 | uint64_t value) | |
1597 | { | |
1598 | GICv3CPUState *cs = icc_cs_from_env(env); | |
1599 | int grp = (ri->crm == 8) ? GICV3_G0 : GICV3_G1; | |
8193d461 | 1600 | uint64_t minval; |
359fbe65 | 1601 | |
77620ba6 PM |
1602 | if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) { |
1603 | icv_bpr_write(env, ri, value); | |
1604 | return; | |
1605 | } | |
1606 | ||
081b1b98 PM |
1607 | trace_gicv3_icc_bpr_write(ri->crm == 8 ? 0 : 1, |
1608 | gicv3_redist_affid(cs), value); | |
359fbe65 PM |
1609 | |
1610 | if (grp == GICV3_G1 && gicv3_use_ns_bank(env)) { | |
1611 | grp = GICV3_G1NS; | |
1612 | } | |
1613 | ||
1614 | if (grp == GICV3_G1 && !arm_is_el3_or_mon(env) && | |
1615 | (cs->icc_ctlr_el1[GICV3_S] & ICC_CTLR_EL1_CBPR)) { | |
1616 | /* CBPR_EL1S means secure EL1 or AArch32 EL3 !Mon BPR1 accesses | |
1617 | * modify BPR0 | |
1618 | */ | |
1619 | grp = GICV3_G0; | |
1620 | } | |
1621 | ||
1622 | if (grp == GICV3_G1NS && arm_current_el(env) < 3 && | |
1623 | (cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_CBPR)) { | |
1624 | /* reads return bpr0 + 1 sat to 7, writes ignored */ | |
1625 | return; | |
1626 | } | |
1627 | ||
84597ff3 | 1628 | minval = (grp == GICV3_G1NS) ? icc_min_bpr_ns(cs) : icc_min_bpr(cs); |
8193d461 PM |
1629 | if (value < minval) { |
1630 | value = minval; | |
1631 | } | |
1632 | ||
359fbe65 PM |
1633 | cs->icc_bpr[grp] = value & 7; |
1634 | gicv3_cpuif_update(cs); | |
1635 | } | |
1636 | ||
1637 | static uint64_t icc_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
1638 | { | |
1639 | GICv3CPUState *cs = icc_cs_from_env(env); | |
1640 | uint64_t value; | |
1641 | ||
1642 | int regno = ri->opc2 & 3; | |
887aae10 | 1643 | int grp = (ri->crm & 1) ? GICV3_G1 : GICV3_G0; |
359fbe65 | 1644 | |
77620ba6 PM |
1645 | if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) { |
1646 | return icv_ap_read(env, ri); | |
1647 | } | |
1648 | ||
359fbe65 PM |
1649 | if (grp == GICV3_G1 && gicv3_use_ns_bank(env)) { |
1650 | grp = GICV3_G1NS; | |
1651 | } | |
1652 | ||
1653 | value = cs->icc_apr[grp][regno]; | |
1654 | ||
081b1b98 | 1655 | trace_gicv3_icc_ap_read(ri->crm & 1, regno, gicv3_redist_affid(cs), value); |
359fbe65 PM |
1656 | return value; |
1657 | } | |
1658 | ||
1659 | static void icc_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1660 | uint64_t value) | |
1661 | { | |
1662 | GICv3CPUState *cs = icc_cs_from_env(env); | |
1663 | ||
1664 | int regno = ri->opc2 & 3; | |
887aae10 | 1665 | int grp = (ri->crm & 1) ? GICV3_G1 : GICV3_G0; |
359fbe65 | 1666 | |
77620ba6 PM |
1667 | if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) { |
1668 | icv_ap_write(env, ri, value); | |
1669 | return; | |
1670 | } | |
1671 | ||
081b1b98 | 1672 | trace_gicv3_icc_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value); |
359fbe65 PM |
1673 | |
1674 | if (grp == GICV3_G1 && gicv3_use_ns_bank(env)) { | |
1675 | grp = GICV3_G1NS; | |
1676 | } | |
1677 | ||
1678 | /* It's not possible to claim that a Non-secure interrupt is active | |
1679 | * at a priority outside the Non-secure range (128..255), since this | |
1680 | * would otherwise allow malicious NS code to block delivery of S interrupts | |
1681 | * by writing a bad value to these registers. | |
1682 | */ | |
1683 | if (grp == GICV3_G1NS && regno < 2 && arm_feature(env, ARM_FEATURE_EL3)) { | |
1684 | return; | |
1685 | } | |
1686 | ||
1687 | cs->icc_apr[grp][regno] = value & 0xFFFFFFFFU; | |
1688 | gicv3_cpuif_update(cs); | |
1689 | } | |
1690 | ||
227a8653 PM |
1691 | static void icc_dir_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1692 | uint64_t value) | |
1693 | { | |
1694 | /* Deactivate interrupt */ | |
1695 | GICv3CPUState *cs = icc_cs_from_env(env); | |
1696 | int irq = value & 0xffffff; | |
1697 | bool irq_is_secure, single_sec_state, irq_is_grp0; | |
1698 | bool route_fiq_to_el3, route_irq_to_el3, route_fiq_to_el2, route_irq_to_el2; | |
1699 | ||
df313f48 PM |
1700 | if (icv_access(env, HCR_FMO | HCR_IMO)) { |
1701 | icv_dir_write(env, ri, value); | |
1702 | return; | |
1703 | } | |
1704 | ||
227a8653 PM |
1705 | trace_gicv3_icc_dir_write(gicv3_redist_affid(cs), value); |
1706 | ||
1707 | if (irq >= cs->gic->num_irq) { | |
1708 | /* Also catches special interrupt numbers and LPIs */ | |
1709 | return; | |
1710 | } | |
1711 | ||
1712 | if (!icc_eoi_split(env, cs)) { | |
1713 | return; | |
1714 | } | |
1715 | ||
1716 | int grp = gicv3_irq_group(cs->gic, cs, irq); | |
1717 | ||
1718 | single_sec_state = cs->gic->gicd_ctlr & GICD_CTLR_DS; | |
1719 | irq_is_secure = !single_sec_state && (grp != GICV3_G1NS); | |
1720 | irq_is_grp0 = grp == GICV3_G0; | |
1721 | ||
1722 | /* Check whether we're allowed to deactivate this interrupt based | |
1723 | * on its group and the current CPU state. | |
1724 | * These checks are laid out to correspond to the spec's pseudocode. | |
1725 | */ | |
1726 | route_fiq_to_el3 = env->cp15.scr_el3 & SCR_FIQ; | |
1727 | route_irq_to_el3 = env->cp15.scr_el3 & SCR_IRQ; | |
1728 | /* No need to include !IsSecure in route_*_to_el2 as it's only | |
1729 | * tested in cases where we know !IsSecure is true. | |
1730 | */ | |
f7778444 RH |
1731 | uint64_t hcr_el2 = arm_hcr_el2_eff(env); |
1732 | route_fiq_to_el2 = hcr_el2 & HCR_FMO; | |
1733 | route_irq_to_el2 = hcr_el2 & HCR_IMO; | |
227a8653 PM |
1734 | |
1735 | switch (arm_current_el(env)) { | |
1736 | case 3: | |
1737 | break; | |
1738 | case 2: | |
1739 | if (single_sec_state && irq_is_grp0 && !route_fiq_to_el3) { | |
1740 | break; | |
1741 | } | |
1742 | if (!irq_is_secure && !irq_is_grp0 && !route_irq_to_el3) { | |
1743 | break; | |
1744 | } | |
1745 | return; | |
1746 | case 1: | |
1747 | if (!arm_is_secure_below_el3(env)) { | |
1748 | if (single_sec_state && irq_is_grp0 && | |
1749 | !route_fiq_to_el3 && !route_fiq_to_el2) { | |
1750 | break; | |
1751 | } | |
1752 | if (!irq_is_secure && !irq_is_grp0 && | |
1753 | !route_irq_to_el3 && !route_irq_to_el2) { | |
1754 | break; | |
1755 | } | |
1756 | } else { | |
1757 | if (irq_is_grp0 && !route_fiq_to_el3) { | |
1758 | break; | |
1759 | } | |
1760 | if (!irq_is_grp0 && | |
1761 | (!irq_is_secure || !single_sec_state) && | |
1762 | !route_irq_to_el3) { | |
1763 | break; | |
1764 | } | |
1765 | } | |
1766 | return; | |
1767 | default: | |
1768 | g_assert_not_reached(); | |
1769 | } | |
1770 | ||
1771 | icc_deactivate_irq(cs, irq); | |
1772 | } | |
1773 | ||
1774 | static uint64_t icc_rpr_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
1775 | { | |
1776 | GICv3CPUState *cs = icc_cs_from_env(env); | |
df313f48 PM |
1777 | int prio; |
1778 | ||
1779 | if (icv_access(env, HCR_FMO | HCR_IMO)) { | |
1780 | return icv_rpr_read(env, ri); | |
1781 | } | |
1782 | ||
1783 | prio = icc_highest_active_prio(cs); | |
227a8653 PM |
1784 | |
1785 | if (arm_feature(env, ARM_FEATURE_EL3) && | |
1786 | !arm_is_secure(env) && (env->cp15.scr_el3 & SCR_FIQ)) { | |
1787 | /* NS GIC access and Group 0 is inaccessible to NS */ | |
a2e2d7fc | 1788 | if ((prio & 0x80) == 0) { |
227a8653 PM |
1789 | /* NS mustn't see priorities in the Secure half of the range */ |
1790 | prio = 0; | |
1791 | } else if (prio != 0xff) { | |
1792 | /* Non-idle priority: show the Non-secure view of it */ | |
1793 | prio = (prio << 1) & 0xff; | |
1794 | } | |
1795 | } | |
1796 | ||
1797 | trace_gicv3_icc_rpr_read(gicv3_redist_affid(cs), prio); | |
1798 | return prio; | |
1799 | } | |
1800 | ||
b1a0eb77 PM |
1801 | static void icc_generate_sgi(CPUARMState *env, GICv3CPUState *cs, |
1802 | uint64_t value, int grp, bool ns) | |
1803 | { | |
1804 | GICv3State *s = cs->gic; | |
1805 | ||
1806 | /* Extract Aff3/Aff2/Aff1 and shift into the bottom 24 bits */ | |
1807 | uint64_t aff = extract64(value, 48, 8) << 16 | | |
1808 | extract64(value, 32, 8) << 8 | | |
1809 | extract64(value, 16, 8); | |
1810 | uint32_t targetlist = extract64(value, 0, 16); | |
1811 | uint32_t irq = extract64(value, 24, 4); | |
1812 | bool irm = extract64(value, 40, 1); | |
1813 | int i; | |
1814 | ||
1815 | if (grp == GICV3_G1 && s->gicd_ctlr & GICD_CTLR_DS) { | |
1816 | /* If GICD_CTLR.DS == 1, the Distributor treats Secure Group 1 | |
1817 | * interrupts as Group 0 interrupts and must send Secure Group 0 | |
1818 | * interrupts to the target CPUs. | |
1819 | */ | |
1820 | grp = GICV3_G0; | |
1821 | } | |
1822 | ||
1823 | trace_gicv3_icc_generate_sgi(gicv3_redist_affid(cs), irq, irm, | |
1824 | aff, targetlist); | |
1825 | ||
1826 | for (i = 0; i < s->num_cpu; i++) { | |
1827 | GICv3CPUState *ocs = &s->cpu[i]; | |
1828 | ||
1829 | if (irm) { | |
1830 | /* IRM == 1 : route to all CPUs except self */ | |
1831 | if (cs == ocs) { | |
1832 | continue; | |
1833 | } | |
1834 | } else { | |
1835 | /* IRM == 0 : route to Aff3.Aff2.Aff1.n for all n in [0..15] | |
1836 | * where the corresponding bit is set in targetlist | |
1837 | */ | |
1838 | int aff0; | |
1839 | ||
1840 | if (ocs->gicr_typer >> 40 != aff) { | |
1841 | continue; | |
1842 | } | |
1843 | aff0 = extract64(ocs->gicr_typer, 32, 8); | |
1844 | if (aff0 > 15 || extract32(targetlist, aff0, 1) == 0) { | |
1845 | continue; | |
1846 | } | |
1847 | } | |
1848 | ||
1849 | /* The redistributor will check against its own GICR_NSACR as needed */ | |
1850 | gicv3_redist_send_sgi(ocs, grp, irq, ns); | |
1851 | } | |
1852 | } | |
1853 | ||
1854 | static void icc_sgi0r_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1855 | uint64_t value) | |
1856 | { | |
1857 | /* Generate Secure Group 0 SGI. */ | |
1858 | GICv3CPUState *cs = icc_cs_from_env(env); | |
1859 | bool ns = !arm_is_secure(env); | |
1860 | ||
1861 | icc_generate_sgi(env, cs, value, GICV3_G0, ns); | |
1862 | } | |
1863 | ||
1864 | static void icc_sgi1r_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1865 | uint64_t value) | |
1866 | { | |
1867 | /* Generate Group 1 SGI for the current Security state */ | |
1868 | GICv3CPUState *cs = icc_cs_from_env(env); | |
1869 | int grp; | |
1870 | bool ns = !arm_is_secure(env); | |
1871 | ||
1872 | grp = ns ? GICV3_G1NS : GICV3_G1; | |
1873 | icc_generate_sgi(env, cs, value, grp, ns); | |
1874 | } | |
1875 | ||
1876 | static void icc_asgi1r_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1877 | uint64_t value) | |
1878 | { | |
1879 | /* Generate Group 1 SGI for the Security state that is not | |
1880 | * the current state | |
1881 | */ | |
1882 | GICv3CPUState *cs = icc_cs_from_env(env); | |
1883 | int grp; | |
1884 | bool ns = !arm_is_secure(env); | |
1885 | ||
1886 | grp = ns ? GICV3_G1 : GICV3_G1NS; | |
1887 | icc_generate_sgi(env, cs, value, grp, ns); | |
1888 | } | |
1889 | ||
359fbe65 PM |
1890 | static uint64_t icc_igrpen_read(CPUARMState *env, const ARMCPRegInfo *ri) |
1891 | { | |
1892 | GICv3CPUState *cs = icc_cs_from_env(env); | |
1893 | int grp = ri->opc2 & 1 ? GICV3_G1 : GICV3_G0; | |
1894 | uint64_t value; | |
1895 | ||
77620ba6 PM |
1896 | if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) { |
1897 | return icv_igrpen_read(env, ri); | |
1898 | } | |
1899 | ||
359fbe65 PM |
1900 | if (grp == GICV3_G1 && gicv3_use_ns_bank(env)) { |
1901 | grp = GICV3_G1NS; | |
1902 | } | |
1903 | ||
1904 | value = cs->icc_igrpen[grp]; | |
081b1b98 PM |
1905 | trace_gicv3_icc_igrpen_read(ri->opc2 & 1 ? 1 : 0, |
1906 | gicv3_redist_affid(cs), value); | |
359fbe65 PM |
1907 | return value; |
1908 | } | |
1909 | ||
1910 | static void icc_igrpen_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1911 | uint64_t value) | |
1912 | { | |
1913 | GICv3CPUState *cs = icc_cs_from_env(env); | |
1914 | int grp = ri->opc2 & 1 ? GICV3_G1 : GICV3_G0; | |
1915 | ||
77620ba6 PM |
1916 | if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) { |
1917 | icv_igrpen_write(env, ri, value); | |
1918 | return; | |
1919 | } | |
1920 | ||
081b1b98 PM |
1921 | trace_gicv3_icc_igrpen_write(ri->opc2 & 1 ? 1 : 0, |
1922 | gicv3_redist_affid(cs), value); | |
359fbe65 PM |
1923 | |
1924 | if (grp == GICV3_G1 && gicv3_use_ns_bank(env)) { | |
1925 | grp = GICV3_G1NS; | |
1926 | } | |
1927 | ||
1928 | cs->icc_igrpen[grp] = value & ICC_IGRPEN_ENABLE; | |
1929 | gicv3_cpuif_update(cs); | |
1930 | } | |
1931 | ||
1932 | static uint64_t icc_igrpen1_el3_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
1933 | { | |
1934 | GICv3CPUState *cs = icc_cs_from_env(env); | |
081b1b98 | 1935 | uint64_t value; |
359fbe65 PM |
1936 | |
1937 | /* IGRPEN1_EL3 bits 0 and 1 are r/w aliases into IGRPEN1_EL1 NS and S */ | |
081b1b98 PM |
1938 | value = cs->icc_igrpen[GICV3_G1NS] | (cs->icc_igrpen[GICV3_G1] << 1); |
1939 | trace_gicv3_icc_igrpen1_el3_read(gicv3_redist_affid(cs), value); | |
1940 | return value; | |
359fbe65 PM |
1941 | } |
1942 | ||
1943 | static void icc_igrpen1_el3_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1944 | uint64_t value) | |
1945 | { | |
1946 | GICv3CPUState *cs = icc_cs_from_env(env); | |
1947 | ||
1948 | trace_gicv3_icc_igrpen1_el3_write(gicv3_redist_affid(cs), value); | |
1949 | ||
1950 | /* IGRPEN1_EL3 bits 0 and 1 are r/w aliases into IGRPEN1_EL1 NS and S */ | |
1951 | cs->icc_igrpen[GICV3_G1NS] = extract32(value, 0, 1); | |
1952 | cs->icc_igrpen[GICV3_G1] = extract32(value, 1, 1); | |
1953 | gicv3_cpuif_update(cs); | |
1954 | } | |
1955 | ||
1956 | static uint64_t icc_ctlr_el1_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
1957 | { | |
1958 | GICv3CPUState *cs = icc_cs_from_env(env); | |
1959 | int bank = gicv3_use_ns_bank(env) ? GICV3_NS : GICV3_S; | |
1960 | uint64_t value; | |
1961 | ||
77620ba6 PM |
1962 | if (icv_access(env, HCR_FMO | HCR_IMO)) { |
1963 | return icv_ctlr_read(env, ri); | |
1964 | } | |
1965 | ||
359fbe65 PM |
1966 | value = cs->icc_ctlr_el1[bank]; |
1967 | trace_gicv3_icc_ctlr_read(gicv3_redist_affid(cs), value); | |
1968 | return value; | |
1969 | } | |
1970 | ||
1971 | static void icc_ctlr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1972 | uint64_t value) | |
1973 | { | |
1974 | GICv3CPUState *cs = icc_cs_from_env(env); | |
1975 | int bank = gicv3_use_ns_bank(env) ? GICV3_NS : GICV3_S; | |
1976 | uint64_t mask; | |
1977 | ||
77620ba6 PM |
1978 | if (icv_access(env, HCR_FMO | HCR_IMO)) { |
1979 | icv_ctlr_write(env, ri, value); | |
1980 | return; | |
1981 | } | |
1982 | ||
359fbe65 PM |
1983 | trace_gicv3_icc_ctlr_write(gicv3_redist_affid(cs), value); |
1984 | ||
1985 | /* Only CBPR and EOIMODE can be RW; | |
1986 | * for us PMHE is RAZ/WI (we don't implement 1-of-N interrupts or | |
1987 | * the asseciated priority-based routing of them); | |
1988 | * if EL3 is implemented and GICD_CTLR.DS == 0, then PMHE and CBPR are RO. | |
1989 | */ | |
1990 | if (arm_feature(env, ARM_FEATURE_EL3) && | |
1991 | ((cs->gic->gicd_ctlr & GICD_CTLR_DS) == 0)) { | |
1992 | mask = ICC_CTLR_EL1_EOIMODE; | |
1993 | } else { | |
1994 | mask = ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE; | |
1995 | } | |
1996 | ||
1997 | cs->icc_ctlr_el1[bank] &= ~mask; | |
1998 | cs->icc_ctlr_el1[bank] |= (value & mask); | |
1999 | gicv3_cpuif_update(cs); | |
2000 | } | |
2001 | ||
2002 | ||
2003 | static uint64_t icc_ctlr_el3_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2004 | { | |
2005 | GICv3CPUState *cs = icc_cs_from_env(env); | |
2006 | uint64_t value; | |
2007 | ||
2008 | value = cs->icc_ctlr_el3; | |
2009 | if (cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_EOIMODE) { | |
2010 | value |= ICC_CTLR_EL3_EOIMODE_EL1NS; | |
2011 | } | |
2012 | if (cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_CBPR) { | |
2013 | value |= ICC_CTLR_EL3_CBPR_EL1NS; | |
2014 | } | |
2015 | if (cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_EOIMODE) { | |
2016 | value |= ICC_CTLR_EL3_EOIMODE_EL1S; | |
2017 | } | |
2018 | if (cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_CBPR) { | |
2019 | value |= ICC_CTLR_EL3_CBPR_EL1S; | |
2020 | } | |
2021 | ||
2022 | trace_gicv3_icc_ctlr_el3_read(gicv3_redist_affid(cs), value); | |
2023 | return value; | |
2024 | } | |
2025 | ||
2026 | static void icc_ctlr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2027 | uint64_t value) | |
2028 | { | |
2029 | GICv3CPUState *cs = icc_cs_from_env(env); | |
2030 | uint64_t mask; | |
2031 | ||
2032 | trace_gicv3_icc_ctlr_el3_write(gicv3_redist_affid(cs), value); | |
2033 | ||
2034 | /* *_EL1NS and *_EL1S bits are aliases into the ICC_CTLR_EL1 bits. */ | |
09380dd1 | 2035 | cs->icc_ctlr_el1[GICV3_NS] &= ~(ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE); |
359fbe65 PM |
2036 | if (value & ICC_CTLR_EL3_EOIMODE_EL1NS) { |
2037 | cs->icc_ctlr_el1[GICV3_NS] |= ICC_CTLR_EL1_EOIMODE; | |
2038 | } | |
2039 | if (value & ICC_CTLR_EL3_CBPR_EL1NS) { | |
2040 | cs->icc_ctlr_el1[GICV3_NS] |= ICC_CTLR_EL1_CBPR; | |
2041 | } | |
2042 | ||
09380dd1 | 2043 | cs->icc_ctlr_el1[GICV3_S] &= ~(ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE); |
359fbe65 PM |
2044 | if (value & ICC_CTLR_EL3_EOIMODE_EL1S) { |
2045 | cs->icc_ctlr_el1[GICV3_S] |= ICC_CTLR_EL1_EOIMODE; | |
2046 | } | |
2047 | if (value & ICC_CTLR_EL3_CBPR_EL1S) { | |
2048 | cs->icc_ctlr_el1[GICV3_S] |= ICC_CTLR_EL1_CBPR; | |
2049 | } | |
2050 | ||
9323e79f | 2051 | /* The only bit stored in icc_ctlr_el3 which is writable is EOIMODE_EL3: */ |
359fbe65 PM |
2052 | mask = ICC_CTLR_EL3_EOIMODE_EL3; |
2053 | ||
2054 | cs->icc_ctlr_el3 &= ~mask; | |
2055 | cs->icc_ctlr_el3 |= (value & mask); | |
2056 | gicv3_cpuif_update(cs); | |
2057 | } | |
2058 | ||
2059 | static CPAccessResult gicv3_irqfiq_access(CPUARMState *env, | |
2060 | const ARMCPRegInfo *ri, bool isread) | |
2061 | { | |
2062 | CPAccessResult r = CP_ACCESS_OK; | |
86830554 PM |
2063 | GICv3CPUState *cs = icc_cs_from_env(env); |
2064 | int el = arm_current_el(env); | |
2065 | ||
2066 | if ((cs->ich_hcr_el2 & ICH_HCR_EL2_TC) && | |
2067 | el == 1 && !arm_is_secure_below_el3(env)) { | |
2068 | /* Takes priority over a possible EL3 trap */ | |
2069 | return CP_ACCESS_TRAP_EL2; | |
2070 | } | |
359fbe65 PM |
2071 | |
2072 | if ((env->cp15.scr_el3 & (SCR_FIQ | SCR_IRQ)) == (SCR_FIQ | SCR_IRQ)) { | |
86830554 | 2073 | switch (el) { |
359fbe65 | 2074 | case 1: |
f7778444 RH |
2075 | /* Note that arm_hcr_el2_eff takes secure state into account. */ |
2076 | if ((arm_hcr_el2_eff(env) & (HCR_IMO | HCR_FMO)) == 0) { | |
359fbe65 PM |
2077 | r = CP_ACCESS_TRAP_EL3; |
2078 | } | |
2079 | break; | |
2080 | case 2: | |
2081 | r = CP_ACCESS_TRAP_EL3; | |
2082 | break; | |
2083 | case 3: | |
2084 | if (!is_a64(env) && !arm_is_el3_or_mon(env)) { | |
2085 | r = CP_ACCESS_TRAP_EL3; | |
2086 | } | |
92b30c2f | 2087 | break; |
359fbe65 PM |
2088 | default: |
2089 | g_assert_not_reached(); | |
2090 | } | |
2091 | } | |
2092 | ||
2093 | if (r == CP_ACCESS_TRAP_EL3 && !arm_el_is_aa64(env, 3)) { | |
2094 | r = CP_ACCESS_TRAP; | |
2095 | } | |
2096 | return r; | |
2097 | } | |
2098 | ||
86830554 PM |
2099 | static CPAccessResult gicv3_dir_access(CPUARMState *env, |
2100 | const ARMCPRegInfo *ri, bool isread) | |
2101 | { | |
2102 | GICv3CPUState *cs = icc_cs_from_env(env); | |
2103 | ||
2104 | if ((cs->ich_hcr_el2 & ICH_HCR_EL2_TDIR) && | |
2105 | arm_current_el(env) == 1 && !arm_is_secure_below_el3(env)) { | |
2106 | /* Takes priority over a possible EL3 trap */ | |
2107 | return CP_ACCESS_TRAP_EL2; | |
2108 | } | |
2109 | ||
2110 | return gicv3_irqfiq_access(env, ri, isread); | |
2111 | } | |
2112 | ||
2113 | static CPAccessResult gicv3_sgi_access(CPUARMState *env, | |
2114 | const ARMCPRegInfo *ri, bool isread) | |
2115 | { | |
f7778444 RH |
2116 | if (arm_current_el(env) == 1 && |
2117 | (arm_hcr_el2_eff(env) & (HCR_IMO | HCR_FMO)) != 0) { | |
86830554 PM |
2118 | /* Takes priority over a possible EL3 trap */ |
2119 | return CP_ACCESS_TRAP_EL2; | |
2120 | } | |
2121 | ||
2122 | return gicv3_irqfiq_access(env, ri, isread); | |
2123 | } | |
2124 | ||
359fbe65 PM |
2125 | static CPAccessResult gicv3_fiq_access(CPUARMState *env, |
2126 | const ARMCPRegInfo *ri, bool isread) | |
2127 | { | |
2128 | CPAccessResult r = CP_ACCESS_OK; | |
86830554 PM |
2129 | GICv3CPUState *cs = icc_cs_from_env(env); |
2130 | int el = arm_current_el(env); | |
2131 | ||
2132 | if ((cs->ich_hcr_el2 & ICH_HCR_EL2_TALL0) && | |
2133 | el == 1 && !arm_is_secure_below_el3(env)) { | |
2134 | /* Takes priority over a possible EL3 trap */ | |
2135 | return CP_ACCESS_TRAP_EL2; | |
2136 | } | |
359fbe65 PM |
2137 | |
2138 | if (env->cp15.scr_el3 & SCR_FIQ) { | |
86830554 | 2139 | switch (el) { |
359fbe65 | 2140 | case 1: |
f7778444 | 2141 | if ((arm_hcr_el2_eff(env) & HCR_FMO) == 0) { |
359fbe65 PM |
2142 | r = CP_ACCESS_TRAP_EL3; |
2143 | } | |
2144 | break; | |
2145 | case 2: | |
2146 | r = CP_ACCESS_TRAP_EL3; | |
2147 | break; | |
2148 | case 3: | |
2149 | if (!is_a64(env) && !arm_is_el3_or_mon(env)) { | |
2150 | r = CP_ACCESS_TRAP_EL3; | |
2151 | } | |
92b30c2f | 2152 | break; |
359fbe65 PM |
2153 | default: |
2154 | g_assert_not_reached(); | |
2155 | } | |
2156 | } | |
2157 | ||
2158 | if (r == CP_ACCESS_TRAP_EL3 && !arm_el_is_aa64(env, 3)) { | |
2159 | r = CP_ACCESS_TRAP; | |
2160 | } | |
2161 | return r; | |
2162 | } | |
2163 | ||
2164 | static CPAccessResult gicv3_irq_access(CPUARMState *env, | |
2165 | const ARMCPRegInfo *ri, bool isread) | |
2166 | { | |
2167 | CPAccessResult r = CP_ACCESS_OK; | |
86830554 PM |
2168 | GICv3CPUState *cs = icc_cs_from_env(env); |
2169 | int el = arm_current_el(env); | |
2170 | ||
2171 | if ((cs->ich_hcr_el2 & ICH_HCR_EL2_TALL1) && | |
2172 | el == 1 && !arm_is_secure_below_el3(env)) { | |
2173 | /* Takes priority over a possible EL3 trap */ | |
2174 | return CP_ACCESS_TRAP_EL2; | |
2175 | } | |
359fbe65 PM |
2176 | |
2177 | if (env->cp15.scr_el3 & SCR_IRQ) { | |
86830554 | 2178 | switch (el) { |
359fbe65 | 2179 | case 1: |
f7778444 | 2180 | if ((arm_hcr_el2_eff(env) & HCR_IMO) == 0) { |
359fbe65 PM |
2181 | r = CP_ACCESS_TRAP_EL3; |
2182 | } | |
2183 | break; | |
2184 | case 2: | |
2185 | r = CP_ACCESS_TRAP_EL3; | |
2186 | break; | |
2187 | case 3: | |
2188 | if (!is_a64(env) && !arm_is_el3_or_mon(env)) { | |
2189 | r = CP_ACCESS_TRAP_EL3; | |
2190 | } | |
2191 | break; | |
2192 | default: | |
2193 | g_assert_not_reached(); | |
2194 | } | |
2195 | } | |
2196 | ||
2197 | if (r == CP_ACCESS_TRAP_EL3 && !arm_el_is_aa64(env, 3)) { | |
2198 | r = CP_ACCESS_TRAP; | |
2199 | } | |
2200 | return r; | |
2201 | } | |
2202 | ||
2203 | static void icc_reset(CPUARMState *env, const ARMCPRegInfo *ri) | |
2204 | { | |
2205 | GICv3CPUState *cs = icc_cs_from_env(env); | |
2206 | ||
2207 | cs->icc_ctlr_el1[GICV3_S] = ICC_CTLR_EL1_A3V | | |
2208 | (1 << ICC_CTLR_EL1_IDBITS_SHIFT) | | |
84597ff3 | 2209 | ((cs->pribits - 1) << ICC_CTLR_EL1_PRIBITS_SHIFT); |
359fbe65 PM |
2210 | cs->icc_ctlr_el1[GICV3_NS] = ICC_CTLR_EL1_A3V | |
2211 | (1 << ICC_CTLR_EL1_IDBITS_SHIFT) | | |
84597ff3 | 2212 | ((cs->pribits - 1) << ICC_CTLR_EL1_PRIBITS_SHIFT); |
359fbe65 | 2213 | cs->icc_pmr_el1 = 0; |
84597ff3 PM |
2214 | cs->icc_bpr[GICV3_G0] = icc_min_bpr(cs); |
2215 | cs->icc_bpr[GICV3_G1] = icc_min_bpr(cs); | |
2216 | cs->icc_bpr[GICV3_G1NS] = icc_min_bpr_ns(cs); | |
359fbe65 PM |
2217 | memset(cs->icc_apr, 0, sizeof(cs->icc_apr)); |
2218 | memset(cs->icc_igrpen, 0, sizeof(cs->icc_igrpen)); | |
2219 | cs->icc_ctlr_el3 = ICC_CTLR_EL3_NDS | ICC_CTLR_EL3_A3V | | |
2220 | (1 << ICC_CTLR_EL3_IDBITS_SHIFT) | | |
84597ff3 | 2221 | ((cs->pribits - 1) << ICC_CTLR_EL3_PRIBITS_SHIFT); |
4eb833b5 PM |
2222 | |
2223 | memset(cs->ich_apr, 0, sizeof(cs->ich_apr)); | |
2224 | cs->ich_hcr_el2 = 0; | |
2225 | memset(cs->ich_lr_el2, 0, sizeof(cs->ich_lr_el2)); | |
2226 | cs->ich_vmcr_el2 = ICH_VMCR_EL2_VFIQEN | | |
f5dc1b77 | 2227 | ((icv_min_vbpr(cs) + 1) << ICH_VMCR_EL2_VBPR1_SHIFT) | |
4eb833b5 | 2228 | (icv_min_vbpr(cs) << ICH_VMCR_EL2_VBPR0_SHIFT); |
359fbe65 PM |
2229 | } |
2230 | ||
2231 | static const ARMCPRegInfo gicv3_cpuif_reginfo[] = { | |
2232 | { .name = "ICC_PMR_EL1", .state = ARM_CP_STATE_BOTH, | |
2233 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 6, .opc2 = 0, | |
2234 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2235 | .access = PL1_RW, .accessfn = gicv3_irqfiq_access, | |
2236 | .readfn = icc_pmr_read, | |
2237 | .writefn = icc_pmr_write, | |
2238 | /* We hang the whole cpu interface reset routine off here | |
2239 | * rather than parcelling it out into one little function | |
2240 | * per register | |
2241 | */ | |
2242 | .resetfn = icc_reset, | |
2243 | }, | |
227a8653 PM |
2244 | { .name = "ICC_IAR0_EL1", .state = ARM_CP_STATE_BOTH, |
2245 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 0, | |
2246 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2247 | .access = PL1_R, .accessfn = gicv3_fiq_access, | |
2248 | .readfn = icc_iar0_read, | |
2249 | }, | |
2250 | { .name = "ICC_EOIR0_EL1", .state = ARM_CP_STATE_BOTH, | |
2251 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 1, | |
2252 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2253 | .access = PL1_W, .accessfn = gicv3_fiq_access, | |
2254 | .writefn = icc_eoir_write, | |
2255 | }, | |
2256 | { .name = "ICC_HPPIR0_EL1", .state = ARM_CP_STATE_BOTH, | |
2257 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 2, | |
2258 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2259 | .access = PL1_R, .accessfn = gicv3_fiq_access, | |
2260 | .readfn = icc_hppir0_read, | |
2261 | }, | |
359fbe65 PM |
2262 | { .name = "ICC_BPR0_EL1", .state = ARM_CP_STATE_BOTH, |
2263 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 3, | |
2264 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2265 | .access = PL1_RW, .accessfn = gicv3_fiq_access, | |
e971fa04 | 2266 | .readfn = icc_bpr_read, |
359fbe65 PM |
2267 | .writefn = icc_bpr_write, |
2268 | }, | |
2269 | { .name = "ICC_AP0R0_EL1", .state = ARM_CP_STATE_BOTH, | |
2270 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 4, | |
2271 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2272 | .access = PL1_RW, .accessfn = gicv3_fiq_access, | |
e971fa04 | 2273 | .readfn = icc_ap_read, |
359fbe65 PM |
2274 | .writefn = icc_ap_write, |
2275 | }, | |
359fbe65 PM |
2276 | /* All the ICC_AP1R*_EL1 registers are banked */ |
2277 | { .name = "ICC_AP1R0_EL1", .state = ARM_CP_STATE_BOTH, | |
2278 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 9, .opc2 = 0, | |
2279 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2280 | .access = PL1_RW, .accessfn = gicv3_irq_access, | |
2281 | .readfn = icc_ap_read, | |
2282 | .writefn = icc_ap_write, | |
2283 | }, | |
227a8653 PM |
2284 | { .name = "ICC_DIR_EL1", .state = ARM_CP_STATE_BOTH, |
2285 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 11, .opc2 = 1, | |
2286 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
86830554 | 2287 | .access = PL1_W, .accessfn = gicv3_dir_access, |
227a8653 PM |
2288 | .writefn = icc_dir_write, |
2289 | }, | |
2290 | { .name = "ICC_RPR_EL1", .state = ARM_CP_STATE_BOTH, | |
2291 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 11, .opc2 = 3, | |
2292 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2293 | .access = PL1_R, .accessfn = gicv3_irqfiq_access, | |
2294 | .readfn = icc_rpr_read, | |
2295 | }, | |
b1a0eb77 PM |
2296 | { .name = "ICC_SGI1R_EL1", .state = ARM_CP_STATE_AA64, |
2297 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 11, .opc2 = 5, | |
2298 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
86830554 | 2299 | .access = PL1_W, .accessfn = gicv3_sgi_access, |
b1a0eb77 PM |
2300 | .writefn = icc_sgi1r_write, |
2301 | }, | |
2302 | { .name = "ICC_SGI1R", | |
2303 | .cp = 15, .opc1 = 0, .crm = 12, | |
2304 | .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_RAW, | |
86830554 | 2305 | .access = PL1_W, .accessfn = gicv3_sgi_access, |
b1a0eb77 PM |
2306 | .writefn = icc_sgi1r_write, |
2307 | }, | |
2308 | { .name = "ICC_ASGI1R_EL1", .state = ARM_CP_STATE_AA64, | |
2309 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 11, .opc2 = 6, | |
2310 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
86830554 | 2311 | .access = PL1_W, .accessfn = gicv3_sgi_access, |
b1a0eb77 PM |
2312 | .writefn = icc_asgi1r_write, |
2313 | }, | |
2314 | { .name = "ICC_ASGI1R", | |
2315 | .cp = 15, .opc1 = 1, .crm = 12, | |
2316 | .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_RAW, | |
86830554 | 2317 | .access = PL1_W, .accessfn = gicv3_sgi_access, |
b1a0eb77 PM |
2318 | .writefn = icc_asgi1r_write, |
2319 | }, | |
2320 | { .name = "ICC_SGI0R_EL1", .state = ARM_CP_STATE_AA64, | |
2321 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 11, .opc2 = 7, | |
2322 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
86830554 | 2323 | .access = PL1_W, .accessfn = gicv3_sgi_access, |
b1a0eb77 PM |
2324 | .writefn = icc_sgi0r_write, |
2325 | }, | |
2326 | { .name = "ICC_SGI0R", | |
2327 | .cp = 15, .opc1 = 2, .crm = 12, | |
2328 | .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_RAW, | |
86830554 | 2329 | .access = PL1_W, .accessfn = gicv3_sgi_access, |
b1a0eb77 PM |
2330 | .writefn = icc_sgi0r_write, |
2331 | }, | |
227a8653 PM |
2332 | { .name = "ICC_IAR1_EL1", .state = ARM_CP_STATE_BOTH, |
2333 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 0, | |
2334 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2335 | .access = PL1_R, .accessfn = gicv3_irq_access, | |
2336 | .readfn = icc_iar1_read, | |
2337 | }, | |
2338 | { .name = "ICC_EOIR1_EL1", .state = ARM_CP_STATE_BOTH, | |
2339 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 1, | |
2340 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2341 | .access = PL1_W, .accessfn = gicv3_irq_access, | |
2342 | .writefn = icc_eoir_write, | |
2343 | }, | |
2344 | { .name = "ICC_HPPIR1_EL1", .state = ARM_CP_STATE_BOTH, | |
2345 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 2, | |
2346 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2347 | .access = PL1_R, .accessfn = gicv3_irq_access, | |
2348 | .readfn = icc_hppir1_read, | |
2349 | }, | |
359fbe65 PM |
2350 | /* This register is banked */ |
2351 | { .name = "ICC_BPR1_EL1", .state = ARM_CP_STATE_BOTH, | |
2352 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 3, | |
2353 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2354 | .access = PL1_RW, .accessfn = gicv3_irq_access, | |
2355 | .readfn = icc_bpr_read, | |
2356 | .writefn = icc_bpr_write, | |
2357 | }, | |
2358 | /* This register is banked */ | |
2359 | { .name = "ICC_CTLR_EL1", .state = ARM_CP_STATE_BOTH, | |
2360 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 4, | |
2361 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2362 | .access = PL1_RW, .accessfn = gicv3_irqfiq_access, | |
2363 | .readfn = icc_ctlr_el1_read, | |
2364 | .writefn = icc_ctlr_el1_write, | |
2365 | }, | |
2366 | { .name = "ICC_SRE_EL1", .state = ARM_CP_STATE_BOTH, | |
2367 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 5, | |
2368 | .type = ARM_CP_NO_RAW | ARM_CP_CONST, | |
2369 | .access = PL1_RW, | |
2370 | /* We don't support IRQ/FIQ bypass and system registers are | |
2371 | * always enabled, so all our bits are RAZ/WI or RAO/WI. | |
2372 | * This register is banked but since it's constant we don't | |
2373 | * need to do anything special. | |
2374 | */ | |
2375 | .resetvalue = 0x7, | |
2376 | }, | |
2377 | { .name = "ICC_IGRPEN0_EL1", .state = ARM_CP_STATE_BOTH, | |
2378 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 6, | |
2379 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2380 | .access = PL1_RW, .accessfn = gicv3_fiq_access, | |
bd8db7d9 | 2381 | .fgt = FGT_ICC_IGRPENN_EL1, |
e971fa04 | 2382 | .readfn = icc_igrpen_read, |
359fbe65 PM |
2383 | .writefn = icc_igrpen_write, |
2384 | }, | |
2385 | /* This register is banked */ | |
2386 | { .name = "ICC_IGRPEN1_EL1", .state = ARM_CP_STATE_BOTH, | |
2387 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 7, | |
2388 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2389 | .access = PL1_RW, .accessfn = gicv3_irq_access, | |
bd8db7d9 | 2390 | .fgt = FGT_ICC_IGRPENN_EL1, |
359fbe65 PM |
2391 | .readfn = icc_igrpen_read, |
2392 | .writefn = icc_igrpen_write, | |
2393 | }, | |
2394 | { .name = "ICC_SRE_EL2", .state = ARM_CP_STATE_BOTH, | |
2395 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 9, .opc2 = 5, | |
2396 | .type = ARM_CP_NO_RAW | ARM_CP_CONST, | |
2397 | .access = PL2_RW, | |
2398 | /* We don't support IRQ/FIQ bypass and system registers are | |
2399 | * always enabled, so all our bits are RAZ/WI or RAO/WI. | |
2400 | */ | |
2401 | .resetvalue = 0xf, | |
2402 | }, | |
2403 | { .name = "ICC_CTLR_EL3", .state = ARM_CP_STATE_BOTH, | |
2404 | .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 12, .opc2 = 4, | |
2405 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2406 | .access = PL3_RW, | |
359fbe65 PM |
2407 | .readfn = icc_ctlr_el3_read, |
2408 | .writefn = icc_ctlr_el3_write, | |
2409 | }, | |
2410 | { .name = "ICC_SRE_EL3", .state = ARM_CP_STATE_BOTH, | |
2411 | .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 12, .opc2 = 5, | |
2412 | .type = ARM_CP_NO_RAW | ARM_CP_CONST, | |
2413 | .access = PL3_RW, | |
2414 | /* We don't support IRQ/FIQ bypass and system registers are | |
2415 | * always enabled, so all our bits are RAZ/WI or RAO/WI. | |
2416 | */ | |
2417 | .resetvalue = 0xf, | |
2418 | }, | |
2419 | { .name = "ICC_IGRPEN1_EL3", .state = ARM_CP_STATE_BOTH, | |
2420 | .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 12, .opc2 = 7, | |
2421 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2422 | .access = PL3_RW, | |
2423 | .readfn = icc_igrpen1_el3_read, | |
2424 | .writefn = icc_igrpen1_el3_write, | |
2425 | }, | |
359fbe65 PM |
2426 | }; |
2427 | ||
84597ff3 PM |
2428 | static const ARMCPRegInfo gicv3_cpuif_icc_apxr1_reginfo[] = { |
2429 | { .name = "ICC_AP0R1_EL1", .state = ARM_CP_STATE_BOTH, | |
2430 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 5, | |
2431 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2432 | .access = PL1_RW, .accessfn = gicv3_fiq_access, | |
2433 | .readfn = icc_ap_read, | |
2434 | .writefn = icc_ap_write, | |
2435 | }, | |
2436 | { .name = "ICC_AP1R1_EL1", .state = ARM_CP_STATE_BOTH, | |
2437 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 9, .opc2 = 1, | |
2438 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2439 | .access = PL1_RW, .accessfn = gicv3_irq_access, | |
2440 | .readfn = icc_ap_read, | |
2441 | .writefn = icc_ap_write, | |
2442 | }, | |
2443 | }; | |
2444 | ||
2445 | static const ARMCPRegInfo gicv3_cpuif_icc_apxr23_reginfo[] = { | |
2446 | { .name = "ICC_AP0R2_EL1", .state = ARM_CP_STATE_BOTH, | |
2447 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 6, | |
2448 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2449 | .access = PL1_RW, .accessfn = gicv3_fiq_access, | |
2450 | .readfn = icc_ap_read, | |
2451 | .writefn = icc_ap_write, | |
2452 | }, | |
2453 | { .name = "ICC_AP0R3_EL1", .state = ARM_CP_STATE_BOTH, | |
2454 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 7, | |
2455 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2456 | .access = PL1_RW, .accessfn = gicv3_fiq_access, | |
2457 | .readfn = icc_ap_read, | |
2458 | .writefn = icc_ap_write, | |
2459 | }, | |
2460 | { .name = "ICC_AP1R2_EL1", .state = ARM_CP_STATE_BOTH, | |
2461 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 9, .opc2 = 2, | |
2462 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2463 | .access = PL1_RW, .accessfn = gicv3_irq_access, | |
2464 | .readfn = icc_ap_read, | |
2465 | .writefn = icc_ap_write, | |
2466 | }, | |
2467 | { .name = "ICC_AP1R3_EL1", .state = ARM_CP_STATE_BOTH, | |
2468 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 9, .opc2 = 3, | |
2469 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2470 | .access = PL1_RW, .accessfn = gicv3_irq_access, | |
2471 | .readfn = icc_ap_read, | |
2472 | .writefn = icc_ap_write, | |
2473 | }, | |
2474 | }; | |
2475 | ||
83f036fe PM |
2476 | static uint64_t ich_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) |
2477 | { | |
2478 | GICv3CPUState *cs = icc_cs_from_env(env); | |
2479 | int regno = ri->opc2 & 3; | |
887aae10 | 2480 | int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0; |
83f036fe PM |
2481 | uint64_t value; |
2482 | ||
2483 | value = cs->ich_apr[grp][regno]; | |
2484 | trace_gicv3_ich_ap_read(ri->crm & 1, regno, gicv3_redist_affid(cs), value); | |
2485 | return value; | |
2486 | } | |
2487 | ||
2488 | static void ich_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2489 | uint64_t value) | |
2490 | { | |
2491 | GICv3CPUState *cs = icc_cs_from_env(env); | |
2492 | int regno = ri->opc2 & 3; | |
887aae10 | 2493 | int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0; |
83f036fe PM |
2494 | |
2495 | trace_gicv3_ich_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value); | |
2496 | ||
2497 | cs->ich_apr[grp][regno] = value & 0xFFFFFFFFU; | |
189d1d9d | 2498 | gicv3_cpuif_virt_irq_fiq_update(cs); |
83f036fe PM |
2499 | } |
2500 | ||
2501 | static uint64_t ich_hcr_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2502 | { | |
2503 | GICv3CPUState *cs = icc_cs_from_env(env); | |
2504 | uint64_t value = cs->ich_hcr_el2; | |
2505 | ||
2506 | trace_gicv3_ich_hcr_read(gicv3_redist_affid(cs), value); | |
2507 | return value; | |
2508 | } | |
2509 | ||
2510 | static void ich_hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2511 | uint64_t value) | |
2512 | { | |
2513 | GICv3CPUState *cs = icc_cs_from_env(env); | |
2514 | ||
2515 | trace_gicv3_ich_hcr_write(gicv3_redist_affid(cs), value); | |
2516 | ||
2517 | value &= ICH_HCR_EL2_EN | ICH_HCR_EL2_UIE | ICH_HCR_EL2_LRENPIE | | |
2518 | ICH_HCR_EL2_NPIE | ICH_HCR_EL2_VGRP0EIE | ICH_HCR_EL2_VGRP0DIE | | |
2519 | ICH_HCR_EL2_VGRP1EIE | ICH_HCR_EL2_VGRP1DIE | ICH_HCR_EL2_TC | | |
2520 | ICH_HCR_EL2_TALL0 | ICH_HCR_EL2_TALL1 | ICH_HCR_EL2_TSEI | | |
2521 | ICH_HCR_EL2_TDIR | ICH_HCR_EL2_EOICOUNT_MASK; | |
2522 | ||
2523 | cs->ich_hcr_el2 = value; | |
2524 | gicv3_cpuif_virt_update(cs); | |
2525 | } | |
2526 | ||
2527 | static uint64_t ich_vmcr_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2528 | { | |
2529 | GICv3CPUState *cs = icc_cs_from_env(env); | |
2530 | uint64_t value = cs->ich_vmcr_el2; | |
2531 | ||
2532 | trace_gicv3_ich_vmcr_read(gicv3_redist_affid(cs), value); | |
2533 | return value; | |
2534 | } | |
2535 | ||
2536 | static void ich_vmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2537 | uint64_t value) | |
2538 | { | |
2539 | GICv3CPUState *cs = icc_cs_from_env(env); | |
2540 | ||
2541 | trace_gicv3_ich_vmcr_write(gicv3_redist_affid(cs), value); | |
2542 | ||
2543 | value &= ICH_VMCR_EL2_VENG0 | ICH_VMCR_EL2_VENG1 | ICH_VMCR_EL2_VCBPR | | |
2544 | ICH_VMCR_EL2_VEOIM | ICH_VMCR_EL2_VBPR1_MASK | | |
2545 | ICH_VMCR_EL2_VBPR0_MASK | ICH_VMCR_EL2_VPMR_MASK; | |
2546 | value |= ICH_VMCR_EL2_VFIQEN; | |
2547 | ||
2548 | cs->ich_vmcr_el2 = value; | |
2549 | /* Enforce "writing BPRs to less than minimum sets them to the minimum" | |
2550 | * by reading and writing back the fields. | |
2551 | */ | |
8b7fbd6c | 2552 | write_vbpr(cs, GICV3_G0, read_vbpr(cs, GICV3_G0)); |
83f036fe PM |
2553 | write_vbpr(cs, GICV3_G1, read_vbpr(cs, GICV3_G1)); |
2554 | ||
2555 | gicv3_cpuif_virt_update(cs); | |
2556 | } | |
2557 | ||
2558 | static uint64_t ich_lr_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2559 | { | |
2560 | GICv3CPUState *cs = icc_cs_from_env(env); | |
2561 | int regno = ri->opc2 | ((ri->crm & 1) << 3); | |
2562 | uint64_t value; | |
2563 | ||
2564 | /* This read function handles all of: | |
2565 | * 64-bit reads of the whole LR | |
2566 | * 32-bit reads of the low half of the LR | |
2567 | * 32-bit reads of the high half of the LR | |
2568 | */ | |
2569 | if (ri->state == ARM_CP_STATE_AA32) { | |
2570 | if (ri->crm >= 14) { | |
2571 | value = extract64(cs->ich_lr_el2[regno], 32, 32); | |
2572 | trace_gicv3_ich_lrc_read(regno, gicv3_redist_affid(cs), value); | |
2573 | } else { | |
2574 | value = extract64(cs->ich_lr_el2[regno], 0, 32); | |
2575 | trace_gicv3_ich_lr32_read(regno, gicv3_redist_affid(cs), value); | |
2576 | } | |
2577 | } else { | |
2578 | value = cs->ich_lr_el2[regno]; | |
2579 | trace_gicv3_ich_lr_read(regno, gicv3_redist_affid(cs), value); | |
2580 | } | |
2581 | ||
2582 | return value; | |
2583 | } | |
2584 | ||
2585 | static void ich_lr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2586 | uint64_t value) | |
2587 | { | |
2588 | GICv3CPUState *cs = icc_cs_from_env(env); | |
2589 | int regno = ri->opc2 | ((ri->crm & 1) << 3); | |
2590 | ||
2591 | /* This write function handles all of: | |
2592 | * 64-bit writes to the whole LR | |
2593 | * 32-bit writes to the low half of the LR | |
2594 | * 32-bit writes to the high half of the LR | |
2595 | */ | |
2596 | if (ri->state == ARM_CP_STATE_AA32) { | |
2597 | if (ri->crm >= 14) { | |
2598 | trace_gicv3_ich_lrc_write(regno, gicv3_redist_affid(cs), value); | |
2599 | value = deposit64(cs->ich_lr_el2[regno], 32, 32, value); | |
2600 | } else { | |
2601 | trace_gicv3_ich_lr32_write(regno, gicv3_redist_affid(cs), value); | |
2602 | value = deposit64(cs->ich_lr_el2[regno], 0, 32, value); | |
2603 | } | |
2604 | } else { | |
2605 | trace_gicv3_ich_lr_write(regno, gicv3_redist_affid(cs), value); | |
2606 | } | |
2607 | ||
2608 | /* Enforce RES0 bits in priority field */ | |
2609 | if (cs->vpribits < 8) { | |
2610 | value = deposit64(value, ICH_LR_EL2_PRIORITY_SHIFT, | |
2611 | 8 - cs->vpribits, 0); | |
2612 | } | |
2613 | ||
2614 | cs->ich_lr_el2[regno] = value; | |
2615 | gicv3_cpuif_virt_update(cs); | |
2616 | } | |
2617 | ||
2618 | static uint64_t ich_vtr_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2619 | { | |
2620 | GICv3CPUState *cs = icc_cs_from_env(env); | |
2621 | uint64_t value; | |
2622 | ||
2623 | value = ((cs->num_list_regs - 1) << ICH_VTR_EL2_LISTREGS_SHIFT) | |
e2d5e189 | 2624 | | ICH_VTR_EL2_TDS | ICH_VTR_EL2_A3V |
83f036fe PM |
2625 | | (1 << ICH_VTR_EL2_IDBITS_SHIFT) |
2626 | | ((cs->vprebits - 1) << ICH_VTR_EL2_PREBITS_SHIFT) | |
2627 | | ((cs->vpribits - 1) << ICH_VTR_EL2_PRIBITS_SHIFT); | |
2628 | ||
e2d5e189 PM |
2629 | if (cs->gic->revision < 4) { |
2630 | value |= ICH_VTR_EL2_NV4; | |
2631 | } | |
2632 | ||
83f036fe PM |
2633 | trace_gicv3_ich_vtr_read(gicv3_redist_affid(cs), value); |
2634 | return value; | |
2635 | } | |
2636 | ||
2637 | static uint64_t ich_misr_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2638 | { | |
2639 | GICv3CPUState *cs = icc_cs_from_env(env); | |
2640 | uint64_t value = maintenance_interrupt_state(cs); | |
2641 | ||
2642 | trace_gicv3_ich_misr_read(gicv3_redist_affid(cs), value); | |
2643 | return value; | |
2644 | } | |
2645 | ||
2646 | static uint64_t ich_eisr_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2647 | { | |
2648 | GICv3CPUState *cs = icc_cs_from_env(env); | |
2649 | uint64_t value = eoi_maintenance_interrupt_state(cs, NULL); | |
2650 | ||
2651 | trace_gicv3_ich_eisr_read(gicv3_redist_affid(cs), value); | |
2652 | return value; | |
2653 | } | |
2654 | ||
2655 | static uint64_t ich_elrsr_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2656 | { | |
2657 | GICv3CPUState *cs = icc_cs_from_env(env); | |
2658 | uint64_t value = 0; | |
2659 | int i; | |
2660 | ||
2661 | for (i = 0; i < cs->num_list_regs; i++) { | |
2662 | uint64_t lr = cs->ich_lr_el2[i]; | |
2663 | ||
2664 | if ((lr & ICH_LR_EL2_STATE_MASK) == 0 && | |
d87576e3 | 2665 | ((lr & ICH_LR_EL2_HW) != 0 || (lr & ICH_LR_EL2_EOI) == 0)) { |
83f036fe PM |
2666 | value |= (1 << i); |
2667 | } | |
2668 | } | |
2669 | ||
2670 | trace_gicv3_ich_elrsr_read(gicv3_redist_affid(cs), value); | |
2671 | return value; | |
2672 | } | |
2673 | ||
2674 | static const ARMCPRegInfo gicv3_cpuif_hcr_reginfo[] = { | |
2675 | { .name = "ICH_AP0R0_EL2", .state = ARM_CP_STATE_BOTH, | |
2676 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 8, .opc2 = 0, | |
2677 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2678 | .access = PL2_RW, | |
2679 | .readfn = ich_ap_read, | |
2680 | .writefn = ich_ap_write, | |
2681 | }, | |
2682 | { .name = "ICH_AP1R0_EL2", .state = ARM_CP_STATE_BOTH, | |
2683 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 9, .opc2 = 0, | |
2684 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2685 | .access = PL2_RW, | |
2686 | .readfn = ich_ap_read, | |
2687 | .writefn = ich_ap_write, | |
2688 | }, | |
2689 | { .name = "ICH_HCR_EL2", .state = ARM_CP_STATE_BOTH, | |
2690 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 11, .opc2 = 0, | |
2691 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2692 | .access = PL2_RW, | |
2693 | .readfn = ich_hcr_read, | |
2694 | .writefn = ich_hcr_write, | |
2695 | }, | |
2696 | { .name = "ICH_VTR_EL2", .state = ARM_CP_STATE_BOTH, | |
2697 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 11, .opc2 = 1, | |
2698 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2699 | .access = PL2_R, | |
2700 | .readfn = ich_vtr_read, | |
2701 | }, | |
2702 | { .name = "ICH_MISR_EL2", .state = ARM_CP_STATE_BOTH, | |
2703 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 11, .opc2 = 2, | |
2704 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2705 | .access = PL2_R, | |
2706 | .readfn = ich_misr_read, | |
2707 | }, | |
2708 | { .name = "ICH_EISR_EL2", .state = ARM_CP_STATE_BOTH, | |
2709 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 11, .opc2 = 3, | |
2710 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2711 | .access = PL2_R, | |
2712 | .readfn = ich_eisr_read, | |
2713 | }, | |
2714 | { .name = "ICH_ELRSR_EL2", .state = ARM_CP_STATE_BOTH, | |
2715 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 11, .opc2 = 5, | |
2716 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2717 | .access = PL2_R, | |
2718 | .readfn = ich_elrsr_read, | |
2719 | }, | |
2720 | { .name = "ICH_VMCR_EL2", .state = ARM_CP_STATE_BOTH, | |
2721 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 11, .opc2 = 7, | |
2722 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2723 | .access = PL2_RW, | |
2724 | .readfn = ich_vmcr_read, | |
2725 | .writefn = ich_vmcr_write, | |
2726 | }, | |
83f036fe PM |
2727 | }; |
2728 | ||
2729 | static const ARMCPRegInfo gicv3_cpuif_ich_apxr1_reginfo[] = { | |
2730 | { .name = "ICH_AP0R1_EL2", .state = ARM_CP_STATE_BOTH, | |
2731 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 8, .opc2 = 1, | |
2732 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2733 | .access = PL2_RW, | |
2734 | .readfn = ich_ap_read, | |
2735 | .writefn = ich_ap_write, | |
2736 | }, | |
2737 | { .name = "ICH_AP1R1_EL2", .state = ARM_CP_STATE_BOTH, | |
2738 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 9, .opc2 = 1, | |
2739 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2740 | .access = PL2_RW, | |
2741 | .readfn = ich_ap_read, | |
2742 | .writefn = ich_ap_write, | |
2743 | }, | |
83f036fe PM |
2744 | }; |
2745 | ||
2746 | static const ARMCPRegInfo gicv3_cpuif_ich_apxr23_reginfo[] = { | |
2747 | { .name = "ICH_AP0R2_EL2", .state = ARM_CP_STATE_BOTH, | |
2748 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 8, .opc2 = 2, | |
2749 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2750 | .access = PL2_RW, | |
2751 | .readfn = ich_ap_read, | |
2752 | .writefn = ich_ap_write, | |
2753 | }, | |
2754 | { .name = "ICH_AP0R3_EL2", .state = ARM_CP_STATE_BOTH, | |
2755 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 8, .opc2 = 3, | |
2756 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2757 | .access = PL2_RW, | |
2758 | .readfn = ich_ap_read, | |
2759 | .writefn = ich_ap_write, | |
2760 | }, | |
2761 | { .name = "ICH_AP1R2_EL2", .state = ARM_CP_STATE_BOTH, | |
2762 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 9, .opc2 = 2, | |
2763 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2764 | .access = PL2_RW, | |
2765 | .readfn = ich_ap_read, | |
2766 | .writefn = ich_ap_write, | |
2767 | }, | |
2768 | { .name = "ICH_AP1R3_EL2", .state = ARM_CP_STATE_BOTH, | |
2769 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 9, .opc2 = 3, | |
2770 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2771 | .access = PL2_RW, | |
2772 | .readfn = ich_ap_read, | |
2773 | .writefn = ich_ap_write, | |
2774 | }, | |
83f036fe PM |
2775 | }; |
2776 | ||
359fbe65 PM |
2777 | static void gicv3_cpuif_el_change_hook(ARMCPU *cpu, void *opaque) |
2778 | { | |
f7b9358e PM |
2779 | GICv3CPUState *cs = opaque; |
2780 | ||
2781 | gicv3_cpuif_update(cs); | |
c3f21b06 PM |
2782 | /* |
2783 | * Because vLPIs are only pending in NonSecure state, | |
2784 | * an EL change can change the VIRQ/VFIQ status (but | |
2785 | * cannot affect the maintenance interrupt state) | |
2786 | */ | |
2787 | gicv3_cpuif_virt_irq_fiq_update(cs); | |
359fbe65 PM |
2788 | } |
2789 | ||
2790 | void gicv3_init_cpuif(GICv3State *s) | |
2791 | { | |
2792 | /* Called from the GICv3 realize function; register our system | |
2793 | * registers with the CPU | |
2794 | */ | |
2795 | int i; | |
2796 | ||
2797 | for (i = 0; i < s->num_cpu; i++) { | |
2798 | ARMCPU *cpu = ARM_CPU(qemu_get_cpu(i)); | |
2799 | GICv3CPUState *cs = &s->cpu[i]; | |
2800 | ||
272f75e8 PM |
2801 | /* |
2802 | * If the CPU doesn't define a GICv3 configuration, probably because | |
2803 | * in real hardware it doesn't have one, then we use default values | |
2804 | * matching the one used by most Arm CPUs. This applies to: | |
2805 | * cpu->gic_num_lrs | |
2806 | * cpu->gic_vpribits | |
2807 | * cpu->gic_vprebits | |
39f29e59 | 2808 | * cpu->gic_pribits |
272f75e8 PM |
2809 | */ |
2810 | ||
359fbe65 PM |
2811 | /* Note that we can't just use the GICv3CPUState as an opaque pointer |
2812 | * in define_arm_cp_regs_with_opaque(), because when we're called back | |
2813 | * it might be with code translated by CPU 0 but run by CPU 1, in | |
2814 | * which case we'd get the wrong value. | |
2815 | * So instead we define the regs with no ri->opaque info, and | |
d5a5e4c9 | 2816 | * get back to the GICv3CPUState from the CPUARMState. |
a2260983 AG |
2817 | * |
2818 | * These CP regs callbacks can be called from either TCG or HVF code. | |
359fbe65 PM |
2819 | */ |
2820 | define_arm_cp_regs(cpu, gicv3_cpuif_reginfo); | |
84597ff3 PM |
2821 | |
2822 | /* | |
39f29e59 PM |
2823 | * The CPU implementation specifies the number of supported |
2824 | * bits of physical priority. For backwards compatibility | |
2825 | * of migration, we have a compat property that forces use | |
2826 | * of 8 priority bits regardless of what the CPU really has. | |
84597ff3 | 2827 | */ |
39f29e59 PM |
2828 | if (s->force_8bit_prio) { |
2829 | cs->pribits = 8; | |
2830 | } else { | |
2831 | cs->pribits = cpu->gic_pribits ?: 5; | |
2832 | } | |
2833 | ||
84597ff3 PM |
2834 | /* |
2835 | * The GICv3 has separate ID register fields for virtual priority | |
2836 | * and preemption bit values, but only a single ID register field | |
2837 | * for the physical priority bits. The preemption bit count is | |
2838 | * always the same as the priority bit count, except that 8 bits | |
2839 | * of priority means 7 preemption bits. We precalculate the | |
2840 | * preemption bits because it simplifies the code and makes the | |
2841 | * parallels between the virtual and physical bits of the GIC | |
2842 | * a bit clearer. | |
2843 | */ | |
2844 | cs->prebits = cs->pribits; | |
2845 | if (cs->prebits == 8) { | |
2846 | cs->prebits--; | |
2847 | } | |
2848 | /* | |
2849 | * Check that CPU code defining pribits didn't violate | |
2850 | * architectural constraints our implementation relies on. | |
2851 | */ | |
2852 | g_assert(cs->pribits >= 4 && cs->pribits <= 8); | |
2853 | ||
2854 | /* | |
2855 | * gicv3_cpuif_reginfo[] defines ICC_AP*R0_EL1; add definitions | |
2856 | * for ICC_AP*R{1,2,3}_EL1 if the prebits value requires them. | |
2857 | */ | |
2858 | if (cs->prebits >= 6) { | |
2859 | define_arm_cp_regs(cpu, gicv3_cpuif_icc_apxr1_reginfo); | |
2860 | } | |
2861 | if (cs->prebits == 7) { | |
2862 | define_arm_cp_regs(cpu, gicv3_cpuif_icc_apxr23_reginfo); | |
2863 | } | |
2864 | ||
272f75e8 | 2865 | if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { |
83f036fe PM |
2866 | int j; |
2867 | ||
272f75e8 PM |
2868 | cs->num_list_regs = cpu->gic_num_lrs ?: 4; |
2869 | cs->vpribits = cpu->gic_vpribits ?: 5; | |
2870 | cs->vprebits = cpu->gic_vprebits ?: 5; | |
83f036fe PM |
2871 | |
2872 | /* Check against architectural constraints: getting these | |
2873 | * wrong would be a bug in the CPU code defining these, | |
2874 | * and the implementation relies on them holding. | |
2875 | */ | |
2876 | g_assert(cs->vprebits <= cs->vpribits); | |
2877 | g_assert(cs->vprebits >= 5 && cs->vprebits <= 7); | |
2878 | g_assert(cs->vpribits >= 5 && cs->vpribits <= 8); | |
2879 | ||
2880 | define_arm_cp_regs(cpu, gicv3_cpuif_hcr_reginfo); | |
2881 | ||
2882 | for (j = 0; j < cs->num_list_regs; j++) { | |
2883 | /* Note that the AArch64 LRs are 64-bit; the AArch32 LRs | |
2884 | * are split into two cp15 regs, LR (the low part, with the | |
2885 | * same encoding as the AArch64 LR) and LRC (the high part). | |
2886 | */ | |
2887 | ARMCPRegInfo lr_regset[] = { | |
2888 | { .name = "ICH_LRn_EL2", .state = ARM_CP_STATE_BOTH, | |
2889 | .opc0 = 3, .opc1 = 4, .crn = 12, | |
2890 | .crm = 12 + (j >> 3), .opc2 = j & 7, | |
2891 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2892 | .access = PL2_RW, | |
2893 | .readfn = ich_lr_read, | |
2894 | .writefn = ich_lr_write, | |
2895 | }, | |
2896 | { .name = "ICH_LRCn_EL2", .state = ARM_CP_STATE_AA32, | |
2897 | .cp = 15, .opc1 = 4, .crn = 12, | |
2898 | .crm = 14 + (j >> 3), .opc2 = j & 7, | |
2899 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | |
2900 | .access = PL2_RW, | |
2901 | .readfn = ich_lr_read, | |
2902 | .writefn = ich_lr_write, | |
2903 | }, | |
83f036fe PM |
2904 | }; |
2905 | define_arm_cp_regs(cpu, lr_regset); | |
2906 | } | |
2907 | if (cs->vprebits >= 6) { | |
2908 | define_arm_cp_regs(cpu, gicv3_cpuif_ich_apxr1_reginfo); | |
2909 | } | |
2910 | if (cs->vprebits == 7) { | |
2911 | define_arm_cp_regs(cpu, gicv3_cpuif_ich_apxr23_reginfo); | |
2912 | } | |
2913 | } | |
a2260983 AG |
2914 | if (tcg_enabled() || qtest_enabled()) { |
2915 | /* | |
2916 | * We can only trap EL changes with TCG. However the GIC interrupt | |
2917 | * state only changes on EL changes involving EL2 or EL3, so for | |
2918 | * the non-TCG case this is OK, as EL2 and EL3 can't exist. | |
2919 | */ | |
2920 | arm_register_el_change_hook(cpu, gicv3_cpuif_el_change_hook, cs); | |
2921 | } else { | |
2922 | assert(!arm_feature(&cpu->env, ARM_FEATURE_EL2)); | |
2923 | assert(!arm_feature(&cpu->env, ARM_FEATURE_EL3)); | |
2924 | } | |
359fbe65 PM |
2925 | } |
2926 | } |