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9ee6e8bb PB |
1 | /* |
2 | * ARM Nested Vectored Interrupt Controller | |
3 | * | |
4 | * Copyright (c) 2006-2007 CodeSourcery. | |
5 | * Written by Paul Brook | |
6 | * | |
8e31bf38 | 7 | * This code is licensed under the GPL. |
9ee6e8bb PB |
8 | * |
9 | * The ARMv7M System controller is fairly tightly tied in with the | |
10 | * NVIC. Much of that is also implemented here. | |
11 | */ | |
12 | ||
8ef94f0b | 13 | #include "qemu/osdep.h" |
da34e65c | 14 | #include "qapi/error.h" |
4771d756 | 15 | #include "qemu-common.h" |
33c11879 | 16 | #include "cpu.h" |
83c9f4ca | 17 | #include "hw/sysbus.h" |
1de7afc9 | 18 | #include "qemu/timer.h" |
bd2be150 | 19 | #include "hw/arm/arm.h" |
d2db1de6 | 20 | #include "hw/intc/armv7m_nvic.h" |
da6d674e | 21 | #include "target/arm/cpu.h" |
29c483a5 | 22 | #include "exec/exec-all.h" |
03dd024f | 23 | #include "qemu/log.h" |
da6d674e MD |
24 | #include "trace.h" |
25 | ||
26 | /* IRQ number counting: | |
27 | * | |
28 | * the num-irq property counts the number of external IRQ lines | |
29 | * | |
30 | * NVICState::num_irq counts the total number of exceptions | |
31 | * (external IRQs, the 15 internal exceptions including reset, | |
32 | * and one for the unused exception number 0). | |
33 | * | |
34 | * NVIC_MAX_IRQ is the highest permitted number of external IRQ lines. | |
35 | * | |
36 | * NVIC_MAX_VECTORS is the highest permitted number of exceptions. | |
37 | * | |
38 | * Iterating through all exceptions should typically be done with | |
39 | * for (i = 1; i < s->num_irq; i++) to avoid the unused slot 0. | |
40 | * | |
41 | * The external qemu_irq lines are the NVIC's external IRQ lines, | |
42 | * so line 0 is exception 16. | |
43 | * | |
44 | * In the terminology of the architecture manual, "interrupts" are | |
45 | * a subcategory of exception referring to the external interrupts | |
46 | * (which are exception numbers NVIC_FIRST_IRQ and upward). | |
47 | * For historical reasons QEMU tends to use "interrupt" and | |
48 | * "exception" more or less interchangeably. | |
49 | */ | |
17906a16 | 50 | #define NVIC_FIRST_IRQ NVIC_INTERNAL_VECTORS |
da6d674e MD |
51 | #define NVIC_MAX_IRQ (NVIC_MAX_VECTORS - NVIC_FIRST_IRQ) |
52 | ||
53 | /* Effective running priority of the CPU when no exception is active | |
54 | * (higher than the highest possible priority value) | |
55 | */ | |
56 | #define NVIC_NOEXC_PRIO 0x100 | |
ff96c64a PM |
57 | /* Maximum priority of non-secure exceptions when AIRCR.PRIS is set */ |
58 | #define NVIC_NS_PRIO_LIMIT 0x80 | |
da6d674e | 59 | |
2a29ddee PM |
60 | static const uint8_t nvic_id[] = { |
61 | 0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1 | |
62 | }; | |
63 | ||
da6d674e MD |
64 | static int nvic_pending_prio(NVICState *s) |
65 | { | |
5255fcf8 | 66 | /* return the group priority of the current pending interrupt, |
da6d674e MD |
67 | * or NVIC_NOEXC_PRIO if no interrupt is pending |
68 | */ | |
5255fcf8 | 69 | return s->vectpending_prio; |
da6d674e MD |
70 | } |
71 | ||
72 | /* Return the value of the ISCR RETTOBASE bit: | |
73 | * 1 if there is exactly one active exception | |
74 | * 0 if there is more than one active exception | |
75 | * UNKNOWN if there are no active exceptions (we choose 1, | |
76 | * which matches the choice Cortex-M3 is documented as making). | |
77 | * | |
78 | * NB: some versions of the documentation talk about this | |
79 | * counting "active exceptions other than the one shown by IPSR"; | |
80 | * this is only different in the obscure corner case where guest | |
81 | * code has manually deactivated an exception and is about | |
82 | * to fail an exception-return integrity check. The definition | |
83 | * above is the one from the v8M ARM ARM and is also in line | |
84 | * with the behaviour documented for the Cortex-M3. | |
85 | */ | |
86 | static bool nvic_rettobase(NVICState *s) | |
87 | { | |
88 | int irq, nhand = 0; | |
028b0da4 | 89 | bool check_sec = arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY); |
da6d674e MD |
90 | |
91 | for (irq = ARMV7M_EXCP_RESET; irq < s->num_irq; irq++) { | |
028b0da4 PM |
92 | if (s->vectors[irq].active || |
93 | (check_sec && irq < NVIC_INTERNAL_VECTORS && | |
94 | s->sec_vectors[irq].active)) { | |
da6d674e MD |
95 | nhand++; |
96 | if (nhand == 2) { | |
97 | return 0; | |
98 | } | |
99 | } | |
100 | } | |
101 | ||
102 | return 1; | |
103 | } | |
104 | ||
105 | /* Return the value of the ISCR ISRPENDING bit: | |
106 | * 1 if an external interrupt is pending | |
107 | * 0 if no external interrupt is pending | |
108 | */ | |
109 | static bool nvic_isrpending(NVICState *s) | |
110 | { | |
111 | int irq; | |
112 | ||
113 | /* We can shortcut if the highest priority pending interrupt | |
114 | * happens to be external or if there is nothing pending. | |
115 | */ | |
116 | if (s->vectpending > NVIC_FIRST_IRQ) { | |
117 | return true; | |
118 | } | |
119 | if (s->vectpending == 0) { | |
120 | return false; | |
121 | } | |
122 | ||
123 | for (irq = NVIC_FIRST_IRQ; irq < s->num_irq; irq++) { | |
124 | if (s->vectors[irq].pending) { | |
125 | return true; | |
126 | } | |
127 | } | |
128 | return false; | |
129 | } | |
130 | ||
ff96c64a PM |
131 | static bool exc_is_banked(int exc) |
132 | { | |
133 | /* Return true if this is one of the limited set of exceptions which | |
134 | * are banked (and thus have state in sec_vectors[]) | |
135 | */ | |
136 | return exc == ARMV7M_EXCP_HARD || | |
137 | exc == ARMV7M_EXCP_MEM || | |
138 | exc == ARMV7M_EXCP_USAGE || | |
139 | exc == ARMV7M_EXCP_SVC || | |
140 | exc == ARMV7M_EXCP_PENDSV || | |
141 | exc == ARMV7M_EXCP_SYSTICK; | |
142 | } | |
143 | ||
da6d674e MD |
144 | /* Return a mask word which clears the subpriority bits from |
145 | * a priority value for an M-profile exception, leaving only | |
146 | * the group priority. | |
147 | */ | |
ff96c64a | 148 | static inline uint32_t nvic_gprio_mask(NVICState *s, bool secure) |
da6d674e | 149 | { |
ff96c64a PM |
150 | return ~0U << (s->prigroup[secure] + 1); |
151 | } | |
152 | ||
153 | static bool exc_targets_secure(NVICState *s, int exc) | |
154 | { | |
155 | /* Return true if this non-banked exception targets Secure state. */ | |
156 | if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) { | |
157 | return false; | |
158 | } | |
159 | ||
160 | if (exc >= NVIC_FIRST_IRQ) { | |
161 | return !s->itns[exc]; | |
162 | } | |
163 | ||
164 | /* Function shouldn't be called for banked exceptions. */ | |
165 | assert(!exc_is_banked(exc)); | |
166 | ||
167 | switch (exc) { | |
168 | case ARMV7M_EXCP_NMI: | |
169 | case ARMV7M_EXCP_BUS: | |
170 | return !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK); | |
171 | case ARMV7M_EXCP_SECURE: | |
172 | return true; | |
173 | case ARMV7M_EXCP_DEBUG: | |
174 | /* TODO: controlled by DEMCR.SDME, which we don't yet implement */ | |
175 | return false; | |
176 | default: | |
177 | /* reset, and reserved (unused) low exception numbers. | |
178 | * We'll get called by code that loops through all the exception | |
179 | * numbers, but it doesn't matter what we return here as these | |
180 | * non-existent exceptions will never be pended or active. | |
181 | */ | |
182 | return true; | |
183 | } | |
184 | } | |
185 | ||
186 | static int exc_group_prio(NVICState *s, int rawprio, bool targets_secure) | |
187 | { | |
188 | /* Return the group priority for this exception, given its raw | |
189 | * (group-and-subgroup) priority value and whether it is targeting | |
190 | * secure state or not. | |
191 | */ | |
192 | if (rawprio < 0) { | |
193 | return rawprio; | |
194 | } | |
195 | rawprio &= nvic_gprio_mask(s, targets_secure); | |
196 | /* AIRCR.PRIS causes us to squash all NS priorities into the | |
197 | * lower half of the total range | |
198 | */ | |
199 | if (!targets_secure && | |
200 | (s->cpu->env.v7m.aircr & R_V7M_AIRCR_PRIS_MASK)) { | |
201 | rawprio = (rawprio >> 1) + NVIC_NS_PRIO_LIMIT; | |
202 | } | |
203 | return rawprio; | |
204 | } | |
205 | ||
206 | /* Recompute vectpending and exception_prio for a CPU which implements | |
207 | * the Security extension | |
208 | */ | |
209 | static void nvic_recompute_state_secure(NVICState *s) | |
210 | { | |
211 | int i, bank; | |
212 | int pend_prio = NVIC_NOEXC_PRIO; | |
213 | int active_prio = NVIC_NOEXC_PRIO; | |
214 | int pend_irq = 0; | |
215 | bool pending_is_s_banked = false; | |
216 | ||
217 | /* R_CQRV: precedence is by: | |
218 | * - lowest group priority; if both the same then | |
219 | * - lowest subpriority; if both the same then | |
220 | * - lowest exception number; if both the same (ie banked) then | |
221 | * - secure exception takes precedence | |
222 | * Compare pseudocode RawExecutionPriority. | |
223 | * Annoyingly, now we have two prigroup values (for S and NS) | |
224 | * we can't do the loop comparison on raw priority values. | |
225 | */ | |
226 | for (i = 1; i < s->num_irq; i++) { | |
227 | for (bank = M_REG_S; bank >= M_REG_NS; bank--) { | |
228 | VecInfo *vec; | |
229 | int prio; | |
230 | bool targets_secure; | |
231 | ||
232 | if (bank == M_REG_S) { | |
233 | if (!exc_is_banked(i)) { | |
234 | continue; | |
235 | } | |
236 | vec = &s->sec_vectors[i]; | |
237 | targets_secure = true; | |
238 | } else { | |
239 | vec = &s->vectors[i]; | |
240 | targets_secure = !exc_is_banked(i) && exc_targets_secure(s, i); | |
241 | } | |
242 | ||
243 | prio = exc_group_prio(s, vec->prio, targets_secure); | |
244 | if (vec->enabled && vec->pending && prio < pend_prio) { | |
245 | pend_prio = prio; | |
246 | pend_irq = i; | |
247 | pending_is_s_banked = (bank == M_REG_S); | |
248 | } | |
249 | if (vec->active && prio < active_prio) { | |
250 | active_prio = prio; | |
251 | } | |
252 | } | |
253 | } | |
254 | ||
255 | s->vectpending_is_s_banked = pending_is_s_banked; | |
256 | s->vectpending = pend_irq; | |
257 | s->vectpending_prio = pend_prio; | |
258 | s->exception_prio = active_prio; | |
259 | ||
260 | trace_nvic_recompute_state_secure(s->vectpending, | |
261 | s->vectpending_is_s_banked, | |
262 | s->vectpending_prio, | |
263 | s->exception_prio); | |
da6d674e MD |
264 | } |
265 | ||
266 | /* Recompute vectpending and exception_prio */ | |
267 | static void nvic_recompute_state(NVICState *s) | |
268 | { | |
269 | int i; | |
270 | int pend_prio = NVIC_NOEXC_PRIO; | |
271 | int active_prio = NVIC_NOEXC_PRIO; | |
272 | int pend_irq = 0; | |
273 | ||
ff96c64a PM |
274 | /* In theory we could write one function that handled both |
275 | * the "security extension present" and "not present"; however | |
276 | * the security related changes significantly complicate the | |
277 | * recomputation just by themselves and mixing both cases together | |
278 | * would be even worse, so we retain a separate non-secure-only | |
279 | * version for CPUs which don't implement the security extension. | |
280 | */ | |
281 | if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) { | |
282 | nvic_recompute_state_secure(s); | |
283 | return; | |
284 | } | |
285 | ||
da6d674e MD |
286 | for (i = 1; i < s->num_irq; i++) { |
287 | VecInfo *vec = &s->vectors[i]; | |
288 | ||
289 | if (vec->enabled && vec->pending && vec->prio < pend_prio) { | |
290 | pend_prio = vec->prio; | |
291 | pend_irq = i; | |
292 | } | |
293 | if (vec->active && vec->prio < active_prio) { | |
294 | active_prio = vec->prio; | |
295 | } | |
296 | } | |
297 | ||
22a9c26a | 298 | if (active_prio > 0) { |
ff96c64a | 299 | active_prio &= nvic_gprio_mask(s, false); |
22a9c26a PM |
300 | } |
301 | ||
5255fcf8 | 302 | if (pend_prio > 0) { |
ff96c64a | 303 | pend_prio &= nvic_gprio_mask(s, false); |
5255fcf8 PM |
304 | } |
305 | ||
da6d674e | 306 | s->vectpending = pend_irq; |
5255fcf8 | 307 | s->vectpending_prio = pend_prio; |
22a9c26a | 308 | s->exception_prio = active_prio; |
da6d674e | 309 | |
5255fcf8 PM |
310 | trace_nvic_recompute_state(s->vectpending, |
311 | s->vectpending_prio, | |
312 | s->exception_prio); | |
da6d674e MD |
313 | } |
314 | ||
315 | /* Return the current execution priority of the CPU | |
316 | * (equivalent to the pseudocode ExecutionPriority function). | |
317 | * This is a value between -2 (NMI priority) and NVIC_NOEXC_PRIO. | |
318 | */ | |
319 | static inline int nvic_exec_prio(NVICState *s) | |
320 | { | |
321 | CPUARMState *env = &s->cpu->env; | |
49c80c38 | 322 | int running = NVIC_NOEXC_PRIO; |
da6d674e | 323 | |
49c80c38 PM |
324 | if (env->v7m.basepri[M_REG_NS] > 0) { |
325 | running = exc_group_prio(s, env->v7m.basepri[M_REG_NS], M_REG_NS); | |
326 | } | |
327 | ||
328 | if (env->v7m.basepri[M_REG_S] > 0) { | |
329 | int basepri = exc_group_prio(s, env->v7m.basepri[M_REG_S], M_REG_S); | |
330 | if (running > basepri) { | |
331 | running = basepri; | |
332 | } | |
333 | } | |
334 | ||
335 | if (env->v7m.primask[M_REG_NS]) { | |
336 | if (env->v7m.aircr & R_V7M_AIRCR_PRIS_MASK) { | |
337 | if (running > NVIC_NS_PRIO_LIMIT) { | |
338 | running = NVIC_NS_PRIO_LIMIT; | |
339 | } | |
340 | } else { | |
341 | running = 0; | |
342 | } | |
343 | } | |
344 | ||
345 | if (env->v7m.primask[M_REG_S]) { | |
da6d674e | 346 | running = 0; |
da6d674e | 347 | } |
49c80c38 PM |
348 | |
349 | if (env->v7m.faultmask[M_REG_NS]) { | |
350 | if (env->v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) { | |
351 | running = -1; | |
352 | } else { | |
353 | if (env->v7m.aircr & R_V7M_AIRCR_PRIS_MASK) { | |
354 | if (running > NVIC_NS_PRIO_LIMIT) { | |
355 | running = NVIC_NS_PRIO_LIMIT; | |
356 | } | |
357 | } else { | |
358 | running = 0; | |
359 | } | |
360 | } | |
361 | } | |
362 | ||
363 | if (env->v7m.faultmask[M_REG_S]) { | |
364 | running = (env->v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) ? -3 : -1; | |
365 | } | |
366 | ||
da6d674e MD |
367 | /* consider priority of active handler */ |
368 | return MIN(running, s->exception_prio); | |
369 | } | |
370 | ||
5d479199 PM |
371 | bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) |
372 | { | |
373 | /* Return true if the requested execution priority is negative | |
374 | * for the specified security state, ie that security state | |
375 | * has an active NMI or HardFault or has set its FAULTMASK. | |
376 | * Note that this is not the same as whether the execution | |
377 | * priority is actually negative (for instance AIRCR.PRIS may | |
378 | * mean we don't allow FAULTMASK_NS to actually make the execution | |
379 | * priority negative). Compare pseudocode IsReqExcPriNeg(). | |
380 | */ | |
381 | NVICState *s = opaque; | |
382 | ||
383 | if (s->cpu->env.v7m.faultmask[secure]) { | |
384 | return true; | |
385 | } | |
386 | ||
387 | if (secure ? s->sec_vectors[ARMV7M_EXCP_HARD].active : | |
388 | s->vectors[ARMV7M_EXCP_HARD].active) { | |
389 | return true; | |
390 | } | |
391 | ||
392 | if (s->vectors[ARMV7M_EXCP_NMI].active && | |
393 | exc_targets_secure(s, ARMV7M_EXCP_NMI) == secure) { | |
394 | return true; | |
395 | } | |
396 | ||
397 | return false; | |
398 | } | |
399 | ||
7ecdaa4a PM |
400 | bool armv7m_nvic_can_take_pending_exception(void *opaque) |
401 | { | |
402 | NVICState *s = opaque; | |
403 | ||
404 | return nvic_exec_prio(s) > nvic_pending_prio(s); | |
405 | } | |
406 | ||
42a6686b PM |
407 | int armv7m_nvic_raw_execution_priority(void *opaque) |
408 | { | |
409 | NVICState *s = opaque; | |
410 | ||
411 | return s->exception_prio; | |
412 | } | |
413 | ||
e6a0d350 PM |
414 | /* caller must call nvic_irq_update() after this. |
415 | * secure indicates the bank to use for banked exceptions (we assert if | |
416 | * we are passed secure=true for a non-banked exception). | |
417 | */ | |
418 | static void set_prio(NVICState *s, unsigned irq, bool secure, uint8_t prio) | |
da6d674e MD |
419 | { |
420 | assert(irq > ARMV7M_EXCP_NMI); /* only use for configurable prios */ | |
421 | assert(irq < s->num_irq); | |
422 | ||
e6a0d350 PM |
423 | if (secure) { |
424 | assert(exc_is_banked(irq)); | |
425 | s->sec_vectors[irq].prio = prio; | |
426 | } else { | |
427 | s->vectors[irq].prio = prio; | |
428 | } | |
429 | ||
430 | trace_nvic_set_prio(irq, secure, prio); | |
431 | } | |
432 | ||
433 | /* Return the current raw priority register value. | |
434 | * secure indicates the bank to use for banked exceptions (we assert if | |
435 | * we are passed secure=true for a non-banked exception). | |
436 | */ | |
437 | static int get_prio(NVICState *s, unsigned irq, bool secure) | |
438 | { | |
439 | assert(irq > ARMV7M_EXCP_NMI); /* only use for configurable prios */ | |
440 | assert(irq < s->num_irq); | |
da6d674e | 441 | |
e6a0d350 PM |
442 | if (secure) { |
443 | assert(exc_is_banked(irq)); | |
444 | return s->sec_vectors[irq].prio; | |
445 | } else { | |
446 | return s->vectors[irq].prio; | |
447 | } | |
da6d674e MD |
448 | } |
449 | ||
450 | /* Recompute state and assert irq line accordingly. | |
451 | * Must be called after changes to: | |
452 | * vec->active, vec->enabled, vec->pending or vec->prio for any vector | |
453 | * prigroup | |
454 | */ | |
455 | static void nvic_irq_update(NVICState *s) | |
456 | { | |
457 | int lvl; | |
458 | int pend_prio; | |
459 | ||
460 | nvic_recompute_state(s); | |
461 | pend_prio = nvic_pending_prio(s); | |
462 | ||
463 | /* Raise NVIC output if this IRQ would be taken, except that we | |
464 | * ignore the effects of the BASEPRI, FAULTMASK and PRIMASK (which | |
465 | * will be checked for in arm_v7m_cpu_exec_interrupt()); changes | |
466 | * to those CPU registers don't cause us to recalculate the NVIC | |
467 | * pending info. | |
468 | */ | |
469 | lvl = (pend_prio < s->exception_prio); | |
470 | trace_nvic_irq_update(s->vectpending, pend_prio, s->exception_prio, lvl); | |
471 | qemu_set_irq(s->excpout, lvl); | |
472 | } | |
473 | ||
2fb50a33 PM |
474 | /** |
475 | * armv7m_nvic_clear_pending: mark the specified exception as not pending | |
476 | * @opaque: the NVIC | |
477 | * @irq: the exception number to mark as not pending | |
478 | * @secure: false for non-banked exceptions or for the nonsecure | |
479 | * version of a banked exception, true for the secure version of a banked | |
480 | * exception. | |
481 | * | |
482 | * Marks the specified exception as not pending. Note that we will assert() | |
483 | * if @secure is true and @irq does not specify one of the fixed set | |
484 | * of architecturally banked exceptions. | |
485 | */ | |
486 | static void armv7m_nvic_clear_pending(void *opaque, int irq, bool secure) | |
da6d674e MD |
487 | { |
488 | NVICState *s = (NVICState *)opaque; | |
489 | VecInfo *vec; | |
490 | ||
491 | assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); | |
492 | ||
2fb50a33 PM |
493 | if (secure) { |
494 | assert(exc_is_banked(irq)); | |
495 | vec = &s->sec_vectors[irq]; | |
496 | } else { | |
497 | vec = &s->vectors[irq]; | |
498 | } | |
499 | trace_nvic_clear_pending(irq, secure, vec->enabled, vec->prio); | |
da6d674e MD |
500 | if (vec->pending) { |
501 | vec->pending = 0; | |
502 | nvic_irq_update(s); | |
503 | } | |
504 | } | |
505 | ||
5ede82b8 PM |
506 | static void do_armv7m_nvic_set_pending(void *opaque, int irq, bool secure, |
507 | bool derived) | |
9ee6e8bb | 508 | { |
5ede82b8 PM |
509 | /* Pend an exception, including possibly escalating it to HardFault. |
510 | * | |
511 | * This function handles both "normal" pending of interrupts and | |
512 | * exceptions, and also derived exceptions (ones which occur as | |
513 | * a result of trying to take some other exception). | |
514 | * | |
515 | * If derived == true, the caller guarantees that we are part way through | |
516 | * trying to take an exception (but have not yet called | |
517 | * armv7m_nvic_acknowledge_irq() to make it active), and so: | |
518 | * - s->vectpending is the "original exception" we were trying to take | |
519 | * - irq is the "derived exception" | |
520 | * - nvic_exec_prio(s) gives the priority before exception entry | |
521 | * Here we handle the prioritization logic which the pseudocode puts | |
522 | * in the DerivedLateArrival() function. | |
523 | */ | |
524 | ||
f797c075 | 525 | NVICState *s = (NVICState *)opaque; |
2fb50a33 | 526 | bool banked = exc_is_banked(irq); |
da6d674e | 527 | VecInfo *vec; |
1a5182c0 | 528 | bool targets_secure; |
da6d674e MD |
529 | |
530 | assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); | |
2fb50a33 | 531 | assert(!secure || banked); |
da6d674e | 532 | |
2fb50a33 | 533 | vec = (banked && secure) ? &s->sec_vectors[irq] : &s->vectors[irq]; |
a73c98e1 | 534 | |
1a5182c0 PM |
535 | targets_secure = banked ? secure : exc_targets_secure(s, irq); |
536 | ||
537 | trace_nvic_set_pending(irq, secure, targets_secure, | |
538 | derived, vec->enabled, vec->prio); | |
5ede82b8 PM |
539 | |
540 | if (derived) { | |
541 | /* Derived exceptions are always synchronous. */ | |
542 | assert(irq >= ARMV7M_EXCP_HARD && irq < ARMV7M_EXCP_PENDSV); | |
543 | ||
544 | if (irq == ARMV7M_EXCP_DEBUG && | |
545 | exc_group_prio(s, vec->prio, secure) >= nvic_exec_prio(s)) { | |
546 | /* DebugMonitorFault, but its priority is lower than the | |
547 | * preempted exception priority: just ignore it. | |
548 | */ | |
549 | return; | |
550 | } | |
551 | ||
552 | if (irq == ARMV7M_EXCP_HARD && vec->prio >= s->vectpending_prio) { | |
553 | /* If this is a terminal exception (one which means we cannot | |
554 | * take the original exception, like a failure to read its | |
555 | * vector table entry), then we must take the derived exception. | |
556 | * If the derived exception can't take priority over the | |
557 | * original exception, then we go into Lockup. | |
558 | * | |
559 | * For QEMU, we rely on the fact that a derived exception is | |
560 | * terminal if and only if it's reported to us as HardFault, | |
561 | * which saves having to have an extra argument is_terminal | |
562 | * that we'd only use in one place. | |
563 | */ | |
564 | cpu_abort(&s->cpu->parent_obj, | |
565 | "Lockup: can't take terminal derived exception " | |
566 | "(original exception priority %d)\n", | |
567 | s->vectpending_prio); | |
568 | } | |
569 | /* We now continue with the same code as for a normal pending | |
570 | * exception, which will cause us to pend the derived exception. | |
571 | * We'll then take either the original or the derived exception | |
572 | * based on which is higher priority by the usual mechanism | |
573 | * for selecting the highest priority pending interrupt. | |
574 | */ | |
575 | } | |
a73c98e1 MD |
576 | |
577 | if (irq >= ARMV7M_EXCP_HARD && irq < ARMV7M_EXCP_PENDSV) { | |
578 | /* If a synchronous exception is pending then it may be | |
579 | * escalated to HardFault if: | |
580 | * * it is equal or lower priority to current execution | |
581 | * * it is disabled | |
582 | * (ie we need to take it immediately but we can't do so). | |
583 | * Asynchronous exceptions (and interrupts) simply remain pending. | |
584 | * | |
585 | * For QEMU, we don't have any imprecise (asynchronous) faults, | |
586 | * so we can assume that PREFETCH_ABORT and DATA_ABORT are always | |
587 | * synchronous. | |
588 | * Debug exceptions are awkward because only Debug exceptions | |
589 | * resulting from the BKPT instruction should be escalated, | |
590 | * but we don't currently implement any Debug exceptions other | |
591 | * than those that result from BKPT, so we treat all debug exceptions | |
592 | * as needing escalation. | |
593 | * | |
594 | * This all means we can identify whether to escalate based only on | |
595 | * the exception number and don't (yet) need the caller to explicitly | |
596 | * tell us whether this exception is synchronous or not. | |
597 | */ | |
598 | int running = nvic_exec_prio(s); | |
599 | bool escalate = false; | |
600 | ||
80ac2390 | 601 | if (exc_group_prio(s, vec->prio, secure) >= running) { |
a73c98e1 MD |
602 | trace_nvic_escalate_prio(irq, vec->prio, running); |
603 | escalate = true; | |
604 | } else if (!vec->enabled) { | |
605 | trace_nvic_escalate_disabled(irq); | |
606 | escalate = true; | |
607 | } | |
608 | ||
609 | if (escalate) { | |
a73c98e1 | 610 | |
94a34abe | 611 | /* We need to escalate this exception to a synchronous HardFault. |
2fb50a33 PM |
612 | * If BFHFNMINS is set then we escalate to the banked HF for |
613 | * the target security state of the original exception; otherwise | |
614 | * we take a Secure HardFault. | |
615 | */ | |
a73c98e1 | 616 | irq = ARMV7M_EXCP_HARD; |
2fb50a33 | 617 | if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY) && |
1a5182c0 | 618 | (targets_secure || |
2fb50a33 PM |
619 | !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK))) { |
620 | vec = &s->sec_vectors[irq]; | |
621 | } else { | |
622 | vec = &s->vectors[irq]; | |
623 | } | |
94a34abe PM |
624 | if (running <= vec->prio) { |
625 | /* We want to escalate to HardFault but we can't take the | |
626 | * synchronous HardFault at this point either. This is a | |
627 | * Lockup condition due to a guest bug. We don't model | |
628 | * Lockup, so report via cpu_abort() instead. | |
629 | */ | |
630 | cpu_abort(&s->cpu->parent_obj, | |
631 | "Lockup: can't escalate %d to HardFault " | |
632 | "(current priority %d)\n", irq, running); | |
633 | } | |
634 | ||
2fb50a33 | 635 | /* HF may be banked but there is only one shared HFSR */ |
a73c98e1 MD |
636 | s->cpu->env.v7m.hfsr |= R_V7M_HFSR_FORCED_MASK; |
637 | } | |
638 | } | |
639 | ||
da6d674e MD |
640 | if (!vec->pending) { |
641 | vec->pending = 1; | |
642 | nvic_irq_update(s); | |
643 | } | |
9ee6e8bb PB |
644 | } |
645 | ||
5ede82b8 PM |
646 | void armv7m_nvic_set_pending(void *opaque, int irq, bool secure) |
647 | { | |
648 | do_armv7m_nvic_set_pending(opaque, irq, secure, false); | |
649 | } | |
650 | ||
651 | void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure) | |
652 | { | |
653 | do_armv7m_nvic_set_pending(opaque, irq, secure, true); | |
654 | } | |
655 | ||
9ee6e8bb | 656 | /* Make pending IRQ active. */ |
6c948518 | 657 | void armv7m_nvic_acknowledge_irq(void *opaque) |
9ee6e8bb | 658 | { |
f797c075 | 659 | NVICState *s = (NVICState *)opaque; |
da6d674e MD |
660 | CPUARMState *env = &s->cpu->env; |
661 | const int pending = s->vectpending; | |
662 | const int running = nvic_exec_prio(s); | |
da6d674e MD |
663 | VecInfo *vec; |
664 | ||
665 | assert(pending > ARMV7M_EXCP_RESET && pending < s->num_irq); | |
666 | ||
5cb18069 PM |
667 | if (s->vectpending_is_s_banked) { |
668 | vec = &s->sec_vectors[pending]; | |
5cb18069 PM |
669 | } else { |
670 | vec = &s->vectors[pending]; | |
5cb18069 | 671 | } |
da6d674e MD |
672 | |
673 | assert(vec->enabled); | |
674 | assert(vec->pending); | |
675 | ||
5255fcf8 | 676 | assert(s->vectpending_prio < running); |
da6d674e | 677 | |
6c948518 | 678 | trace_nvic_acknowledge_irq(pending, s->vectpending_prio); |
da6d674e MD |
679 | |
680 | vec->active = 1; | |
681 | vec->pending = 0; | |
682 | ||
de2db7ec | 683 | write_v7m_exception(env, s->vectpending); |
da6d674e MD |
684 | |
685 | nvic_irq_update(s); | |
6c948518 PM |
686 | } |
687 | ||
688 | void armv7m_nvic_get_pending_irq_info(void *opaque, | |
689 | int *pirq, bool *ptargets_secure) | |
690 | { | |
691 | NVICState *s = (NVICState *)opaque; | |
692 | const int pending = s->vectpending; | |
693 | bool targets_secure; | |
694 | ||
695 | assert(pending > ARMV7M_EXCP_RESET && pending < s->num_irq); | |
696 | ||
697 | if (s->vectpending_is_s_banked) { | |
698 | targets_secure = true; | |
699 | } else { | |
700 | targets_secure = !exc_is_banked(pending) && | |
701 | exc_targets_secure(s, pending); | |
702 | } | |
703 | ||
704 | trace_nvic_get_pending_irq_info(pending, targets_secure); | |
5cb18069 | 705 | |
6c948518 PM |
706 | *ptargets_secure = targets_secure; |
707 | *pirq = pending; | |
9ee6e8bb PB |
708 | } |
709 | ||
5cb18069 | 710 | int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure) |
9ee6e8bb | 711 | { |
f797c075 | 712 | NVICState *s = (NVICState *)opaque; |
da6d674e | 713 | VecInfo *vec; |
aa488fe3 | 714 | int ret; |
da6d674e MD |
715 | |
716 | assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); | |
717 | ||
5cb18069 PM |
718 | if (secure && exc_is_banked(irq)) { |
719 | vec = &s->sec_vectors[irq]; | |
720 | } else { | |
721 | vec = &s->vectors[irq]; | |
722 | } | |
da6d674e | 723 | |
5cb18069 | 724 | trace_nvic_complete_irq(irq, secure); |
da6d674e | 725 | |
aa488fe3 PM |
726 | if (!vec->active) { |
727 | /* Tell the caller this was an illegal exception return */ | |
728 | return -1; | |
729 | } | |
730 | ||
731 | ret = nvic_rettobase(s); | |
732 | ||
da6d674e MD |
733 | vec->active = 0; |
734 | if (vec->level) { | |
735 | /* Re-pend the exception if it's still held high; only | |
736 | * happens for extenal IRQs | |
737 | */ | |
738 | assert(irq >= NVIC_FIRST_IRQ); | |
739 | vec->pending = 1; | |
740 | } | |
741 | ||
742 | nvic_irq_update(s); | |
aa488fe3 PM |
743 | |
744 | return ret; | |
da6d674e MD |
745 | } |
746 | ||
747 | /* callback when external interrupt line is changed */ | |
748 | static void set_irq_level(void *opaque, int n, int level) | |
749 | { | |
750 | NVICState *s = opaque; | |
751 | VecInfo *vec; | |
752 | ||
753 | n += NVIC_FIRST_IRQ; | |
754 | ||
755 | assert(n >= NVIC_FIRST_IRQ && n < s->num_irq); | |
756 | ||
757 | trace_nvic_set_irq_level(n, level); | |
758 | ||
759 | /* The pending status of an external interrupt is | |
760 | * latched on rising edge and exception handler return. | |
761 | * | |
762 | * Pulsing the IRQ will always run the handler | |
763 | * once, and the handler will re-run until the | |
764 | * level is low when the handler completes. | |
765 | */ | |
766 | vec = &s->vectors[n]; | |
767 | if (level != vec->level) { | |
768 | vec->level = level; | |
769 | if (level) { | |
2fb50a33 | 770 | armv7m_nvic_set_pending(s, n, false); |
da6d674e MD |
771 | } |
772 | } | |
9ee6e8bb PB |
773 | } |
774 | ||
45db7ba6 | 775 | static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) |
9ee6e8bb | 776 | { |
d713ea6c | 777 | ARMCPU *cpu = s->cpu; |
9ee6e8bb | 778 | uint32_t val; |
9ee6e8bb PB |
779 | |
780 | switch (offset) { | |
781 | case 4: /* Interrupt Control Type. */ | |
da6d674e | 782 | return ((s->num_irq - NVIC_FIRST_IRQ) / 32) - 1; |
ae7c5c85 PM |
783 | case 0xc: /* CPPWR */ |
784 | if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { | |
785 | goto bad_offset; | |
786 | } | |
787 | /* We make the IMPDEF choice that nothing can ever go into a | |
788 | * non-retentive power state, which allows us to RAZ/WI this. | |
789 | */ | |
790 | return 0; | |
e1be0a57 PM |
791 | case 0x380 ... 0x3bf: /* NVIC_ITNS<n> */ |
792 | { | |
cf5f7937 | 793 | int startvec = 8 * (offset - 0x380) + NVIC_FIRST_IRQ; |
e1be0a57 PM |
794 | int i; |
795 | ||
796 | if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { | |
797 | goto bad_offset; | |
798 | } | |
799 | if (!attrs.secure) { | |
800 | return 0; | |
801 | } | |
802 | val = 0; | |
803 | for (i = 0; i < 32 && startvec + i < s->num_irq; i++) { | |
804 | if (s->itns[startvec + i]) { | |
805 | val |= (1 << i); | |
806 | } | |
807 | } | |
808 | return val; | |
809 | } | |
9ee6e8bb | 810 | case 0xd00: /* CPUID Base. */ |
e3da9921 | 811 | return cpu->midr; |
3f1e0eb7 | 812 | case 0xd04: /* Interrupt Control State (ICSR) */ |
9ee6e8bb | 813 | /* VECTACTIVE */ |
b06c262b | 814 | val = cpu->env.v7m.exception; |
9ee6e8bb | 815 | /* VECTPENDING */ |
da6d674e MD |
816 | val |= (s->vectpending & 0xff) << 12; |
817 | /* ISRPENDING - set if any external IRQ is pending */ | |
818 | if (nvic_isrpending(s)) { | |
819 | val |= (1 << 22); | |
820 | } | |
821 | /* RETTOBASE - set if only one handler is active */ | |
822 | if (nvic_rettobase(s)) { | |
823 | val |= (1 << 11); | |
9ee6e8bb | 824 | } |
3f1e0eb7 PM |
825 | if (attrs.secure) { |
826 | /* PENDSTSET */ | |
827 | if (s->sec_vectors[ARMV7M_EXCP_SYSTICK].pending) { | |
828 | val |= (1 << 26); | |
829 | } | |
830 | /* PENDSVSET */ | |
831 | if (s->sec_vectors[ARMV7M_EXCP_PENDSV].pending) { | |
832 | val |= (1 << 28); | |
833 | } | |
834 | } else { | |
835 | /* PENDSTSET */ | |
836 | if (s->vectors[ARMV7M_EXCP_SYSTICK].pending) { | |
837 | val |= (1 << 26); | |
838 | } | |
839 | /* PENDSVSET */ | |
840 | if (s->vectors[ARMV7M_EXCP_PENDSV].pending) { | |
841 | val |= (1 << 28); | |
842 | } | |
da6d674e | 843 | } |
9ee6e8bb | 844 | /* NMIPENDSET */ |
4f2eff36 PM |
845 | if ((attrs.secure || (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) |
846 | && s->vectors[ARMV7M_EXCP_NMI].pending) { | |
9ee6e8bb | 847 | val |= (1 << 31); |
da6d674e | 848 | } |
3f1e0eb7 PM |
849 | /* ISRPREEMPT: RES0 when halting debug not implemented */ |
850 | /* STTNS: RES0 for the Main Extension */ | |
9ee6e8bb PB |
851 | return val; |
852 | case 0xd08: /* Vector Table Offset. */ | |
45db7ba6 | 853 | return cpu->env.v7m.vecbase[attrs.secure]; |
3b2e9344 PM |
854 | case 0xd0c: /* Application Interrupt/Reset Control (AIRCR) */ |
855 | val = 0xfa050000 | (s->prigroup[attrs.secure] << 8); | |
856 | if (attrs.secure) { | |
857 | /* s->aircr stores PRIS, BFHFNMINS, SYSRESETREQS */ | |
858 | val |= cpu->env.v7m.aircr; | |
859 | } else { | |
860 | if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { | |
861 | /* BFHFNMINS is R/O from NS; other bits are RAZ/WI. If | |
862 | * security isn't supported then BFHFNMINS is RAO (and | |
863 | * the bit in env.v7m.aircr is always set). | |
864 | */ | |
865 | val |= cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK; | |
866 | } | |
867 | } | |
868 | return val; | |
9ee6e8bb | 869 | case 0xd10: /* System Control. */ |
7c9140af JS |
870 | if (!arm_feature(&cpu->env, ARM_FEATURE_V7)) { |
871 | goto bad_offset; | |
872 | } | |
24ac0fb1 | 873 | return cpu->env.v7m.scr[attrs.secure]; |
9ee6e8bb | 874 | case 0xd14: /* Configuration Control. */ |
9d40cd8a PM |
875 | /* The BFHFNMIGN bit is the only non-banked bit; we |
876 | * keep it in the non-secure copy of the register. | |
877 | */ | |
878 | val = cpu->env.v7m.ccr[attrs.secure]; | |
879 | val |= cpu->env.v7m.ccr[M_REG_NS] & R_V7M_CCR_BFHFNMIGN_MASK; | |
880 | return val; | |
437d59c1 | 881 | case 0xd24: /* System Handler Control and State (SHCSR) */ |
9ee6e8bb | 882 | val = 0; |
437d59c1 PM |
883 | if (attrs.secure) { |
884 | if (s->sec_vectors[ARMV7M_EXCP_MEM].active) { | |
885 | val |= (1 << 0); | |
886 | } | |
887 | if (s->sec_vectors[ARMV7M_EXCP_HARD].active) { | |
888 | val |= (1 << 2); | |
889 | } | |
890 | if (s->sec_vectors[ARMV7M_EXCP_USAGE].active) { | |
891 | val |= (1 << 3); | |
892 | } | |
893 | if (s->sec_vectors[ARMV7M_EXCP_SVC].active) { | |
894 | val |= (1 << 7); | |
895 | } | |
896 | if (s->sec_vectors[ARMV7M_EXCP_PENDSV].active) { | |
897 | val |= (1 << 10); | |
898 | } | |
899 | if (s->sec_vectors[ARMV7M_EXCP_SYSTICK].active) { | |
900 | val |= (1 << 11); | |
901 | } | |
902 | if (s->sec_vectors[ARMV7M_EXCP_USAGE].pending) { | |
903 | val |= (1 << 12); | |
904 | } | |
905 | if (s->sec_vectors[ARMV7M_EXCP_MEM].pending) { | |
906 | val |= (1 << 13); | |
907 | } | |
908 | if (s->sec_vectors[ARMV7M_EXCP_SVC].pending) { | |
909 | val |= (1 << 15); | |
910 | } | |
911 | if (s->sec_vectors[ARMV7M_EXCP_MEM].enabled) { | |
912 | val |= (1 << 16); | |
913 | } | |
914 | if (s->sec_vectors[ARMV7M_EXCP_USAGE].enabled) { | |
915 | val |= (1 << 18); | |
916 | } | |
917 | if (s->sec_vectors[ARMV7M_EXCP_HARD].pending) { | |
918 | val |= (1 << 21); | |
919 | } | |
920 | /* SecureFault is not banked but is always RAZ/WI to NS */ | |
921 | if (s->vectors[ARMV7M_EXCP_SECURE].active) { | |
922 | val |= (1 << 4); | |
923 | } | |
924 | if (s->vectors[ARMV7M_EXCP_SECURE].enabled) { | |
925 | val |= (1 << 19); | |
926 | } | |
927 | if (s->vectors[ARMV7M_EXCP_SECURE].pending) { | |
928 | val |= (1 << 20); | |
929 | } | |
930 | } else { | |
931 | if (s->vectors[ARMV7M_EXCP_MEM].active) { | |
932 | val |= (1 << 0); | |
933 | } | |
934 | if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { | |
935 | /* HARDFAULTACT, HARDFAULTPENDED not present in v7M */ | |
936 | if (s->vectors[ARMV7M_EXCP_HARD].active) { | |
937 | val |= (1 << 2); | |
938 | } | |
939 | if (s->vectors[ARMV7M_EXCP_HARD].pending) { | |
940 | val |= (1 << 21); | |
941 | } | |
942 | } | |
943 | if (s->vectors[ARMV7M_EXCP_USAGE].active) { | |
944 | val |= (1 << 3); | |
945 | } | |
946 | if (s->vectors[ARMV7M_EXCP_SVC].active) { | |
947 | val |= (1 << 7); | |
948 | } | |
949 | if (s->vectors[ARMV7M_EXCP_PENDSV].active) { | |
950 | val |= (1 << 10); | |
951 | } | |
952 | if (s->vectors[ARMV7M_EXCP_SYSTICK].active) { | |
953 | val |= (1 << 11); | |
954 | } | |
955 | if (s->vectors[ARMV7M_EXCP_USAGE].pending) { | |
956 | val |= (1 << 12); | |
957 | } | |
958 | if (s->vectors[ARMV7M_EXCP_MEM].pending) { | |
959 | val |= (1 << 13); | |
960 | } | |
961 | if (s->vectors[ARMV7M_EXCP_SVC].pending) { | |
962 | val |= (1 << 15); | |
963 | } | |
964 | if (s->vectors[ARMV7M_EXCP_MEM].enabled) { | |
965 | val |= (1 << 16); | |
966 | } | |
967 | if (s->vectors[ARMV7M_EXCP_USAGE].enabled) { | |
968 | val |= (1 << 18); | |
969 | } | |
da6d674e | 970 | } |
437d59c1 PM |
971 | if (attrs.secure || (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) { |
972 | if (s->vectors[ARMV7M_EXCP_BUS].active) { | |
973 | val |= (1 << 1); | |
974 | } | |
975 | if (s->vectors[ARMV7M_EXCP_BUS].pending) { | |
976 | val |= (1 << 14); | |
977 | } | |
978 | if (s->vectors[ARMV7M_EXCP_BUS].enabled) { | |
979 | val |= (1 << 17); | |
980 | } | |
981 | if (arm_feature(&cpu->env, ARM_FEATURE_V8) && | |
982 | s->vectors[ARMV7M_EXCP_NMI].active) { | |
983 | /* NMIACT is not present in v7M */ | |
984 | val |= (1 << 5); | |
985 | } | |
da6d674e | 986 | } |
437d59c1 PM |
987 | |
988 | /* TODO: this is RAZ/WI from NS if DEMCR.SDME is set */ | |
da6d674e MD |
989 | if (s->vectors[ARMV7M_EXCP_DEBUG].active) { |
990 | val |= (1 << 8); | |
991 | } | |
9ee6e8bb | 992 | return val; |
9ee6e8bb | 993 | case 0xd2c: /* Hard Fault Status. */ |
7c9140af JS |
994 | if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { |
995 | goto bad_offset; | |
996 | } | |
e6b33209 | 997 | return cpu->env.v7m.hfsr; |
9ee6e8bb | 998 | case 0xd30: /* Debug Fault Status. */ |
e6b33209 MD |
999 | return cpu->env.v7m.dfsr; |
1000 | case 0xd34: /* MMFAR MemManage Fault Address */ | |
7c9140af JS |
1001 | if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { |
1002 | goto bad_offset; | |
1003 | } | |
c51a5cfc | 1004 | return cpu->env.v7m.mmfar[attrs.secure]; |
9ee6e8bb | 1005 | case 0xd38: /* Bus Fault Address. */ |
7c9140af JS |
1006 | if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { |
1007 | goto bad_offset; | |
1008 | } | |
e6b33209 | 1009 | return cpu->env.v7m.bfar; |
9ee6e8bb PB |
1010 | case 0xd3c: /* Aux Fault Status. */ |
1011 | /* TODO: Implement fault status registers. */ | |
e6b33209 MD |
1012 | qemu_log_mask(LOG_UNIMP, |
1013 | "Aux Fault status registers unimplemented\n"); | |
e72e3ffc | 1014 | return 0; |
9ee6e8bb | 1015 | case 0xd40: /* PFR0. */ |
5a53e2c1 PM |
1016 | return cpu->id_pfr0; |
1017 | case 0xd44: /* PFR1. */ | |
1018 | return cpu->id_pfr1; | |
9ee6e8bb | 1019 | case 0xd48: /* DFR0. */ |
5a53e2c1 | 1020 | return cpu->id_dfr0; |
9ee6e8bb | 1021 | case 0xd4c: /* AFR0. */ |
5a53e2c1 | 1022 | return cpu->id_afr0; |
9ee6e8bb | 1023 | case 0xd50: /* MMFR0. */ |
5a53e2c1 | 1024 | return cpu->id_mmfr0; |
9ee6e8bb | 1025 | case 0xd54: /* MMFR1. */ |
5a53e2c1 | 1026 | return cpu->id_mmfr1; |
9ee6e8bb | 1027 | case 0xd58: /* MMFR2. */ |
5a53e2c1 | 1028 | return cpu->id_mmfr2; |
9ee6e8bb | 1029 | case 0xd5c: /* MMFR3. */ |
5a53e2c1 | 1030 | return cpu->id_mmfr3; |
9ee6e8bb | 1031 | case 0xd60: /* ISAR0. */ |
5a53e2c1 | 1032 | return cpu->id_isar0; |
9ee6e8bb | 1033 | case 0xd64: /* ISAR1. */ |
5a53e2c1 | 1034 | return cpu->id_isar1; |
9ee6e8bb | 1035 | case 0xd68: /* ISAR2. */ |
5a53e2c1 | 1036 | return cpu->id_isar2; |
9ee6e8bb | 1037 | case 0xd6c: /* ISAR3. */ |
5a53e2c1 | 1038 | return cpu->id_isar3; |
9ee6e8bb | 1039 | case 0xd70: /* ISAR4. */ |
5a53e2c1 PM |
1040 | return cpu->id_isar4; |
1041 | case 0xd74: /* ISAR5. */ | |
1042 | return cpu->id_isar5; | |
43bbce7f PM |
1043 | case 0xd78: /* CLIDR */ |
1044 | return cpu->clidr; | |
1045 | case 0xd7c: /* CTR */ | |
1046 | return cpu->ctr; | |
1047 | case 0xd80: /* CSSIDR */ | |
1048 | { | |
1049 | int idx = cpu->env.v7m.csselr[attrs.secure] & R_V7M_CSSELR_INDEX_MASK; | |
1050 | return cpu->ccsidr[idx]; | |
1051 | } | |
1052 | case 0xd84: /* CSSELR */ | |
1053 | return cpu->env.v7m.csselr[attrs.secure]; | |
9ee6e8bb | 1054 | /* TODO: Implement debug registers. */ |
29c483a5 MD |
1055 | case 0xd90: /* MPU_TYPE */ |
1056 | /* Unified MPU; if the MPU is not present this value is zero */ | |
1057 | return cpu->pmsav7_dregion << 8; | |
1058 | break; | |
1059 | case 0xd94: /* MPU_CTRL */ | |
ecf5e8ea | 1060 | return cpu->env.v7m.mpu_ctrl[attrs.secure]; |
29c483a5 | 1061 | case 0xd98: /* MPU_RNR */ |
1bc04a88 | 1062 | return cpu->env.pmsav7.rnr[attrs.secure]; |
29c483a5 MD |
1063 | case 0xd9c: /* MPU_RBAR */ |
1064 | case 0xda4: /* MPU_RBAR_A1 */ | |
1065 | case 0xdac: /* MPU_RBAR_A2 */ | |
1066 | case 0xdb4: /* MPU_RBAR_A3 */ | |
1067 | { | |
1bc04a88 | 1068 | int region = cpu->env.pmsav7.rnr[attrs.secure]; |
29c483a5 | 1069 | |
0e1a46bb PM |
1070 | if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { |
1071 | /* PMSAv8M handling of the aliases is different from v7M: | |
1072 | * aliases A1, A2, A3 override the low two bits of the region | |
1073 | * number in MPU_RNR, and there is no 'region' field in the | |
1074 | * RBAR register. | |
1075 | */ | |
1076 | int aliasno = (offset - 0xd9c) / 8; /* 0..3 */ | |
1077 | if (aliasno) { | |
1078 | region = deposit32(region, 0, 2, aliasno); | |
1079 | } | |
1080 | if (region >= cpu->pmsav7_dregion) { | |
1081 | return 0; | |
1082 | } | |
62c58ee0 | 1083 | return cpu->env.pmsav8.rbar[attrs.secure][region]; |
0e1a46bb PM |
1084 | } |
1085 | ||
29c483a5 MD |
1086 | if (region >= cpu->pmsav7_dregion) { |
1087 | return 0; | |
1088 | } | |
2b75ef01 | 1089 | return (cpu->env.pmsav7.drbar[region] & ~0x1f) | (region & 0xf); |
29c483a5 | 1090 | } |
0e1a46bb PM |
1091 | case 0xda0: /* MPU_RASR (v7M), MPU_RLAR (v8M) */ |
1092 | case 0xda8: /* MPU_RASR_A1 (v7M), MPU_RLAR_A1 (v8M) */ | |
1093 | case 0xdb0: /* MPU_RASR_A2 (v7M), MPU_RLAR_A2 (v8M) */ | |
1094 | case 0xdb8: /* MPU_RASR_A3 (v7M), MPU_RLAR_A3 (v8M) */ | |
29c483a5 | 1095 | { |
1bc04a88 | 1096 | int region = cpu->env.pmsav7.rnr[attrs.secure]; |
29c483a5 | 1097 | |
0e1a46bb PM |
1098 | if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { |
1099 | /* PMSAv8M handling of the aliases is different from v7M: | |
1100 | * aliases A1, A2, A3 override the low two bits of the region | |
1101 | * number in MPU_RNR. | |
1102 | */ | |
1103 | int aliasno = (offset - 0xda0) / 8; /* 0..3 */ | |
1104 | if (aliasno) { | |
1105 | region = deposit32(region, 0, 2, aliasno); | |
1106 | } | |
1107 | if (region >= cpu->pmsav7_dregion) { | |
1108 | return 0; | |
1109 | } | |
62c58ee0 | 1110 | return cpu->env.pmsav8.rlar[attrs.secure][region]; |
0e1a46bb PM |
1111 | } |
1112 | ||
29c483a5 MD |
1113 | if (region >= cpu->pmsav7_dregion) { |
1114 | return 0; | |
1115 | } | |
1116 | return ((cpu->env.pmsav7.dracr[region] & 0xffff) << 16) | | |
1117 | (cpu->env.pmsav7.drsr[region] & 0xffff); | |
1118 | } | |
0e1a46bb PM |
1119 | case 0xdc0: /* MPU_MAIR0 */ |
1120 | if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { | |
1121 | goto bad_offset; | |
1122 | } | |
4125e6fe | 1123 | return cpu->env.pmsav8.mair0[attrs.secure]; |
0e1a46bb PM |
1124 | case 0xdc4: /* MPU_MAIR1 */ |
1125 | if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { | |
1126 | goto bad_offset; | |
1127 | } | |
4125e6fe | 1128 | return cpu->env.pmsav8.mair1[attrs.secure]; |
9901c576 PM |
1129 | case 0xdd0: /* SAU_CTRL */ |
1130 | if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { | |
1131 | goto bad_offset; | |
1132 | } | |
1133 | if (!attrs.secure) { | |
1134 | return 0; | |
1135 | } | |
1136 | return cpu->env.sau.ctrl; | |
1137 | case 0xdd4: /* SAU_TYPE */ | |
1138 | if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { | |
1139 | goto bad_offset; | |
1140 | } | |
1141 | if (!attrs.secure) { | |
1142 | return 0; | |
1143 | } | |
1144 | return cpu->sau_sregion; | |
1145 | case 0xdd8: /* SAU_RNR */ | |
1146 | if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { | |
1147 | goto bad_offset; | |
1148 | } | |
1149 | if (!attrs.secure) { | |
1150 | return 0; | |
1151 | } | |
1152 | return cpu->env.sau.rnr; | |
1153 | case 0xddc: /* SAU_RBAR */ | |
1154 | { | |
1155 | int region = cpu->env.sau.rnr; | |
1156 | ||
1157 | if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { | |
1158 | goto bad_offset; | |
1159 | } | |
1160 | if (!attrs.secure) { | |
1161 | return 0; | |
1162 | } | |
1163 | if (region >= cpu->sau_sregion) { | |
1164 | return 0; | |
1165 | } | |
1166 | return cpu->env.sau.rbar[region]; | |
1167 | } | |
1168 | case 0xde0: /* SAU_RLAR */ | |
1169 | { | |
1170 | int region = cpu->env.sau.rnr; | |
1171 | ||
1172 | if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { | |
1173 | goto bad_offset; | |
1174 | } | |
1175 | if (!attrs.secure) { | |
1176 | return 0; | |
1177 | } | |
1178 | if (region >= cpu->sau_sregion) { | |
1179 | return 0; | |
1180 | } | |
1181 | return cpu->env.sau.rlar[region]; | |
1182 | } | |
bed079da PM |
1183 | case 0xde4: /* SFSR */ |
1184 | if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { | |
1185 | goto bad_offset; | |
1186 | } | |
1187 | if (!attrs.secure) { | |
1188 | return 0; | |
1189 | } | |
1190 | return cpu->env.v7m.sfsr; | |
1191 | case 0xde8: /* SFAR */ | |
1192 | if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { | |
1193 | goto bad_offset; | |
1194 | } | |
1195 | if (!attrs.secure) { | |
1196 | return 0; | |
1197 | } | |
1198 | return cpu->env.v7m.sfar; | |
9ee6e8bb | 1199 | default: |
0e1a46bb | 1200 | bad_offset: |
e72e3ffc PM |
1201 | qemu_log_mask(LOG_GUEST_ERROR, "NVIC: Bad read offset 0x%x\n", offset); |
1202 | return 0; | |
9ee6e8bb PB |
1203 | } |
1204 | } | |
1205 | ||
45db7ba6 PM |
1206 | static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, |
1207 | MemTxAttrs attrs) | |
9ee6e8bb | 1208 | { |
d713ea6c | 1209 | ARMCPU *cpu = s->cpu; |
ff68dacb | 1210 | |
9ee6e8bb | 1211 | switch (offset) { |
ae7c5c85 PM |
1212 | case 0xc: /* CPPWR */ |
1213 | if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { | |
1214 | goto bad_offset; | |
1215 | } | |
1216 | /* Make the IMPDEF choice to RAZ/WI this. */ | |
1217 | break; | |
e1be0a57 PM |
1218 | case 0x380 ... 0x3bf: /* NVIC_ITNS<n> */ |
1219 | { | |
cf5f7937 | 1220 | int startvec = 8 * (offset - 0x380) + NVIC_FIRST_IRQ; |
e1be0a57 PM |
1221 | int i; |
1222 | ||
1223 | if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { | |
1224 | goto bad_offset; | |
1225 | } | |
1226 | if (!attrs.secure) { | |
1227 | break; | |
1228 | } | |
1229 | for (i = 0; i < 32 && startvec + i < s->num_irq; i++) { | |
1230 | s->itns[startvec + i] = (value >> i) & 1; | |
1231 | } | |
1232 | nvic_irq_update(s); | |
1233 | break; | |
1234 | } | |
3f1e0eb7 | 1235 | case 0xd04: /* Interrupt Control State (ICSR) */ |
4f2eff36 | 1236 | if (attrs.secure || cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) { |
3f1e0eb7 PM |
1237 | if (value & (1 << 31)) { |
1238 | armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI, false); | |
1239 | } else if (value & (1 << 30) && | |
1240 | arm_feature(&cpu->env, ARM_FEATURE_V8)) { | |
1241 | /* PENDNMICLR didn't exist in v7M */ | |
1242 | armv7m_nvic_clear_pending(s, ARMV7M_EXCP_NMI, false); | |
1243 | } | |
9ee6e8bb PB |
1244 | } |
1245 | if (value & (1 << 28)) { | |
2fb50a33 | 1246 | armv7m_nvic_set_pending(s, ARMV7M_EXCP_PENDSV, attrs.secure); |
9ee6e8bb | 1247 | } else if (value & (1 << 27)) { |
2fb50a33 | 1248 | armv7m_nvic_clear_pending(s, ARMV7M_EXCP_PENDSV, attrs.secure); |
9ee6e8bb PB |
1249 | } |
1250 | if (value & (1 << 26)) { | |
2fb50a33 | 1251 | armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK, attrs.secure); |
9ee6e8bb | 1252 | } else if (value & (1 << 25)) { |
2fb50a33 | 1253 | armv7m_nvic_clear_pending(s, ARMV7M_EXCP_SYSTICK, attrs.secure); |
9ee6e8bb PB |
1254 | } |
1255 | break; | |
1256 | case 0xd08: /* Vector Table Offset. */ | |
45db7ba6 | 1257 | cpu->env.v7m.vecbase[attrs.secure] = value & 0xffffff80; |
9ee6e8bb | 1258 | break; |
3b2e9344 PM |
1259 | case 0xd0c: /* Application Interrupt/Reset Control (AIRCR) */ |
1260 | if ((value >> R_V7M_AIRCR_VECTKEY_SHIFT) == 0x05fa) { | |
1261 | if (value & R_V7M_AIRCR_SYSRESETREQ_MASK) { | |
1262 | if (attrs.secure || | |
1263 | !(cpu->env.v7m.aircr & R_V7M_AIRCR_SYSRESETREQS_MASK)) { | |
1264 | qemu_irq_pulse(s->sysresetreq); | |
1265 | } | |
e192becd | 1266 | } |
3b2e9344 | 1267 | if (value & R_V7M_AIRCR_VECTCLRACTIVE_MASK) { |
14790f73 MD |
1268 | qemu_log_mask(LOG_GUEST_ERROR, |
1269 | "Setting VECTCLRACTIVE when not in DEBUG mode " | |
1270 | "is UNPREDICTABLE\n"); | |
9ee6e8bb | 1271 | } |
3b2e9344 PM |
1272 | if (value & R_V7M_AIRCR_VECTRESET_MASK) { |
1273 | /* NB: this bit is RES0 in v8M */ | |
14790f73 MD |
1274 | qemu_log_mask(LOG_GUEST_ERROR, |
1275 | "Setting VECTRESET when not in DEBUG mode " | |
1276 | "is UNPREDICTABLE\n"); | |
9ee6e8bb | 1277 | } |
3b2e9344 PM |
1278 | s->prigroup[attrs.secure] = extract32(value, |
1279 | R_V7M_AIRCR_PRIGROUP_SHIFT, | |
1280 | R_V7M_AIRCR_PRIGROUP_LENGTH); | |
1281 | if (attrs.secure) { | |
1282 | /* These bits are only writable by secure */ | |
1283 | cpu->env.v7m.aircr = value & | |
1284 | (R_V7M_AIRCR_SYSRESETREQS_MASK | | |
1285 | R_V7M_AIRCR_BFHFNMINS_MASK | | |
1286 | R_V7M_AIRCR_PRIS_MASK); | |
7208b426 PM |
1287 | /* BFHFNMINS changes the priority of Secure HardFault, and |
1288 | * allows a pending Non-secure HardFault to preempt (which | |
1289 | * we implement by marking it enabled). | |
1290 | */ | |
331f4bae PM |
1291 | if (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) { |
1292 | s->sec_vectors[ARMV7M_EXCP_HARD].prio = -3; | |
7208b426 | 1293 | s->vectors[ARMV7M_EXCP_HARD].enabled = 1; |
331f4bae PM |
1294 | } else { |
1295 | s->sec_vectors[ARMV7M_EXCP_HARD].prio = -1; | |
7208b426 | 1296 | s->vectors[ARMV7M_EXCP_HARD].enabled = 0; |
331f4bae | 1297 | } |
3b2e9344 | 1298 | } |
da6d674e | 1299 | nvic_irq_update(s); |
9ee6e8bb PB |
1300 | } |
1301 | break; | |
1302 | case 0xd10: /* System Control. */ | |
7c9140af JS |
1303 | if (!arm_feature(&cpu->env, ARM_FEATURE_V7)) { |
1304 | goto bad_offset; | |
1305 | } | |
24ac0fb1 PM |
1306 | /* We don't implement deep-sleep so these bits are RAZ/WI. |
1307 | * The other bits in the register are banked. | |
1308 | * QEMU's implementation ignores SEVONPEND and SLEEPONEXIT, which | |
1309 | * is architecturally permitted. | |
1310 | */ | |
1311 | value &= ~(R_V7M_SCR_SLEEPDEEP_MASK | R_V7M_SCR_SLEEPDEEPS_MASK); | |
1312 | cpu->env.v7m.scr[attrs.secure] = value; | |
e6b33209 MD |
1313 | break; |
1314 | case 0xd14: /* Configuration Control. */ | |
1315 | /* Enforce RAZ/WI on reserved and must-RAZ/WI bits */ | |
1316 | value &= (R_V7M_CCR_STKALIGN_MASK | | |
1317 | R_V7M_CCR_BFHFNMIGN_MASK | | |
1318 | R_V7M_CCR_DIV_0_TRP_MASK | | |
1319 | R_V7M_CCR_UNALIGN_TRP_MASK | | |
1320 | R_V7M_CCR_USERSETMPEND_MASK | | |
1321 | R_V7M_CCR_NONBASETHRDENA_MASK); | |
1322 | ||
9d40cd8a PM |
1323 | if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { |
1324 | /* v8M makes NONBASETHRDENA and STKALIGN be RES1 */ | |
1325 | value |= R_V7M_CCR_NONBASETHRDENA_MASK | |
1326 | | R_V7M_CCR_STKALIGN_MASK; | |
1327 | } | |
1328 | if (attrs.secure) { | |
1329 | /* the BFHFNMIGN bit is not banked; keep that in the NS copy */ | |
1330 | cpu->env.v7m.ccr[M_REG_NS] = | |
1331 | (cpu->env.v7m.ccr[M_REG_NS] & ~R_V7M_CCR_BFHFNMIGN_MASK) | |
1332 | | (value & R_V7M_CCR_BFHFNMIGN_MASK); | |
1333 | value &= ~R_V7M_CCR_BFHFNMIGN_MASK; | |
1334 | } | |
1335 | ||
1336 | cpu->env.v7m.ccr[attrs.secure] = value; | |
e72e3ffc | 1337 | break; |
437d59c1 PM |
1338 | case 0xd24: /* System Handler Control and State (SHCSR) */ |
1339 | if (attrs.secure) { | |
1340 | s->sec_vectors[ARMV7M_EXCP_MEM].active = (value & (1 << 0)) != 0; | |
1341 | /* Secure HardFault active bit cannot be written */ | |
1342 | s->sec_vectors[ARMV7M_EXCP_USAGE].active = (value & (1 << 3)) != 0; | |
1343 | s->sec_vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0; | |
1344 | s->sec_vectors[ARMV7M_EXCP_PENDSV].active = | |
1345 | (value & (1 << 10)) != 0; | |
1346 | s->sec_vectors[ARMV7M_EXCP_SYSTICK].active = | |
1347 | (value & (1 << 11)) != 0; | |
1348 | s->sec_vectors[ARMV7M_EXCP_USAGE].pending = | |
1349 | (value & (1 << 12)) != 0; | |
1350 | s->sec_vectors[ARMV7M_EXCP_MEM].pending = (value & (1 << 13)) != 0; | |
1351 | s->sec_vectors[ARMV7M_EXCP_SVC].pending = (value & (1 << 15)) != 0; | |
1352 | s->sec_vectors[ARMV7M_EXCP_MEM].enabled = (value & (1 << 16)) != 0; | |
1353 | s->sec_vectors[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0; | |
1354 | s->sec_vectors[ARMV7M_EXCP_USAGE].enabled = | |
1355 | (value & (1 << 18)) != 0; | |
04829ce3 | 1356 | s->sec_vectors[ARMV7M_EXCP_HARD].pending = (value & (1 << 21)) != 0; |
437d59c1 PM |
1357 | /* SecureFault not banked, but RAZ/WI to NS */ |
1358 | s->vectors[ARMV7M_EXCP_SECURE].active = (value & (1 << 4)) != 0; | |
1359 | s->vectors[ARMV7M_EXCP_SECURE].enabled = (value & (1 << 19)) != 0; | |
1360 | s->vectors[ARMV7M_EXCP_SECURE].pending = (value & (1 << 20)) != 0; | |
1361 | } else { | |
1362 | s->vectors[ARMV7M_EXCP_MEM].active = (value & (1 << 0)) != 0; | |
1363 | if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { | |
1364 | /* HARDFAULTPENDED is not present in v7M */ | |
1365 | s->vectors[ARMV7M_EXCP_HARD].pending = (value & (1 << 21)) != 0; | |
1366 | } | |
1367 | s->vectors[ARMV7M_EXCP_USAGE].active = (value & (1 << 3)) != 0; | |
1368 | s->vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0; | |
1369 | s->vectors[ARMV7M_EXCP_PENDSV].active = (value & (1 << 10)) != 0; | |
1370 | s->vectors[ARMV7M_EXCP_SYSTICK].active = (value & (1 << 11)) != 0; | |
1371 | s->vectors[ARMV7M_EXCP_USAGE].pending = (value & (1 << 12)) != 0; | |
1372 | s->vectors[ARMV7M_EXCP_MEM].pending = (value & (1 << 13)) != 0; | |
1373 | s->vectors[ARMV7M_EXCP_SVC].pending = (value & (1 << 15)) != 0; | |
1374 | s->vectors[ARMV7M_EXCP_MEM].enabled = (value & (1 << 16)) != 0; | |
1375 | s->vectors[ARMV7M_EXCP_USAGE].enabled = (value & (1 << 18)) != 0; | |
1376 | } | |
1377 | if (attrs.secure || (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) { | |
1378 | s->vectors[ARMV7M_EXCP_BUS].active = (value & (1 << 1)) != 0; | |
1379 | s->vectors[ARMV7M_EXCP_BUS].pending = (value & (1 << 14)) != 0; | |
1380 | s->vectors[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0; | |
1381 | } | |
1382 | /* NMIACT can only be written if the write is of a zero, with | |
1383 | * BFHFNMINS 1, and by the CPU in secure state via the NS alias. | |
1384 | */ | |
1385 | if (!attrs.secure && cpu->env.v7m.secure && | |
1386 | (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) && | |
1387 | (value & (1 << 5)) == 0) { | |
1388 | s->vectors[ARMV7M_EXCP_NMI].active = 0; | |
1389 | } | |
1390 | /* HARDFAULTACT can only be written if the write is of a zero | |
1391 | * to the non-secure HardFault state by the CPU in secure state. | |
1392 | * The only case where we can be targeting the non-secure HF state | |
1393 | * when in secure state is if this is a write via the NS alias | |
1394 | * and BFHFNMINS is 1. | |
1395 | */ | |
1396 | if (!attrs.secure && cpu->env.v7m.secure && | |
1397 | (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) && | |
1398 | (value & (1 << 2)) == 0) { | |
1399 | s->vectors[ARMV7M_EXCP_HARD].active = 0; | |
1400 | } | |
1401 | ||
1402 | /* TODO: this is RAZ/WI from NS if DEMCR.SDME is set */ | |
5db53e35 | 1403 | s->vectors[ARMV7M_EXCP_DEBUG].active = (value & (1 << 8)) != 0; |
da6d674e | 1404 | nvic_irq_update(s); |
9ee6e8bb | 1405 | break; |
9ee6e8bb | 1406 | case 0xd2c: /* Hard Fault Status. */ |
7c9140af JS |
1407 | if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { |
1408 | goto bad_offset; | |
1409 | } | |
e6b33209 MD |
1410 | cpu->env.v7m.hfsr &= ~value; /* W1C */ |
1411 | break; | |
9ee6e8bb | 1412 | case 0xd30: /* Debug Fault Status. */ |
e6b33209 MD |
1413 | cpu->env.v7m.dfsr &= ~value; /* W1C */ |
1414 | break; | |
9ee6e8bb | 1415 | case 0xd34: /* Mem Manage Address. */ |
7c9140af JS |
1416 | if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { |
1417 | goto bad_offset; | |
1418 | } | |
c51a5cfc | 1419 | cpu->env.v7m.mmfar[attrs.secure] = value; |
e6b33209 | 1420 | return; |
9ee6e8bb | 1421 | case 0xd38: /* Bus Fault Address. */ |
7c9140af JS |
1422 | if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { |
1423 | goto bad_offset; | |
1424 | } | |
e6b33209 MD |
1425 | cpu->env.v7m.bfar = value; |
1426 | return; | |
9ee6e8bb | 1427 | case 0xd3c: /* Aux Fault Status. */ |
e72e3ffc | 1428 | qemu_log_mask(LOG_UNIMP, |
e6b33209 | 1429 | "NVIC: Aux fault status registers unimplemented\n"); |
e72e3ffc | 1430 | break; |
43bbce7f PM |
1431 | case 0xd84: /* CSSELR */ |
1432 | if (!arm_v7m_csselr_razwi(cpu)) { | |
1433 | cpu->env.v7m.csselr[attrs.secure] = value & R_V7M_CSSELR_INDEX_MASK; | |
1434 | } | |
1435 | break; | |
29c483a5 MD |
1436 | case 0xd90: /* MPU_TYPE */ |
1437 | return; /* RO */ | |
1438 | case 0xd94: /* MPU_CTRL */ | |
1439 | if ((value & | |
1440 | (R_V7M_MPU_CTRL_HFNMIENA_MASK | R_V7M_MPU_CTRL_ENABLE_MASK)) | |
1441 | == R_V7M_MPU_CTRL_HFNMIENA_MASK) { | |
1442 | qemu_log_mask(LOG_GUEST_ERROR, "MPU_CTRL: HFNMIENA and !ENABLE is " | |
1443 | "UNPREDICTABLE\n"); | |
1444 | } | |
ecf5e8ea PM |
1445 | cpu->env.v7m.mpu_ctrl[attrs.secure] |
1446 | = value & (R_V7M_MPU_CTRL_ENABLE_MASK | | |
1447 | R_V7M_MPU_CTRL_HFNMIENA_MASK | | |
1448 | R_V7M_MPU_CTRL_PRIVDEFENA_MASK); | |
29c483a5 MD |
1449 | tlb_flush(CPU(cpu)); |
1450 | break; | |
1451 | case 0xd98: /* MPU_RNR */ | |
1452 | if (value >= cpu->pmsav7_dregion) { | |
1453 | qemu_log_mask(LOG_GUEST_ERROR, "MPU region out of range %" | |
1454 | PRIu32 "/%" PRIu32 "\n", | |
1455 | value, cpu->pmsav7_dregion); | |
1456 | } else { | |
1bc04a88 | 1457 | cpu->env.pmsav7.rnr[attrs.secure] = value; |
29c483a5 MD |
1458 | } |
1459 | break; | |
1460 | case 0xd9c: /* MPU_RBAR */ | |
1461 | case 0xda4: /* MPU_RBAR_A1 */ | |
1462 | case 0xdac: /* MPU_RBAR_A2 */ | |
1463 | case 0xdb4: /* MPU_RBAR_A3 */ | |
1464 | { | |
1465 | int region; | |
1466 | ||
0e1a46bb PM |
1467 | if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { |
1468 | /* PMSAv8M handling of the aliases is different from v7M: | |
1469 | * aliases A1, A2, A3 override the low two bits of the region | |
1470 | * number in MPU_RNR, and there is no 'region' field in the | |
1471 | * RBAR register. | |
1472 | */ | |
1473 | int aliasno = (offset - 0xd9c) / 8; /* 0..3 */ | |
1474 | ||
1bc04a88 | 1475 | region = cpu->env.pmsav7.rnr[attrs.secure]; |
0e1a46bb PM |
1476 | if (aliasno) { |
1477 | region = deposit32(region, 0, 2, aliasno); | |
1478 | } | |
1479 | if (region >= cpu->pmsav7_dregion) { | |
1480 | return; | |
1481 | } | |
62c58ee0 | 1482 | cpu->env.pmsav8.rbar[attrs.secure][region] = value; |
0e1a46bb PM |
1483 | tlb_flush(CPU(cpu)); |
1484 | return; | |
1485 | } | |
1486 | ||
29c483a5 MD |
1487 | if (value & (1 << 4)) { |
1488 | /* VALID bit means use the region number specified in this | |
1489 | * value and also update MPU_RNR.REGION with that value. | |
1490 | */ | |
1491 | region = extract32(value, 0, 4); | |
1492 | if (region >= cpu->pmsav7_dregion) { | |
1493 | qemu_log_mask(LOG_GUEST_ERROR, | |
1494 | "MPU region out of range %u/%" PRIu32 "\n", | |
1495 | region, cpu->pmsav7_dregion); | |
1496 | return; | |
1497 | } | |
1bc04a88 | 1498 | cpu->env.pmsav7.rnr[attrs.secure] = region; |
29c483a5 | 1499 | } else { |
1bc04a88 | 1500 | region = cpu->env.pmsav7.rnr[attrs.secure]; |
29c483a5 MD |
1501 | } |
1502 | ||
1503 | if (region >= cpu->pmsav7_dregion) { | |
1504 | return; | |
1505 | } | |
1506 | ||
1507 | cpu->env.pmsav7.drbar[region] = value & ~0x1f; | |
1508 | tlb_flush(CPU(cpu)); | |
1509 | break; | |
1510 | } | |
0e1a46bb PM |
1511 | case 0xda0: /* MPU_RASR (v7M), MPU_RLAR (v8M) */ |
1512 | case 0xda8: /* MPU_RASR_A1 (v7M), MPU_RLAR_A1 (v8M) */ | |
1513 | case 0xdb0: /* MPU_RASR_A2 (v7M), MPU_RLAR_A2 (v8M) */ | |
1514 | case 0xdb8: /* MPU_RASR_A3 (v7M), MPU_RLAR_A3 (v8M) */ | |
29c483a5 | 1515 | { |
1bc04a88 | 1516 | int region = cpu->env.pmsav7.rnr[attrs.secure]; |
29c483a5 | 1517 | |
0e1a46bb PM |
1518 | if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { |
1519 | /* PMSAv8M handling of the aliases is different from v7M: | |
1520 | * aliases A1, A2, A3 override the low two bits of the region | |
1521 | * number in MPU_RNR. | |
1522 | */ | |
1523 | int aliasno = (offset - 0xd9c) / 8; /* 0..3 */ | |
1524 | ||
1bc04a88 | 1525 | region = cpu->env.pmsav7.rnr[attrs.secure]; |
0e1a46bb PM |
1526 | if (aliasno) { |
1527 | region = deposit32(region, 0, 2, aliasno); | |
1528 | } | |
1529 | if (region >= cpu->pmsav7_dregion) { | |
1530 | return; | |
1531 | } | |
62c58ee0 | 1532 | cpu->env.pmsav8.rlar[attrs.secure][region] = value; |
0e1a46bb PM |
1533 | tlb_flush(CPU(cpu)); |
1534 | return; | |
1535 | } | |
1536 | ||
29c483a5 MD |
1537 | if (region >= cpu->pmsav7_dregion) { |
1538 | return; | |
1539 | } | |
1540 | ||
1541 | cpu->env.pmsav7.drsr[region] = value & 0xff3f; | |
1542 | cpu->env.pmsav7.dracr[region] = (value >> 16) & 0x173f; | |
1543 | tlb_flush(CPU(cpu)); | |
1544 | break; | |
1545 | } | |
0e1a46bb PM |
1546 | case 0xdc0: /* MPU_MAIR0 */ |
1547 | if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { | |
1548 | goto bad_offset; | |
1549 | } | |
1550 | if (cpu->pmsav7_dregion) { | |
1551 | /* Register is RES0 if no MPU regions are implemented */ | |
4125e6fe | 1552 | cpu->env.pmsav8.mair0[attrs.secure] = value; |
0e1a46bb PM |
1553 | } |
1554 | /* We don't need to do anything else because memory attributes | |
1555 | * only affect cacheability, and we don't implement caching. | |
1556 | */ | |
1557 | break; | |
1558 | case 0xdc4: /* MPU_MAIR1 */ | |
1559 | if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { | |
1560 | goto bad_offset; | |
1561 | } | |
1562 | if (cpu->pmsav7_dregion) { | |
1563 | /* Register is RES0 if no MPU regions are implemented */ | |
4125e6fe | 1564 | cpu->env.pmsav8.mair1[attrs.secure] = value; |
0e1a46bb PM |
1565 | } |
1566 | /* We don't need to do anything else because memory attributes | |
1567 | * only affect cacheability, and we don't implement caching. | |
1568 | */ | |
1569 | break; | |
9901c576 PM |
1570 | case 0xdd0: /* SAU_CTRL */ |
1571 | if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { | |
1572 | goto bad_offset; | |
1573 | } | |
1574 | if (!attrs.secure) { | |
1575 | return; | |
1576 | } | |
1577 | cpu->env.sau.ctrl = value & 3; | |
a94bb9cd | 1578 | break; |
9901c576 PM |
1579 | case 0xdd4: /* SAU_TYPE */ |
1580 | if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { | |
1581 | goto bad_offset; | |
1582 | } | |
1583 | break; | |
1584 | case 0xdd8: /* SAU_RNR */ | |
1585 | if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { | |
1586 | goto bad_offset; | |
1587 | } | |
1588 | if (!attrs.secure) { | |
1589 | return; | |
1590 | } | |
1591 | if (value >= cpu->sau_sregion) { | |
1592 | qemu_log_mask(LOG_GUEST_ERROR, "SAU region out of range %" | |
1593 | PRIu32 "/%" PRIu32 "\n", | |
1594 | value, cpu->sau_sregion); | |
1595 | } else { | |
1596 | cpu->env.sau.rnr = value; | |
1597 | } | |
1598 | break; | |
1599 | case 0xddc: /* SAU_RBAR */ | |
1600 | { | |
1601 | int region = cpu->env.sau.rnr; | |
1602 | ||
1603 | if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { | |
1604 | goto bad_offset; | |
1605 | } | |
1606 | if (!attrs.secure) { | |
1607 | return; | |
1608 | } | |
1609 | if (region >= cpu->sau_sregion) { | |
1610 | return; | |
1611 | } | |
1612 | cpu->env.sau.rbar[region] = value & ~0x1f; | |
1613 | tlb_flush(CPU(cpu)); | |
1614 | break; | |
1615 | } | |
1616 | case 0xde0: /* SAU_RLAR */ | |
1617 | { | |
1618 | int region = cpu->env.sau.rnr; | |
1619 | ||
1620 | if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { | |
1621 | goto bad_offset; | |
1622 | } | |
1623 | if (!attrs.secure) { | |
1624 | return; | |
1625 | } | |
1626 | if (region >= cpu->sau_sregion) { | |
1627 | return; | |
1628 | } | |
1629 | cpu->env.sau.rlar[region] = value & ~0x1c; | |
1630 | tlb_flush(CPU(cpu)); | |
1631 | break; | |
1632 | } | |
bed079da PM |
1633 | case 0xde4: /* SFSR */ |
1634 | if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { | |
1635 | goto bad_offset; | |
1636 | } | |
1637 | if (!attrs.secure) { | |
1638 | return; | |
1639 | } | |
1640 | cpu->env.v7m.sfsr &= ~value; /* W1C */ | |
1641 | break; | |
1642 | case 0xde8: /* SFAR */ | |
1643 | if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { | |
1644 | goto bad_offset; | |
1645 | } | |
1646 | if (!attrs.secure) { | |
1647 | return; | |
1648 | } | |
1649 | cpu->env.v7m.sfsr = value; | |
1650 | break; | |
2a29ddee | 1651 | case 0xf00: /* Software Triggered Interrupt Register */ |
da6d674e | 1652 | { |
da6d674e | 1653 | int excnum = (value & 0x1ff) + NVIC_FIRST_IRQ; |
7c9140af JS |
1654 | |
1655 | if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { | |
1656 | goto bad_offset; | |
1657 | } | |
1658 | ||
eb578a23 | 1659 | if (excnum < s->num_irq) { |
2fb50a33 | 1660 | armv7m_nvic_set_pending(s, excnum, false); |
2a29ddee PM |
1661 | } |
1662 | break; | |
da6d674e | 1663 | } |
e8ab26c4 PM |
1664 | case 0xf50: /* ICIALLU */ |
1665 | case 0xf58: /* ICIMVAU */ | |
1666 | case 0xf5c: /* DCIMVAC */ | |
1667 | case 0xf60: /* DCISW */ | |
1668 | case 0xf64: /* DCCMVAU */ | |
1669 | case 0xf68: /* DCCMVAC */ | |
1670 | case 0xf6c: /* DCCSW */ | |
1671 | case 0xf70: /* DCCIMVAC */ | |
1672 | case 0xf74: /* DCCISW */ | |
1673 | case 0xf78: /* BPIALL */ | |
1674 | /* Cache and branch predictor maintenance: for QEMU these always NOP */ | |
1675 | break; | |
9ee6e8bb | 1676 | default: |
0e1a46bb | 1677 | bad_offset: |
e72e3ffc PM |
1678 | qemu_log_mask(LOG_GUEST_ERROR, |
1679 | "NVIC: Bad write offset 0x%x\n", offset); | |
9ee6e8bb PB |
1680 | } |
1681 | } | |
1682 | ||
9d40cd8a | 1683 | static bool nvic_user_access_ok(NVICState *s, hwaddr offset, MemTxAttrs attrs) |
eb578a23 PM |
1684 | { |
1685 | /* Return true if unprivileged access to this register is permitted. */ | |
1686 | switch (offset) { | |
1687 | case 0xf00: /* STIR: accessible only if CCR.USERSETMPEND permits */ | |
9d40cd8a PM |
1688 | /* For access via STIR_NS it is the NS CCR.USERSETMPEND that |
1689 | * controls access even though the CPU is in Secure state (I_QDKX). | |
1690 | */ | |
1691 | return s->cpu->env.v7m.ccr[attrs.secure] & R_V7M_CCR_USERSETMPEND_MASK; | |
eb578a23 PM |
1692 | default: |
1693 | /* All other user accesses cause a BusFault unconditionally */ | |
1694 | return false; | |
1695 | } | |
1696 | } | |
1697 | ||
e6a0d350 PM |
1698 | static int shpr_bank(NVICState *s, int exc, MemTxAttrs attrs) |
1699 | { | |
1700 | /* Behaviour for the SHPR register field for this exception: | |
1701 | * return M_REG_NS to use the nonsecure vector (including for | |
1702 | * non-banked exceptions), M_REG_S for the secure version of | |
1703 | * a banked exception, and -1 if this field should RAZ/WI. | |
1704 | */ | |
1705 | switch (exc) { | |
1706 | case ARMV7M_EXCP_MEM: | |
1707 | case ARMV7M_EXCP_USAGE: | |
1708 | case ARMV7M_EXCP_SVC: | |
1709 | case ARMV7M_EXCP_PENDSV: | |
1710 | case ARMV7M_EXCP_SYSTICK: | |
1711 | /* Banked exceptions */ | |
1712 | return attrs.secure; | |
1713 | case ARMV7M_EXCP_BUS: | |
1714 | /* Not banked, RAZ/WI from nonsecure if BFHFNMINS is zero */ | |
1715 | if (!attrs.secure && | |
1716 | !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) { | |
1717 | return -1; | |
1718 | } | |
1719 | return M_REG_NS; | |
1720 | case ARMV7M_EXCP_SECURE: | |
1721 | /* Not banked, RAZ/WI from nonsecure */ | |
1722 | if (!attrs.secure) { | |
1723 | return -1; | |
1724 | } | |
1725 | return M_REG_NS; | |
1726 | case ARMV7M_EXCP_DEBUG: | |
1727 | /* Not banked. TODO should RAZ/WI if DEMCR.SDME is set */ | |
1728 | return M_REG_NS; | |
1729 | case 8 ... 10: | |
1730 | case 13: | |
1731 | /* RES0 */ | |
1732 | return -1; | |
1733 | default: | |
1734 | /* Not reachable due to decode of SHPR register addresses */ | |
1735 | g_assert_not_reached(); | |
1736 | } | |
1737 | } | |
1738 | ||
eb578a23 PM |
1739 | static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr, |
1740 | uint64_t *data, unsigned size, | |
1741 | MemTxAttrs attrs) | |
2a29ddee | 1742 | { |
f797c075 | 1743 | NVICState *s = (NVICState *)opaque; |
2a29ddee | 1744 | uint32_t offset = addr; |
da6d674e | 1745 | unsigned i, startvec, end; |
0e8153dd AB |
1746 | uint32_t val; |
1747 | ||
9d40cd8a | 1748 | if (attrs.user && !nvic_user_access_ok(s, addr, attrs)) { |
eb578a23 PM |
1749 | /* Generate BusFault for unprivileged accesses */ |
1750 | return MEMTX_ERROR; | |
1751 | } | |
1752 | ||
0e8153dd | 1753 | switch (offset) { |
da6d674e MD |
1754 | /* reads of set and clear both return the status */ |
1755 | case 0x100 ... 0x13f: /* NVIC Set enable */ | |
1756 | offset += 0x80; | |
1757 | /* fall through */ | |
1758 | case 0x180 ... 0x1bf: /* NVIC Clear enable */ | |
1759 | val = 0; | |
12fbf1a1 | 1760 | startvec = 8 * (offset - 0x180) + NVIC_FIRST_IRQ; /* vector # */ |
da6d674e MD |
1761 | |
1762 | for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) { | |
e1be0a57 PM |
1763 | if (s->vectors[startvec + i].enabled && |
1764 | (attrs.secure || s->itns[startvec + i])) { | |
da6d674e MD |
1765 | val |= (1 << i); |
1766 | } | |
1767 | } | |
1768 | break; | |
1769 | case 0x200 ... 0x23f: /* NVIC Set pend */ | |
1770 | offset += 0x80; | |
1771 | /* fall through */ | |
1772 | case 0x280 ... 0x2bf: /* NVIC Clear pend */ | |
1773 | val = 0; | |
12fbf1a1 | 1774 | startvec = 8 * (offset - 0x280) + NVIC_FIRST_IRQ; /* vector # */ |
da6d674e | 1775 | for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) { |
e1be0a57 PM |
1776 | if (s->vectors[startvec + i].pending && |
1777 | (attrs.secure || s->itns[startvec + i])) { | |
da6d674e MD |
1778 | val |= (1 << i); |
1779 | } | |
1780 | } | |
1781 | break; | |
1782 | case 0x300 ... 0x33f: /* NVIC Active */ | |
1783 | val = 0; | |
12fbf1a1 | 1784 | startvec = 8 * (offset - 0x300) + NVIC_FIRST_IRQ; /* vector # */ |
da6d674e MD |
1785 | |
1786 | for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) { | |
e1be0a57 PM |
1787 | if (s->vectors[startvec + i].active && |
1788 | (attrs.secure || s->itns[startvec + i])) { | |
da6d674e MD |
1789 | val |= (1 << i); |
1790 | } | |
1791 | } | |
1792 | break; | |
1793 | case 0x400 ... 0x5ef: /* NVIC Priority */ | |
1794 | val = 0; | |
1795 | startvec = offset - 0x400 + NVIC_FIRST_IRQ; /* vector # */ | |
1796 | ||
1797 | for (i = 0; i < size && startvec + i < s->num_irq; i++) { | |
e1be0a57 PM |
1798 | if (attrs.secure || s->itns[startvec + i]) { |
1799 | val |= s->vectors[startvec + i].prio << (8 * i); | |
1800 | } | |
da6d674e MD |
1801 | } |
1802 | break; | |
7c9140af JS |
1803 | case 0xd18: /* System Handler Priority (SHPR1) */ |
1804 | if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_MAIN)) { | |
1805 | val = 0; | |
1806 | break; | |
1807 | } | |
1808 | /* fall through */ | |
1809 | case 0xd1c ... 0xd23: /* System Handler Priority (SHPR2, SHPR3) */ | |
0e8153dd AB |
1810 | val = 0; |
1811 | for (i = 0; i < size; i++) { | |
e6a0d350 PM |
1812 | unsigned hdlidx = (offset - 0xd14) + i; |
1813 | int sbank = shpr_bank(s, hdlidx, attrs); | |
1814 | ||
1815 | if (sbank < 0) { | |
1816 | continue; | |
1817 | } | |
1818 | val = deposit32(val, i * 8, 8, get_prio(s, hdlidx, sbank)); | |
0e8153dd | 1819 | } |
da6d674e | 1820 | break; |
4b9774ef | 1821 | case 0xd28 ... 0xd2b: /* Configurable Fault Status (CFSR) */ |
7c9140af JS |
1822 | if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_MAIN)) { |
1823 | val = 0; | |
1824 | break; | |
1825 | }; | |
4b9774ef PM |
1826 | /* The BFSR bits [15:8] are shared between security states |
1827 | * and we store them in the NS copy | |
1828 | */ | |
1829 | val = s->cpu->env.v7m.cfsr[attrs.secure]; | |
1830 | val |= s->cpu->env.v7m.cfsr[M_REG_NS] & R_V7M_CFSR_BFSR_MASK; | |
1831 | val = extract32(val, (offset - 0xd28) * 8, size * 8); | |
1832 | break; | |
0e8153dd | 1833 | case 0xfe0 ... 0xfff: /* ID. */ |
2a29ddee | 1834 | if (offset & 3) { |
da6d674e MD |
1835 | val = 0; |
1836 | } else { | |
1837 | val = nvic_id[(offset - 0xfe0) >> 2]; | |
1838 | } | |
1839 | break; | |
1840 | default: | |
1841 | if (size == 4) { | |
45db7ba6 | 1842 | val = nvic_readl(s, offset, attrs); |
da6d674e MD |
1843 | } else { |
1844 | qemu_log_mask(LOG_GUEST_ERROR, | |
1845 | "NVIC: Bad read of size %d at offset 0x%x\n", | |
1846 | size, offset); | |
1847 | val = 0; | |
2a29ddee | 1848 | } |
2a29ddee | 1849 | } |
da6d674e MD |
1850 | |
1851 | trace_nvic_sysreg_read(addr, val, size); | |
eb578a23 PM |
1852 | *data = val; |
1853 | return MEMTX_OK; | |
2a29ddee PM |
1854 | } |
1855 | ||
eb578a23 PM |
1856 | static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr, |
1857 | uint64_t value, unsigned size, | |
1858 | MemTxAttrs attrs) | |
2a29ddee | 1859 | { |
f797c075 | 1860 | NVICState *s = (NVICState *)opaque; |
2a29ddee | 1861 | uint32_t offset = addr; |
da6d674e MD |
1862 | unsigned i, startvec, end; |
1863 | unsigned setval = 0; | |
1864 | ||
1865 | trace_nvic_sysreg_write(addr, value, size); | |
0e8153dd | 1866 | |
9d40cd8a | 1867 | if (attrs.user && !nvic_user_access_ok(s, addr, attrs)) { |
eb578a23 PM |
1868 | /* Generate BusFault for unprivileged accesses */ |
1869 | return MEMTX_ERROR; | |
1870 | } | |
1871 | ||
0e8153dd | 1872 | switch (offset) { |
da6d674e MD |
1873 | case 0x100 ... 0x13f: /* NVIC Set enable */ |
1874 | offset += 0x80; | |
1875 | setval = 1; | |
1876 | /* fall through */ | |
1877 | case 0x180 ... 0x1bf: /* NVIC Clear enable */ | |
1878 | startvec = 8 * (offset - 0x180) + NVIC_FIRST_IRQ; | |
1879 | ||
1880 | for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) { | |
e1be0a57 PM |
1881 | if (value & (1 << i) && |
1882 | (attrs.secure || s->itns[startvec + i])) { | |
da6d674e MD |
1883 | s->vectors[startvec + i].enabled = setval; |
1884 | } | |
1885 | } | |
1886 | nvic_irq_update(s); | |
eb578a23 | 1887 | return MEMTX_OK; |
da6d674e MD |
1888 | case 0x200 ... 0x23f: /* NVIC Set pend */ |
1889 | /* the special logic in armv7m_nvic_set_pending() | |
1890 | * is not needed since IRQs are never escalated | |
1891 | */ | |
1892 | offset += 0x80; | |
1893 | setval = 1; | |
1894 | /* fall through */ | |
1895 | case 0x280 ... 0x2bf: /* NVIC Clear pend */ | |
1896 | startvec = 8 * (offset - 0x280) + NVIC_FIRST_IRQ; /* vector # */ | |
1897 | ||
1898 | for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) { | |
e1be0a57 PM |
1899 | if (value & (1 << i) && |
1900 | (attrs.secure || s->itns[startvec + i])) { | |
da6d674e MD |
1901 | s->vectors[startvec + i].pending = setval; |
1902 | } | |
1903 | } | |
1904 | nvic_irq_update(s); | |
eb578a23 | 1905 | return MEMTX_OK; |
da6d674e | 1906 | case 0x300 ... 0x33f: /* NVIC Active */ |
eb578a23 | 1907 | return MEMTX_OK; /* R/O */ |
da6d674e | 1908 | case 0x400 ... 0x5ef: /* NVIC Priority */ |
12fbf1a1 | 1909 | startvec = (offset - 0x400) + NVIC_FIRST_IRQ; /* vector # */ |
da6d674e MD |
1910 | |
1911 | for (i = 0; i < size && startvec + i < s->num_irq; i++) { | |
e1be0a57 | 1912 | if (attrs.secure || s->itns[startvec + i]) { |
e6a0d350 | 1913 | set_prio(s, startvec + i, false, (value >> (i * 8)) & 0xff); |
e1be0a57 | 1914 | } |
da6d674e MD |
1915 | } |
1916 | nvic_irq_update(s); | |
eb578a23 | 1917 | return MEMTX_OK; |
7c9140af JS |
1918 | case 0xd18: /* System Handler Priority (SHPR1) */ |
1919 | if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_MAIN)) { | |
1920 | return MEMTX_OK; | |
1921 | } | |
1922 | /* fall through */ | |
1923 | case 0xd1c ... 0xd23: /* System Handler Priority (SHPR2, SHPR3) */ | |
0e8153dd | 1924 | for (i = 0; i < size; i++) { |
da6d674e | 1925 | unsigned hdlidx = (offset - 0xd14) + i; |
e6a0d350 PM |
1926 | int newprio = extract32(value, i * 8, 8); |
1927 | int sbank = shpr_bank(s, hdlidx, attrs); | |
1928 | ||
1929 | if (sbank < 0) { | |
1930 | continue; | |
1931 | } | |
1932 | set_prio(s, hdlidx, sbank, newprio); | |
0e8153dd | 1933 | } |
da6d674e | 1934 | nvic_irq_update(s); |
eb578a23 | 1935 | return MEMTX_OK; |
4b9774ef | 1936 | case 0xd28 ... 0xd2b: /* Configurable Fault Status (CFSR) */ |
7c9140af JS |
1937 | if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_MAIN)) { |
1938 | return MEMTX_OK; | |
1939 | } | |
4b9774ef PM |
1940 | /* All bits are W1C, so construct 32 bit value with 0s in |
1941 | * the parts not written by the access size | |
1942 | */ | |
1943 | value <<= ((offset - 0xd28) * 8); | |
1944 | ||
1945 | s->cpu->env.v7m.cfsr[attrs.secure] &= ~value; | |
1946 | if (attrs.secure) { | |
1947 | /* The BFSR bits [15:8] are shared between security states | |
1948 | * and we store them in the NS copy. | |
1949 | */ | |
1950 | s->cpu->env.v7m.cfsr[M_REG_NS] &= ~(value & R_V7M_CFSR_BFSR_MASK); | |
1951 | } | |
1952 | return MEMTX_OK; | |
0e8153dd | 1953 | } |
2a29ddee | 1954 | if (size == 4) { |
45db7ba6 | 1955 | nvic_writel(s, offset, value, attrs); |
eb578a23 | 1956 | return MEMTX_OK; |
2a29ddee | 1957 | } |
e72e3ffc PM |
1958 | qemu_log_mask(LOG_GUEST_ERROR, |
1959 | "NVIC: Bad write of size %d at offset 0x%x\n", size, offset); | |
eb578a23 PM |
1960 | /* This is UNPREDICTABLE; treat as RAZ/WI */ |
1961 | return MEMTX_OK; | |
2a29ddee PM |
1962 | } |
1963 | ||
1964 | static const MemoryRegionOps nvic_sysreg_ops = { | |
eb578a23 PM |
1965 | .read_with_attrs = nvic_sysreg_read, |
1966 | .write_with_attrs = nvic_sysreg_write, | |
2a29ddee PM |
1967 | .endianness = DEVICE_NATIVE_ENDIAN, |
1968 | }; | |
1969 | ||
f104919d PM |
1970 | static MemTxResult nvic_sysreg_ns_write(void *opaque, hwaddr addr, |
1971 | uint64_t value, unsigned size, | |
1972 | MemTxAttrs attrs) | |
1973 | { | |
62f01848 PM |
1974 | MemoryRegion *mr = opaque; |
1975 | ||
f104919d PM |
1976 | if (attrs.secure) { |
1977 | /* S accesses to the alias act like NS accesses to the real region */ | |
1978 | attrs.secure = 0; | |
62f01848 | 1979 | return memory_region_dispatch_write(mr, addr, value, size, attrs); |
f104919d PM |
1980 | } else { |
1981 | /* NS attrs are RAZ/WI for privileged, and BusFault for user */ | |
1982 | if (attrs.user) { | |
1983 | return MEMTX_ERROR; | |
1984 | } | |
1985 | return MEMTX_OK; | |
1986 | } | |
1987 | } | |
1988 | ||
1989 | static MemTxResult nvic_sysreg_ns_read(void *opaque, hwaddr addr, | |
1990 | uint64_t *data, unsigned size, | |
1991 | MemTxAttrs attrs) | |
1992 | { | |
62f01848 PM |
1993 | MemoryRegion *mr = opaque; |
1994 | ||
f104919d PM |
1995 | if (attrs.secure) { |
1996 | /* S accesses to the alias act like NS accesses to the real region */ | |
1997 | attrs.secure = 0; | |
62f01848 | 1998 | return memory_region_dispatch_read(mr, addr, data, size, attrs); |
f104919d PM |
1999 | } else { |
2000 | /* NS attrs are RAZ/WI for privileged, and BusFault for user */ | |
2001 | if (attrs.user) { | |
2002 | return MEMTX_ERROR; | |
2003 | } | |
2004 | *data = 0; | |
2005 | return MEMTX_OK; | |
2006 | } | |
2007 | } | |
2008 | ||
2009 | static const MemoryRegionOps nvic_sysreg_ns_ops = { | |
2010 | .read_with_attrs = nvic_sysreg_ns_read, | |
2011 | .write_with_attrs = nvic_sysreg_ns_write, | |
2012 | .endianness = DEVICE_NATIVE_ENDIAN, | |
2013 | }; | |
2014 | ||
27f26bfe PM |
2015 | static MemTxResult nvic_systick_write(void *opaque, hwaddr addr, |
2016 | uint64_t value, unsigned size, | |
2017 | MemTxAttrs attrs) | |
2018 | { | |
2019 | NVICState *s = opaque; | |
2020 | MemoryRegion *mr; | |
2021 | ||
2022 | /* Direct the access to the correct systick */ | |
2023 | mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]), 0); | |
2024 | return memory_region_dispatch_write(mr, addr, value, size, attrs); | |
2025 | } | |
2026 | ||
2027 | static MemTxResult nvic_systick_read(void *opaque, hwaddr addr, | |
2028 | uint64_t *data, unsigned size, | |
2029 | MemTxAttrs attrs) | |
2030 | { | |
2031 | NVICState *s = opaque; | |
2032 | MemoryRegion *mr; | |
2033 | ||
2034 | /* Direct the access to the correct systick */ | |
2035 | mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]), 0); | |
2036 | return memory_region_dispatch_read(mr, addr, data, size, attrs); | |
2037 | } | |
2038 | ||
2039 | static const MemoryRegionOps nvic_systick_ops = { | |
2040 | .read_with_attrs = nvic_systick_read, | |
2041 | .write_with_attrs = nvic_systick_write, | |
2042 | .endianness = DEVICE_NATIVE_ENDIAN, | |
2043 | }; | |
2044 | ||
da6d674e MD |
2045 | static int nvic_post_load(void *opaque, int version_id) |
2046 | { | |
2047 | NVICState *s = opaque; | |
2048 | unsigned i; | |
331f4bae | 2049 | int resetprio; |
da6d674e MD |
2050 | |
2051 | /* Check for out of range priority settings */ | |
331f4bae PM |
2052 | resetprio = arm_feature(&s->cpu->env, ARM_FEATURE_V8) ? -4 : -3; |
2053 | ||
2054 | if (s->vectors[ARMV7M_EXCP_RESET].prio != resetprio || | |
da6d674e MD |
2055 | s->vectors[ARMV7M_EXCP_NMI].prio != -2 || |
2056 | s->vectors[ARMV7M_EXCP_HARD].prio != -1) { | |
2057 | return 1; | |
2058 | } | |
2059 | for (i = ARMV7M_EXCP_MEM; i < s->num_irq; i++) { | |
2060 | if (s->vectors[i].prio & ~0xff) { | |
2061 | return 1; | |
2062 | } | |
2063 | } | |
2064 | ||
2065 | nvic_recompute_state(s); | |
2066 | ||
2067 | return 0; | |
2068 | } | |
2069 | ||
2070 | static const VMStateDescription vmstate_VecInfo = { | |
2071 | .name = "armv7m_nvic_info", | |
2072 | .version_id = 1, | |
2073 | .minimum_version_id = 1, | |
2074 | .fields = (VMStateField[]) { | |
2075 | VMSTATE_INT16(prio, VecInfo), | |
2076 | VMSTATE_UINT8(enabled, VecInfo), | |
2077 | VMSTATE_UINT8(pending, VecInfo), | |
2078 | VMSTATE_UINT8(active, VecInfo), | |
2079 | VMSTATE_UINT8(level, VecInfo), | |
2080 | VMSTATE_END_OF_LIST() | |
2081 | } | |
2082 | }; | |
2083 | ||
17906a16 PM |
2084 | static bool nvic_security_needed(void *opaque) |
2085 | { | |
2086 | NVICState *s = opaque; | |
2087 | ||
2088 | return arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY); | |
2089 | } | |
2090 | ||
2091 | static int nvic_security_post_load(void *opaque, int version_id) | |
2092 | { | |
2093 | NVICState *s = opaque; | |
2094 | int i; | |
2095 | ||
2096 | /* Check for out of range priority settings */ | |
331f4bae PM |
2097 | if (s->sec_vectors[ARMV7M_EXCP_HARD].prio != -1 |
2098 | && s->sec_vectors[ARMV7M_EXCP_HARD].prio != -3) { | |
2099 | /* We can't cross-check against AIRCR.BFHFNMINS as we don't know | |
2100 | * if the CPU state has been migrated yet; a mismatch won't | |
2101 | * cause the emulation to blow up, though. | |
2102 | */ | |
17906a16 PM |
2103 | return 1; |
2104 | } | |
2105 | for (i = ARMV7M_EXCP_MEM; i < ARRAY_SIZE(s->sec_vectors); i++) { | |
2106 | if (s->sec_vectors[i].prio & ~0xff) { | |
2107 | return 1; | |
2108 | } | |
2109 | } | |
2110 | return 0; | |
2111 | } | |
2112 | ||
2113 | static const VMStateDescription vmstate_nvic_security = { | |
942566ff | 2114 | .name = "armv7m_nvic/m-security", |
17906a16 PM |
2115 | .version_id = 1, |
2116 | .minimum_version_id = 1, | |
2117 | .needed = nvic_security_needed, | |
2118 | .post_load = &nvic_security_post_load, | |
2119 | .fields = (VMStateField[]) { | |
2120 | VMSTATE_STRUCT_ARRAY(sec_vectors, NVICState, NVIC_INTERNAL_VECTORS, 1, | |
2121 | vmstate_VecInfo, VecInfo), | |
3b2e9344 | 2122 | VMSTATE_UINT32(prigroup[M_REG_S], NVICState), |
e1be0a57 | 2123 | VMSTATE_BOOL_ARRAY(itns, NVICState, NVIC_MAX_VECTORS), |
17906a16 PM |
2124 | VMSTATE_END_OF_LIST() |
2125 | } | |
2126 | }; | |
2127 | ||
0797226c JQ |
2128 | static const VMStateDescription vmstate_nvic = { |
2129 | .name = "armv7m_nvic", | |
ff68dacb PM |
2130 | .version_id = 4, |
2131 | .minimum_version_id = 4, | |
da6d674e | 2132 | .post_load = &nvic_post_load, |
8f1e884b | 2133 | .fields = (VMStateField[]) { |
da6d674e MD |
2134 | VMSTATE_STRUCT_ARRAY(vectors, NVICState, NVIC_MAX_VECTORS, 1, |
2135 | vmstate_VecInfo, VecInfo), | |
3b2e9344 | 2136 | VMSTATE_UINT32(prigroup[M_REG_NS], NVICState), |
0797226c | 2137 | VMSTATE_END_OF_LIST() |
17906a16 PM |
2138 | }, |
2139 | .subsections = (const VMStateDescription*[]) { | |
2140 | &vmstate_nvic_security, | |
2141 | NULL | |
0797226c JQ |
2142 | } |
2143 | }; | |
23e39294 | 2144 | |
da6d674e MD |
2145 | static Property props_nvic[] = { |
2146 | /* Number of external IRQ lines (so excluding the 16 internal exceptions) */ | |
2147 | DEFINE_PROP_UINT32("num-irq", NVICState, num_irq, 64), | |
2148 | DEFINE_PROP_END_OF_LIST() | |
2149 | }; | |
2150 | ||
aecff692 PM |
2151 | static void armv7m_nvic_reset(DeviceState *dev) |
2152 | { | |
331f4bae | 2153 | int resetprio; |
f797c075 | 2154 | NVICState *s = NVIC(dev); |
da6d674e | 2155 | |
8ff26a33 PM |
2156 | memset(s->vectors, 0, sizeof(s->vectors)); |
2157 | memset(s->sec_vectors, 0, sizeof(s->sec_vectors)); | |
2158 | s->prigroup[M_REG_NS] = 0; | |
2159 | s->prigroup[M_REG_S] = 0; | |
2160 | ||
da6d674e | 2161 | s->vectors[ARMV7M_EXCP_NMI].enabled = 1; |
da6d674e MD |
2162 | /* MEM, BUS, and USAGE are enabled through |
2163 | * the System Handler Control register | |
b3387ede | 2164 | */ |
da6d674e MD |
2165 | s->vectors[ARMV7M_EXCP_SVC].enabled = 1; |
2166 | s->vectors[ARMV7M_EXCP_DEBUG].enabled = 1; | |
2167 | s->vectors[ARMV7M_EXCP_PENDSV].enabled = 1; | |
2168 | s->vectors[ARMV7M_EXCP_SYSTICK].enabled = 1; | |
2169 | ||
331f4bae PM |
2170 | resetprio = arm_feature(&s->cpu->env, ARM_FEATURE_V8) ? -4 : -3; |
2171 | s->vectors[ARMV7M_EXCP_RESET].prio = resetprio; | |
da6d674e MD |
2172 | s->vectors[ARMV7M_EXCP_NMI].prio = -2; |
2173 | s->vectors[ARMV7M_EXCP_HARD].prio = -1; | |
2174 | ||
17906a16 PM |
2175 | if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) { |
2176 | s->sec_vectors[ARMV7M_EXCP_HARD].enabled = 1; | |
2177 | s->sec_vectors[ARMV7M_EXCP_SVC].enabled = 1; | |
2178 | s->sec_vectors[ARMV7M_EXCP_PENDSV].enabled = 1; | |
2179 | s->sec_vectors[ARMV7M_EXCP_SYSTICK].enabled = 1; | |
2180 | ||
2181 | /* AIRCR.BFHFNMINS resets to 0 so Secure HF is priority -1 (R_CMTC) */ | |
2182 | s->sec_vectors[ARMV7M_EXCP_HARD].prio = -1; | |
7208b426 PM |
2183 | /* If AIRCR.BFHFNMINS is 0 then NS HF is (effectively) disabled */ |
2184 | s->vectors[ARMV7M_EXCP_HARD].enabled = 0; | |
2185 | } else { | |
2186 | s->vectors[ARMV7M_EXCP_HARD].enabled = 1; | |
17906a16 PM |
2187 | } |
2188 | ||
da6d674e MD |
2189 | /* Strictly speaking the reset handler should be enabled. |
2190 | * However, we don't simulate soft resets through the NVIC, | |
2191 | * and the reset vector should never be pended. | |
2192 | * So we leave it disabled to catch logic errors. | |
2193 | */ | |
2194 | ||
2195 | s->exception_prio = NVIC_NOEXC_PRIO; | |
2196 | s->vectpending = 0; | |
e93bc2ac | 2197 | s->vectpending_is_s_banked = false; |
5255fcf8 | 2198 | s->vectpending_prio = NVIC_NOEXC_PRIO; |
e1be0a57 PM |
2199 | |
2200 | if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) { | |
2201 | memset(s->itns, 0, sizeof(s->itns)); | |
2202 | } else { | |
2203 | /* This state is constant and not guest accessible in a non-security | |
2204 | * NVIC; we set the bits to true to avoid having to do a feature | |
2205 | * bit check in the NVIC enable/pend/etc register accessors. | |
2206 | */ | |
2207 | int i; | |
2208 | ||
2209 | for (i = NVIC_FIRST_IRQ; i < ARRAY_SIZE(s->itns); i++) { | |
2210 | s->itns[i] = true; | |
2211 | } | |
2212 | } | |
ff68dacb | 2213 | } |
da6d674e | 2214 | |
ff68dacb PM |
2215 | static void nvic_systick_trigger(void *opaque, int n, int level) |
2216 | { | |
2217 | NVICState *s = opaque; | |
2218 | ||
2219 | if (level) { | |
2220 | /* SysTick just asked us to pend its exception. | |
2221 | * (This is different from an external interrupt line's | |
2222 | * behaviour.) | |
27f26bfe PM |
2223 | * n == 0 : NonSecure systick |
2224 | * n == 1 : Secure systick | |
ff68dacb | 2225 | */ |
27f26bfe | 2226 | armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK, n); |
ff68dacb | 2227 | } |
aecff692 PM |
2228 | } |
2229 | ||
53111180 | 2230 | static void armv7m_nvic_realize(DeviceState *dev, Error **errp) |
9ee6e8bb | 2231 | { |
f797c075 | 2232 | NVICState *s = NVIC(dev); |
ff68dacb | 2233 | Error *err = NULL; |
f104919d | 2234 | int regionlen; |
9ee6e8bb | 2235 | |
d713ea6c | 2236 | s->cpu = ARM_CPU(qemu_get_cpu(0)); |
95f87565 PM |
2237 | |
2238 | if (!s->cpu || !arm_feature(&s->cpu->env, ARM_FEATURE_M)) { | |
2239 | error_setg(errp, "The NVIC can only be used with a Cortex-M CPU"); | |
2240 | return; | |
2241 | } | |
da6d674e MD |
2242 | |
2243 | if (s->num_irq > NVIC_MAX_IRQ) { | |
2244 | error_setg(errp, "num-irq %d exceeds NVIC maximum", s->num_irq); | |
53111180 PM |
2245 | return; |
2246 | } | |
da6d674e MD |
2247 | |
2248 | qdev_init_gpio_in(dev, set_irq_level, s->num_irq); | |
2249 | ||
2250 | /* include space for internal exception vectors */ | |
2251 | s->num_irq += NVIC_FIRST_IRQ; | |
2252 | ||
27f26bfe PM |
2253 | object_property_set_bool(OBJECT(&s->systick[M_REG_NS]), true, |
2254 | "realized", &err); | |
ff68dacb PM |
2255 | if (err != NULL) { |
2256 | error_propagate(errp, err); | |
2257 | return; | |
2258 | } | |
27f26bfe PM |
2259 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->systick[M_REG_NS]), 0, |
2260 | qdev_get_gpio_in_named(dev, "systick-trigger", | |
2261 | M_REG_NS)); | |
2262 | ||
2263 | if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) { | |
2264 | /* We couldn't init the secure systick device in instance_init | |
2265 | * as we didn't know then if the CPU had the security extensions; | |
2266 | * so we have to do it here. | |
2267 | */ | |
2268 | object_initialize(&s->systick[M_REG_S], sizeof(s->systick[M_REG_S]), | |
2269 | TYPE_SYSTICK); | |
2270 | qdev_set_parent_bus(DEVICE(&s->systick[M_REG_S]), sysbus_get_default()); | |
2271 | ||
2272 | object_property_set_bool(OBJECT(&s->systick[M_REG_S]), true, | |
2273 | "realized", &err); | |
2274 | if (err != NULL) { | |
2275 | error_propagate(errp, err); | |
2276 | return; | |
2277 | } | |
2278 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->systick[M_REG_S]), 0, | |
2279 | qdev_get_gpio_in_named(dev, "systick-trigger", | |
2280 | M_REG_S)); | |
2281 | } | |
ff68dacb | 2282 | |
da6d674e MD |
2283 | /* The NVIC and System Control Space (SCS) starts at 0xe000e000 |
2284 | * and looks like this: | |
2285 | * 0x004 - ICTR | |
ff68dacb | 2286 | * 0x010 - 0xff - systick |
da6d674e MD |
2287 | * 0x100..0x7ec - NVIC |
2288 | * 0x7f0..0xcff - Reserved | |
2289 | * 0xd00..0xd3c - SCS registers | |
2290 | * 0xd40..0xeff - Reserved or Not implemented | |
2291 | * 0xf00 - STIR | |
f104919d PM |
2292 | * |
2293 | * Some registers within this space are banked between security states. | |
2294 | * In v8M there is a second range 0xe002e000..0xe002efff which is the | |
2295 | * NonSecure alias SCS; secure accesses to this behave like NS accesses | |
2296 | * to the main SCS range, and non-secure accesses (including when | |
2297 | * the security extension is not implemented) are RAZ/WI. | |
2298 | * Note that both the main SCS range and the alias range are defined | |
2299 | * to be exempt from memory attribution (R_BLJT) and so the memory | |
2300 | * transaction attribute always matches the current CPU security | |
2301 | * state (attrs.secure == env->v7m.secure). In the nvic_sysreg_ns_ops | |
2302 | * wrappers we change attrs.secure to indicate the NS access; so | |
2303 | * generally code determining which banked register to use should | |
2304 | * use attrs.secure; code determining actual behaviour of the system | |
2305 | * should use env->v7m.secure. | |
2a29ddee | 2306 | */ |
f104919d PM |
2307 | regionlen = arm_feature(&s->cpu->env, ARM_FEATURE_V8) ? 0x21000 : 0x1000; |
2308 | memory_region_init(&s->container, OBJECT(s), "nvic", regionlen); | |
2a29ddee PM |
2309 | /* The system register region goes at the bottom of the priority |
2310 | * stack as it covers the whole page. | |
2311 | */ | |
1437c94b | 2312 | memory_region_init_io(&s->sysregmem, OBJECT(s), &nvic_sysreg_ops, s, |
2a29ddee PM |
2313 | "nvic_sysregs", 0x1000); |
2314 | memory_region_add_subregion(&s->container, 0, &s->sysregmem); | |
27f26bfe PM |
2315 | |
2316 | memory_region_init_io(&s->systickmem, OBJECT(s), | |
2317 | &nvic_systick_ops, s, | |
2318 | "nvic_systick", 0xe0); | |
2319 | ||
ff68dacb | 2320 | memory_region_add_subregion_overlap(&s->container, 0x10, |
27f26bfe | 2321 | &s->systickmem, 1); |
da6d674e | 2322 | |
f104919d PM |
2323 | if (arm_feature(&s->cpu->env, ARM_FEATURE_V8)) { |
2324 | memory_region_init_io(&s->sysreg_ns_mem, OBJECT(s), | |
62f01848 | 2325 | &nvic_sysreg_ns_ops, &s->sysregmem, |
f104919d PM |
2326 | "nvic_sysregs_ns", 0x1000); |
2327 | memory_region_add_subregion(&s->container, 0x20000, &s->sysreg_ns_mem); | |
27f26bfe PM |
2328 | memory_region_init_io(&s->systick_ns_mem, OBJECT(s), |
2329 | &nvic_sysreg_ns_ops, &s->systickmem, | |
2330 | "nvic_systick_ns", 0xe0); | |
2331 | memory_region_add_subregion_overlap(&s->container, 0x20010, | |
2332 | &s->systick_ns_mem, 1); | |
f104919d PM |
2333 | } |
2334 | ||
98957a94 | 2335 | sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container); |
9ee6e8bb | 2336 | } |
fe7e8758 | 2337 | |
55e00a19 PM |
2338 | static void armv7m_nvic_instance_init(Object *obj) |
2339 | { | |
2340 | /* We have a different default value for the num-irq property | |
2341 | * than our superclass. This function runs after qdev init | |
2342 | * has set the defaults from the Property array and before | |
2343 | * any user-specified property setting, so just modify the | |
fae15286 | 2344 | * value in the GICState struct. |
55e00a19 | 2345 | */ |
e192becd | 2346 | DeviceState *dev = DEVICE(obj); |
f797c075 | 2347 | NVICState *nvic = NVIC(obj); |
da6d674e MD |
2348 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
2349 | ||
955cbc6b TH |
2350 | sysbus_init_child_obj(obj, "systick-reg-ns", &nvic->systick[M_REG_NS], |
2351 | sizeof(nvic->systick[M_REG_NS]), TYPE_SYSTICK); | |
27f26bfe PM |
2352 | /* We can't initialize the secure systick here, as we don't know |
2353 | * yet if we need it. | |
2354 | */ | |
ff68dacb | 2355 | |
da6d674e | 2356 | sysbus_init_irq(sbd, &nvic->excpout); |
e192becd | 2357 | qdev_init_gpio_out_named(dev, &nvic->sysresetreq, "SYSRESETREQ", 1); |
27f26bfe PM |
2358 | qdev_init_gpio_in_named(dev, nvic_systick_trigger, "systick-trigger", |
2359 | M_REG_NUM_BANKS); | |
55e00a19 | 2360 | } |
39bffca2 | 2361 | |
999e12bb AL |
2362 | static void armv7m_nvic_class_init(ObjectClass *klass, void *data) |
2363 | { | |
39bffca2 | 2364 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 2365 | |
39bffca2 | 2366 | dc->vmsd = &vmstate_nvic; |
da6d674e | 2367 | dc->props = props_nvic; |
aecff692 | 2368 | dc->reset = armv7m_nvic_reset; |
53111180 | 2369 | dc->realize = armv7m_nvic_realize; |
999e12bb AL |
2370 | } |
2371 | ||
8c43a6f0 | 2372 | static const TypeInfo armv7m_nvic_info = { |
1e8cae4d | 2373 | .name = TYPE_NVIC, |
da6d674e | 2374 | .parent = TYPE_SYS_BUS_DEVICE, |
55e00a19 | 2375 | .instance_init = armv7m_nvic_instance_init, |
f797c075 | 2376 | .instance_size = sizeof(NVICState), |
39bffca2 | 2377 | .class_init = armv7m_nvic_class_init, |
da6d674e | 2378 | .class_size = sizeof(SysBusDeviceClass), |
a32134aa ML |
2379 | }; |
2380 | ||
83f7d43a | 2381 | static void armv7m_nvic_register_types(void) |
fe7e8758 | 2382 | { |
39bffca2 | 2383 | type_register_static(&armv7m_nvic_info); |
fe7e8758 PB |
2384 | } |
2385 | ||
83f7d43a | 2386 | type_init(armv7m_nvic_register_types) |