]>
Commit | Line | Data |
---|---|---|
e62b5b13 EI |
1 | /* |
2 | * QEMU ETRAX Interrupt Controller. | |
3 | * | |
4 | * Copyright (c) 2008 Edgar E. Iglesias, Axis Communications AB. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
90191d07 | 25 | #include "qemu/osdep.h" |
83c9f4ca | 26 | #include "hw/sysbus.h" |
0b8fa32f | 27 | #include "qemu/module.h" |
64552b6b | 28 | #include "hw/irq.h" |
a27bd6c7 | 29 | #include "hw/qdev-properties.h" |
db1015e9 | 30 | #include "qom/object.h" |
e62b5b13 EI |
31 | |
32 | #define D(x) | |
33 | ||
979d98ca EI |
34 | #define R_RW_MASK 0 |
35 | #define R_R_VECT 1 | |
36 | #define R_R_MASKED_VECT 2 | |
37 | #define R_R_NMI 3 | |
38 | #define R_R_GURU 4 | |
39 | #define R_MAX 5 | |
8d13fcc0 | 40 | |
9062143f | 41 | #define TYPE_ETRAX_FS_PIC "etraxfs,pic" |
8110fa1d EH |
42 | DECLARE_INSTANCE_CHECKER(struct etrax_pic, ETRAX_FS_PIC, |
43 | TYPE_ETRAX_FS_PIC) | |
9062143f | 44 | |
fd6dc90b | 45 | struct etrax_pic |
e62b5b13 | 46 | { |
9062143f AF |
47 | SysBusDevice parent_obj; |
48 | ||
5dd25f36 | 49 | MemoryRegion mmio; |
fd6dc90b EI |
50 | qemu_irq parent_irq; |
51 | qemu_irq parent_nmi; | |
979d98ca | 52 | uint32_t regs[R_MAX]; |
e62b5b13 EI |
53 | }; |
54 | ||
fd6dc90b | 55 | static void pic_update(struct etrax_pic *fs) |
979d98ca | 56 | { |
979d98ca EI |
57 | uint32_t vector = 0; |
58 | int i; | |
59 | ||
60 | fs->regs[R_R_MASKED_VECT] = fs->regs[R_R_VECT] & fs->regs[R_RW_MASK]; | |
61 | ||
66a0a2cb | 62 | /* The ETRAX interrupt controller signals interrupts to the core |
979d98ca EI |
63 | through an interrupt request wire and an irq vector bus. If |
64 | multiple interrupts are simultaneously active it chooses vector | |
65 | 0x30 and lets the sw choose the priorities. */ | |
66 | if (fs->regs[R_R_MASKED_VECT]) { | |
67 | uint32_t mv = fs->regs[R_R_MASKED_VECT]; | |
68 | for (i = 0; i < 31; i++) { | |
69 | if (mv & 1) { | |
70 | vector = 0x31 + i; | |
71 | /* Check for multiple interrupts. */ | |
72 | if (mv > 1) | |
73 | vector = 0x30; | |
74 | break; | |
75 | } | |
76 | mv >>= 1; | |
77 | } | |
979d98ca | 78 | } |
fd6dc90b | 79 | |
f4f64388 | 80 | qemu_set_irq(fs->parent_irq, vector); |
e62b5b13 EI |
81 | } |
82 | ||
5dd25f36 | 83 | static uint64_t |
a8170e5e | 84 | pic_read(void *opaque, hwaddr addr, unsigned int size) |
e62b5b13 | 85 | { |
fd6dc90b | 86 | struct etrax_pic *fs = opaque; |
979d98ca | 87 | uint32_t rval; |
e62b5b13 | 88 | |
979d98ca EI |
89 | rval = fs->regs[addr >> 2]; |
90 | D(printf("%s %x=%x\n", __func__, addr, rval)); | |
91 | return rval; | |
e62b5b13 EI |
92 | } |
93 | ||
a8170e5e | 94 | static void pic_write(void *opaque, hwaddr addr, |
5dd25f36 | 95 | uint64_t value, unsigned int size) |
e62b5b13 | 96 | { |
fd6dc90b | 97 | struct etrax_pic *fs = opaque; |
979d98ca | 98 | D(printf("%s addr=%x val=%x\n", __func__, addr, value)); |
8d13fcc0 | 99 | |
979d98ca EI |
100 | if (addr == R_RW_MASK) { |
101 | fs->regs[R_RW_MASK] = value; | |
102 | pic_update(fs); | |
103 | } | |
e62b5b13 EI |
104 | } |
105 | ||
5dd25f36 EI |
106 | static const MemoryRegionOps pic_ops = { |
107 | .read = pic_read, | |
108 | .write = pic_write, | |
109 | .endianness = DEVICE_NATIVE_ENDIAN, | |
110 | .valid = { | |
111 | .min_access_size = 4, | |
112 | .max_access_size = 4 | |
113 | } | |
e62b5b13 EI |
114 | }; |
115 | ||
5ef98b47 | 116 | static void nmi_handler(void *opaque, int irq, int level) |
979d98ca | 117 | { |
fd6dc90b | 118 | struct etrax_pic *fs = (void *)opaque; |
979d98ca EI |
119 | uint32_t mask; |
120 | ||
121 | mask = 1 << irq; | |
122 | if (level) | |
123 | fs->regs[R_R_NMI] |= mask; | |
124 | else | |
125 | fs->regs[R_R_NMI] &= ~mask; | |
126 | ||
fd6dc90b | 127 | qemu_set_irq(fs->parent_nmi, !!fs->regs[R_R_NMI]); |
5ef98b47 EI |
128 | } |
129 | ||
73cfd29f | 130 | static void irq_handler(void *opaque, int irq, int level) |
e7ae771f | 131 | { |
fd6dc90b | 132 | struct etrax_pic *fs = (void *)opaque; |
73cfd29f | 133 | |
e7ae771f SW |
134 | if (irq >= 30) { |
135 | nmi_handler(opaque, irq, level); | |
136 | return; | |
137 | } | |
73cfd29f | 138 | |
979d98ca EI |
139 | irq -= 1; |
140 | fs->regs[R_R_VECT] &= ~(1 << irq); | |
141 | fs->regs[R_R_VECT] |= (!!level << irq); | |
142 | pic_update(fs); | |
5ef98b47 EI |
143 | } |
144 | ||
b46818e9 | 145 | static void etraxfs_pic_init(Object *obj) |
e62b5b13 | 146 | { |
b46818e9 XZ |
147 | DeviceState *dev = DEVICE(obj); |
148 | struct etrax_pic *s = ETRAX_FS_PIC(obj); | |
149 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | |
e62b5b13 | 150 | |
9062143f AF |
151 | qdev_init_gpio_in(dev, irq_handler, 32); |
152 | sysbus_init_irq(sbd, &s->parent_irq); | |
153 | sysbus_init_irq(sbd, &s->parent_nmi); | |
e62b5b13 | 154 | |
b46818e9 | 155 | memory_region_init_io(&s->mmio, obj, &pic_ops, s, |
1437c94b | 156 | "etraxfs-pic", R_MAX * 4); |
9062143f | 157 | sysbus_init_mmio(sbd, &s->mmio); |
e62b5b13 | 158 | } |
fd6dc90b | 159 | |
8c43a6f0 | 160 | static const TypeInfo etraxfs_pic_info = { |
9062143f | 161 | .name = TYPE_ETRAX_FS_PIC, |
39bffca2 AL |
162 | .parent = TYPE_SYS_BUS_DEVICE, |
163 | .instance_size = sizeof(struct etrax_pic), | |
b46818e9 | 164 | .instance_init = etraxfs_pic_init, |
ee6847d1 GH |
165 | }; |
166 | ||
83f7d43a | 167 | static void etraxfs_pic_register_types(void) |
fd6dc90b | 168 | { |
39bffca2 | 169 | type_register_static(&etraxfs_pic_info); |
fd6dc90b EI |
170 | } |
171 | ||
83f7d43a | 172 | type_init(etraxfs_pic_register_types) |