[mirror_qemu.git] / hw / intc / exynos4210_gic.c

/*
 * Samsung exynos4210 GIC implementation. Based on hw/arm_gic.c
 *
 * Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd.
 * All rights reserved.
 *
 * Evgeny Voevodin <e.voevodin@samsung.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See the GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "hw/sysbus.h"
#include "migration/vmstate.h"
#include "qapi/error.h"
#include "qemu/module.h"
#include "hw/irq.h"
#include "hw/qdev-properties.h"
#include "hw/arm/exynos4210.h"
#include "qom/object.h"

enum ExtGicId {
    EXT_GIC_ID_MDMA_LCD0 = 66,
    EXT_GIC_ID_PDMA0,
    EXT_GIC_ID_PDMA1,
    EXT_GIC_ID_TIMER0,
    EXT_GIC_ID_TIMER1,
    EXT_GIC_ID_TIMER2,
    EXT_GIC_ID_TIMER3,
    EXT_GIC_ID_TIMER4,
    EXT_GIC_ID_MCT_L0,
    EXT_GIC_ID_WDT,
    EXT_GIC_ID_RTC_ALARM,
    EXT_GIC_ID_RTC_TIC,
    EXT_GIC_ID_GPIO_XB,
    EXT_GIC_ID_GPIO_XA,
    EXT_GIC_ID_MCT_L1,
    EXT_GIC_ID_IEM_APC,
    EXT_GIC_ID_IEM_IEC,
    EXT_GIC_ID_NFC,
    EXT_GIC_ID_UART0,
    EXT_GIC_ID_UART1,
    EXT_GIC_ID_UART2,
    EXT_GIC_ID_UART3,
    EXT_GIC_ID_UART4,
    EXT_GIC_ID_MCT_G0,
    EXT_GIC_ID_I2C0,
    EXT_GIC_ID_I2C1,
    EXT_GIC_ID_I2C2,
    EXT_GIC_ID_I2C3,
    EXT_GIC_ID_I2C4,
    EXT_GIC_ID_I2C5,
    EXT_GIC_ID_I2C6,
    EXT_GIC_ID_I2C7,
    EXT_GIC_ID_SPI0,
    EXT_GIC_ID_SPI1,
    EXT_GIC_ID_SPI2,
    EXT_GIC_ID_MCT_G1,
    EXT_GIC_ID_USB_HOST,
    EXT_GIC_ID_USB_DEVICE,
    EXT_GIC_ID_MODEMIF,
    EXT_GIC_ID_HSMMC0,
    EXT_GIC_ID_HSMMC1,
    EXT_GIC_ID_HSMMC2,
    EXT_GIC_ID_HSMMC3,
    EXT_GIC_ID_SDMMC,
    EXT_GIC_ID_MIPI_CSI_4LANE,
    EXT_GIC_ID_MIPI_DSI_4LANE,
    EXT_GIC_ID_MIPI_CSI_2LANE,
    EXT_GIC_ID_MIPI_DSI_2LANE,
    EXT_GIC_ID_ONENAND_AUDI,
    EXT_GIC_ID_ROTATOR,
    EXT_GIC_ID_FIMC0,
    EXT_GIC_ID_FIMC1,
    EXT_GIC_ID_FIMC2,
    EXT_GIC_ID_FIMC3,
    EXT_GIC_ID_JPEG,
    EXT_GIC_ID_2D,
    EXT_GIC_ID_PCIe,
    EXT_GIC_ID_MIXER,
    EXT_GIC_ID_HDMI,
    EXT_GIC_ID_HDMI_I2C,
    EXT_GIC_ID_MFC,
    EXT_GIC_ID_TVENC,
};

enum ExtInt {
    EXT_GIC_ID_EXTINT0 = 48,
    EXT_GIC_ID_EXTINT1,
    EXT_GIC_ID_EXTINT2,
    EXT_GIC_ID_EXTINT3,
    EXT_GIC_ID_EXTINT4,
    EXT_GIC_ID_EXTINT5,
    EXT_GIC_ID_EXTINT6,
    EXT_GIC_ID_EXTINT7,
    EXT_GIC_ID_EXTINT8,
    EXT_GIC_ID_EXTINT9,
    EXT_GIC_ID_EXTINT10,
    EXT_GIC_ID_EXTINT11,
    EXT_GIC_ID_EXTINT12,
    EXT_GIC_ID_EXTINT13,
    EXT_GIC_ID_EXTINT14,
    EXT_GIC_ID_EXTINT15
};

/*
 * External GIC sources which are not from External Interrupt Combiner or
 * External Interrupts are starting from EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ,
 * which is INTG16 in Internal Interrupt Combiner.
 */

static const uint32_t
combiner_grp_to_gic_id[64-EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
    /* int combiner groups 16-19 */
    { }, { }, { }, { },
    /* int combiner group 20 */
    { 0, EXT_GIC_ID_MDMA_LCD0 },
    /* int combiner group 21 */
    { EXT_GIC_ID_PDMA0, EXT_GIC_ID_PDMA1 },
    /* int combiner group 22 */
    { EXT_GIC_ID_TIMER0, EXT_GIC_ID_TIMER1, EXT_GIC_ID_TIMER2,
            EXT_GIC_ID_TIMER3, EXT_GIC_ID_TIMER4 },
    /* int combiner group 23 */
    { EXT_GIC_ID_RTC_ALARM, EXT_GIC_ID_RTC_TIC },
    /* int combiner group 24 */
    { EXT_GIC_ID_GPIO_XB, EXT_GIC_ID_GPIO_XA },
    /* int combiner group 25 */
    { EXT_GIC_ID_IEM_APC, EXT_GIC_ID_IEM_IEC },
    /* int combiner group 26 */
    { EXT_GIC_ID_UART0, EXT_GIC_ID_UART1, EXT_GIC_ID_UART2, EXT_GIC_ID_UART3,
            EXT_GIC_ID_UART4 },
    /* int combiner group 27 */
    { EXT_GIC_ID_I2C0, EXT_GIC_ID_I2C1, EXT_GIC_ID_I2C2, EXT_GIC_ID_I2C3,
            EXT_GIC_ID_I2C4, EXT_GIC_ID_I2C5, EXT_GIC_ID_I2C6,
            EXT_GIC_ID_I2C7 },
    /* int combiner group 28 */
    { EXT_GIC_ID_SPI0, EXT_GIC_ID_SPI1, EXT_GIC_ID_SPI2 , EXT_GIC_ID_USB_HOST},
    /* int combiner group 29 */
    { EXT_GIC_ID_HSMMC0, EXT_GIC_ID_HSMMC1, EXT_GIC_ID_HSMMC2,
     EXT_GIC_ID_HSMMC3, EXT_GIC_ID_SDMMC },
    /* int combiner group 30 */
    { EXT_GIC_ID_MIPI_CSI_4LANE, EXT_GIC_ID_MIPI_CSI_2LANE },
    /* int combiner group 31 */
    { EXT_GIC_ID_MIPI_DSI_4LANE, EXT_GIC_ID_MIPI_DSI_2LANE },
    /* int combiner group 32 */
    { EXT_GIC_ID_FIMC0, EXT_GIC_ID_FIMC1 },
    /* int combiner group 33 */
    { EXT_GIC_ID_FIMC2, EXT_GIC_ID_FIMC3 },
    /* int combiner group 34 */
    { EXT_GIC_ID_ONENAND_AUDI, EXT_GIC_ID_NFC },
    /* int combiner group 35 */
    { 0, 0, 0, EXT_GIC_ID_MCT_L1, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
    /* int combiner group 36 */
    { EXT_GIC_ID_MIXER },
    /* int combiner group 37 */
    { EXT_GIC_ID_EXTINT4, EXT_GIC_ID_EXTINT5, EXT_GIC_ID_EXTINT6,
     EXT_GIC_ID_EXTINT7 },
    /* groups 38-50 */
    { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { },
    /* int combiner group 51 */
    { EXT_GIC_ID_MCT_L0, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
    /* group 52 */
    { },
    /* int combiner group 53 */
    { EXT_GIC_ID_WDT, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
    /* groups 54-63 */
    { }, { }, { }, { }, { }, { }, { }, { }, { }, { }
};

#define EXYNOS4210_GIC_NIRQ 160

#define EXYNOS4210_EXT_GIC_CPU_REGION_SIZE     0x10000
#define EXYNOS4210_EXT_GIC_DIST_REGION_SIZE    0x10000

#define EXYNOS4210_EXT_GIC_PER_CPU_OFFSET      0x8000
#define EXYNOS4210_EXT_GIC_CPU_GET_OFFSET(n) \
    ((n) * EXYNOS4210_EXT_GIC_PER_CPU_OFFSET)
#define EXYNOS4210_EXT_GIC_DIST_GET_OFFSET(n) \
    ((n) * EXYNOS4210_EXT_GIC_PER_CPU_OFFSET)

#define EXYNOS4210_GIC_CPU_REGION_SIZE  0x100
#define EXYNOS4210_GIC_DIST_REGION_SIZE 0x1000

static void exynos4210_irq_handler(void *opaque, int irq, int level)
{
    Exynos4210Irq *s = (Exynos4210Irq *)opaque;

    /* Bypass */
    qemu_set_irq(s->board_irqs[irq], level);
}

/*
 * Initialize exynos4210 IRQ subsystem stub.
 */
qemu_irq *exynos4210_init_irq(Exynos4210Irq *s)
{
    return qemu_allocate_irqs(exynos4210_irq_handler, s,
            EXYNOS4210_MAX_INT_COMBINER_IN_IRQ);
}

/*
 * Initialize board IRQs.
 * These IRQs contain splitted Int/External Combiner and External Gic IRQs.
 */
void exynos4210_init_board_irqs(Exynos4210Irq *s)
{
    uint32_t grp, bit, irq_id, n;

    for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) {
        irq_id = 0;
        if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4) ||
                n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4)) {
            /* MCT_G0 is passed to External GIC */
            irq_id = EXT_GIC_ID_MCT_G0;
        }
        if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5) ||
                n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 5)) {
            /* MCT_G1 is passed to External and GIC */
            irq_id = EXT_GIC_ID_MCT_G1;
        }
        if (irq_id) {
            s->board_irqs[n] = qemu_irq_split(s->int_combiner_irq[n],
                    s->ext_gic_irq[irq_id-32]);
        } else {
            s->board_irqs[n] = qemu_irq_split(s->int_combiner_irq[n],
                    s->ext_combiner_irq[n]);
        }
    }
    for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) {
        /* these IDs are passed to Internal Combiner and External GIC */
        grp = EXYNOS4210_COMBINER_GET_GRP_NUM(n);
        bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n);
        irq_id = combiner_grp_to_gic_id[grp -
                     EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit];

        if (irq_id) {
            s->board_irqs[n] = qemu_irq_split(s->int_combiner_irq[n],
                    s->ext_gic_irq[irq_id-32]);
        }
    }
}

/*
 * Get IRQ number from exynos4210 IRQ subsystem stub.
 * To identify IRQ source use internal combiner group and bit number
 *  grp - group number
 *  bit - bit number inside group
 */
uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit)
{
    return EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit);
}

/********* GIC part *********/

#define TYPE_EXYNOS4210_GIC "exynos4210.gic"
OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210GicState, EXYNOS4210_GIC)

struct Exynos4210GicState {
    SysBusDevice parent_obj;

    MemoryRegion cpu_container;
    MemoryRegion dist_container;
    MemoryRegion cpu_alias[EXYNOS4210_NCPUS];
    MemoryRegion dist_alias[EXYNOS4210_NCPUS];
    uint32_t num_cpu;
    DeviceState *gic;
};

static void exynos4210_gic_set_irq(void *opaque, int irq, int level)
{
    Exynos4210GicState *s = (Exynos4210GicState *)opaque;
    qemu_set_irq(qdev_get_gpio_in(s->gic, irq), level);
}

static void exynos4210_gic_realize(DeviceState *dev, Error **errp)
{
    Object *obj = OBJECT(dev);
    Exynos4210GicState *s = EXYNOS4210_GIC(obj);
    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
    const char cpu_prefix[] = "exynos4210-gic-alias_cpu";
    const char dist_prefix[] = "exynos4210-gic-alias_dist";
    char cpu_alias_name[sizeof(cpu_prefix) + 3];
    char dist_alias_name[sizeof(cpu_prefix) + 3];
    SysBusDevice *gicbusdev;
    uint32_t n = s->num_cpu;
    uint32_t i;

    s->gic = qdev_new("arm_gic");
    qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu);
    qdev_prop_set_uint32(s->gic, "num-irq", EXYNOS4210_GIC_NIRQ);
    gicbusdev = SYS_BUS_DEVICE(s->gic);
    sysbus_realize_and_unref(gicbusdev, &error_fatal);

    /* Pass through outbound IRQ lines from the GIC */
    sysbus_pass_irq(sbd, gicbusdev);

    /* Pass through inbound GPIO lines to the GIC */
    qdev_init_gpio_in(dev, exynos4210_gic_set_irq,
                      EXYNOS4210_GIC_NIRQ - 32);

    memory_region_init(&s->cpu_container, obj, "exynos4210-cpu-container",
            EXYNOS4210_EXT_GIC_CPU_REGION_SIZE);
    memory_region_init(&s->dist_container, obj, "exynos4210-dist-container",
            EXYNOS4210_EXT_GIC_DIST_REGION_SIZE);

    /*
     * This clues in gcc that our on-stack buffers do, in fact have
     * enough room for the cpu numbers.  gcc 9.2.1 on 32-bit x86
     * doesn't figure this out, otherwise and gives spurious warnings.
     */
    assert(n <= EXYNOS4210_NCPUS);
    for (i = 0; i < n; i++) {
        /* Map CPU interface per SMP Core */
        sprintf(cpu_alias_name, "%s%x", cpu_prefix, i);
        memory_region_init_alias(&s->cpu_alias[i], obj,
                                 cpu_alias_name,
                                 sysbus_mmio_get_region(gicbusdev, 1),
                                 0,
                                 EXYNOS4210_GIC_CPU_REGION_SIZE);
        memory_region_add_subregion(&s->cpu_container,
                EXYNOS4210_EXT_GIC_CPU_GET_OFFSET(i), &s->cpu_alias[i]);

        /* Map Distributor per SMP Core */
        sprintf(dist_alias_name, "%s%x", dist_prefix, i);
        memory_region_init_alias(&s->dist_alias[i], obj,
                                 dist_alias_name,
                                 sysbus_mmio_get_region(gicbusdev, 0),
                                 0,
                                 EXYNOS4210_GIC_DIST_REGION_SIZE);
        memory_region_add_subregion(&s->dist_container,
                EXYNOS4210_EXT_GIC_DIST_GET_OFFSET(i), &s->dist_alias[i]);
    }

    sysbus_init_mmio(sbd, &s->cpu_container);
    sysbus_init_mmio(sbd, &s->dist_container);
}

static Property exynos4210_gic_properties[] = {
    DEFINE_PROP_UINT32("num-cpu", Exynos4210GicState, num_cpu, 1),
    DEFINE_PROP_END_OF_LIST(),
};

static void exynos4210_gic_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    device_class_set_props(dc, exynos4210_gic_properties);
    dc->realize = exynos4210_gic_realize;
}

static const TypeInfo exynos4210_gic_info = {
    .name          = TYPE_EXYNOS4210_GIC,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(Exynos4210GicState),
    .class_init    = exynos4210_gic_class_init,
};

static void exynos4210_gic_register_types(void)
{
    type_register_static(&exynos4210_gic_info);
}

type_init(exynos4210_gic_register_types)

/* IRQ OR Gate struct.
 *
 * This device models an OR gate. There are n_in input qdev gpio lines and one
 * output sysbus IRQ line. The output IRQ level is formed as OR between all
 * gpio inputs.
 */

#define TYPE_EXYNOS4210_IRQ_GATE "exynos4210.irq_gate"
OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210IRQGateState, EXYNOS4210_IRQ_GATE)

struct Exynos4210IRQGateState {
    SysBusDevice parent_obj;

    uint32_t n_in;      /* inputs amount */
    uint32_t *level;    /* input levels */
    qemu_irq out;       /* output IRQ */
};

static Property exynos4210_irq_gate_properties[] = {
    DEFINE_PROP_UINT32("n_in", Exynos4210IRQGateState, n_in, 1),
    DEFINE_PROP_END_OF_LIST(),
};

static const VMStateDescription vmstate_exynos4210_irq_gate = {
    .name = "exynos4210.irq_gate",
    .version_id = 2,
    .minimum_version_id = 2,
    .fields = (VMStateField[]) {
        VMSTATE_VBUFFER_UINT32(level, Exynos4210IRQGateState, 1, NULL, n_in),
        VMSTATE_END_OF_LIST()
    }
};

/* Process a change in IRQ input. */
static void exynos4210_irq_gate_handler(void *opaque, int irq, int level)
{
    Exynos4210IRQGateState *s = (Exynos4210IRQGateState *)opaque;
    uint32_t i;

    assert(irq < s->n_in);

    s->level[irq] = level;

    for (i = 0; i < s->n_in; i++) {
        if (s->level[i] >= 1) {
            qemu_irq_raise(s->out);
            return;
        }
    }

    qemu_irq_lower(s->out);
}

static void exynos4210_irq_gate_reset(DeviceState *d)
{
    Exynos4210IRQGateState *s = EXYNOS4210_IRQ_GATE(d);

    memset(s->level, 0, s->n_in * sizeof(*s->level));
}

/*
 * IRQ Gate initialization.
 */
static void exynos4210_irq_gate_init(Object *obj)
{
    Exynos4210IRQGateState *s = EXYNOS4210_IRQ_GATE(obj);
    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);

    sysbus_init_irq(sbd, &s->out);
}

static void exynos4210_irq_gate_realize(DeviceState *dev, Error **errp)
{
    Exynos4210IRQGateState *s = EXYNOS4210_IRQ_GATE(dev);

    /* Allocate general purpose input signals and connect a handler to each of
     * them */
    qdev_init_gpio_in(dev, exynos4210_irq_gate_handler, s->n_in);

    s->level = g_malloc0(s->n_in * sizeof(*s->level));
}

static void exynos4210_irq_gate_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->reset = exynos4210_irq_gate_reset;
    dc->vmsd = &vmstate_exynos4210_irq_gate;
    device_class_set_props(dc, exynos4210_irq_gate_properties);
    dc->realize = exynos4210_irq_gate_realize;
}

static const TypeInfo exynos4210_irq_gate_info = {
    .name          = TYPE_EXYNOS4210_IRQ_GATE,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(Exynos4210IRQGateState),
    .instance_init = exynos4210_irq_gate_init,
    .class_init    = exynos4210_irq_gate_class_init,
};

static void exynos4210_irq_gate_register_types(void)
{
    type_register_static(&exynos4210_irq_gate_info);
}

type_init(exynos4210_irq_gate_register_types)
Commit	Line	Data
8e03cf1e EV	1	/*
	2	* Samsung exynos4210 GIC implementation. Based on hw/arm_gic.c
	3	*
	4	* Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd.
	5	* All rights reserved.
	6	*
	7	* Evgeny Voevodin <e.voevodin@samsung.com>
	8	*
	9	* This program is free software; you can redistribute it and/or modify it
	10	* under the terms of the GNU General Public License as published by the
	11	* Free Software Foundation; either version 2 of the License, or (at your
	12	* option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
	17	* See the GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License along
	20	* with this program; if not, see <http://www.gnu.org/licenses/>.
	21	*/
	22
8ef94f0b	23	#include "qemu/osdep.h"
83c9f4ca	24	#include "hw/sysbus.h"
d6454270	25	#include "migration/vmstate.h"
3e80f690	26	#include "qapi/error.h"
0b8fa32f	27	#include "qemu/module.h"
83c9f4ca	28	#include "hw/irq.h"
a27bd6c7	29	#include "hw/qdev-properties.h"
0d09e41a	30	#include "hw/arm/exynos4210.h"
db1015e9	31	#include "qom/object.h"
8e03cf1e EV	32
	33	enum ExtGicId {
	34	EXT_GIC_ID_MDMA_LCD0 = 66,
	35	EXT_GIC_ID_PDMA0,
	36	EXT_GIC_ID_PDMA1,
	37	EXT_GIC_ID_TIMER0,
	38	EXT_GIC_ID_TIMER1,
	39	EXT_GIC_ID_TIMER2,
	40	EXT_GIC_ID_TIMER3,
	41	EXT_GIC_ID_TIMER4,
	42	EXT_GIC_ID_MCT_L0,
	43	EXT_GIC_ID_WDT,
	44	EXT_GIC_ID_RTC_ALARM,
	45	EXT_GIC_ID_RTC_TIC,
	46	EXT_GIC_ID_GPIO_XB,
	47	EXT_GIC_ID_GPIO_XA,
	48	EXT_GIC_ID_MCT_L1,
	49	EXT_GIC_ID_IEM_APC,
	50	EXT_GIC_ID_IEM_IEC,
	51	EXT_GIC_ID_NFC,
	52	EXT_GIC_ID_UART0,
	53	EXT_GIC_ID_UART1,
	54	EXT_GIC_ID_UART2,
	55	EXT_GIC_ID_UART3,
	56	EXT_GIC_ID_UART4,
	57	EXT_GIC_ID_MCT_G0,
	58	EXT_GIC_ID_I2C0,
	59	EXT_GIC_ID_I2C1,
	60	EXT_GIC_ID_I2C2,
	61	EXT_GIC_ID_I2C3,
	62	EXT_GIC_ID_I2C4,
	63	EXT_GIC_ID_I2C5,
	64	EXT_GIC_ID_I2C6,
	65	EXT_GIC_ID_I2C7,
	66	EXT_GIC_ID_SPI0,
	67	EXT_GIC_ID_SPI1,
	68	EXT_GIC_ID_SPI2,
	69	EXT_GIC_ID_MCT_G1,
	70	EXT_GIC_ID_USB_HOST,
	71	EXT_GIC_ID_USB_DEVICE,
	72	EXT_GIC_ID_MODEMIF,
	73	EXT_GIC_ID_HSMMC0,
	74	EXT_GIC_ID_HSMMC1,
	75	EXT_GIC_ID_HSMMC2,
	76	EXT_GIC_ID_HSMMC3,
	77	EXT_GIC_ID_SDMMC,
	78	EXT_GIC_ID_MIPI_CSI_4LANE,
	79	EXT_GIC_ID_MIPI_DSI_4LANE,
	80	EXT_GIC_ID_MIPI_CSI_2LANE,
	81	EXT_GIC_ID_MIPI_DSI_2LANE,
	82	EXT_GIC_ID_ONENAND_AUDI,
	83	EXT_GIC_ID_ROTATOR,
	84	EXT_GIC_ID_FIMC0,
	85	EXT_GIC_ID_FIMC1,
	86	EXT_GIC_ID_FIMC2,
	87	EXT_GIC_ID_FIMC3,
	88	EXT_GIC_ID_JPEG,
	89	EXT_GIC_ID_2D,
	90	EXT_GIC_ID_PCIe,
	91	EXT_GIC_ID_MIXER,
	92	EXT_GIC_ID_HDMI,
	93	EXT_GIC_ID_HDMI_I2C,
	94	EXT_GIC_ID_MFC,
	95	EXT_GIC_ID_TVENC,
96	};
97
98	enum ExtInt {
99	EXT_GIC_ID_EXTINT0 = 48,
100	EXT_GIC_ID_EXTINT1,
101	EXT_GIC_ID_EXTINT2,
102	EXT_GIC_ID_EXTINT3,
103	EXT_GIC_ID_EXTINT4,
104	EXT_GIC_ID_EXTINT5,
105	EXT_GIC_ID_EXTINT6,
106	EXT_GIC_ID_EXTINT7,
107	EXT_GIC_ID_EXTINT8,
108	EXT_GIC_ID_EXTINT9,
109	EXT_GIC_ID_EXTINT10,
110	EXT_GIC_ID_EXTINT11,
111	EXT_GIC_ID_EXTINT12,
112	EXT_GIC_ID_EXTINT13,
113	EXT_GIC_ID_EXTINT14,
114	EXT_GIC_ID_EXTINT15
115	};
116
117	/*
118	* External GIC sources which are not from External Interrupt Combiner or
119	* External Interrupts are starting from EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ,
120	* which is INTG16 in Internal Interrupt Combiner.
121	*/
122
5f7f22ff	123	static const uint32_t
8e03cf1e EV	124	combiner_grp_to_gic_id[64-EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
	125	/* int combiner groups 16-19 */
	126	{ }, { }, { }, { },
	127	/* int combiner group 20 */
	128	{ 0, EXT_GIC_ID_MDMA_LCD0 },
	129	/* int combiner group 21 */
	130	{ EXT_GIC_ID_PDMA0, EXT_GIC_ID_PDMA1 },
	131	/* int combiner group 22 */
	132	{ EXT_GIC_ID_TIMER0, EXT_GIC_ID_TIMER1, EXT_GIC_ID_TIMER2,
	133	EXT_GIC_ID_TIMER3, EXT_GIC_ID_TIMER4 },
	134	/* int combiner group 23 */
	135	{ EXT_GIC_ID_RTC_ALARM, EXT_GIC_ID_RTC_TIC },
	136	/* int combiner group 24 */
	137	{ EXT_GIC_ID_GPIO_XB, EXT_GIC_ID_GPIO_XA },
	138	/* int combiner group 25 */
	139	{ EXT_GIC_ID_IEM_APC, EXT_GIC_ID_IEM_IEC },
	140	/* int combiner group 26 */
	141	{ EXT_GIC_ID_UART0, EXT_GIC_ID_UART1, EXT_GIC_ID_UART2, EXT_GIC_ID_UART3,
	142	EXT_GIC_ID_UART4 },
	143	/* int combiner group 27 */
	144	{ EXT_GIC_ID_I2C0, EXT_GIC_ID_I2C1, EXT_GIC_ID_I2C2, EXT_GIC_ID_I2C3,
	145	EXT_GIC_ID_I2C4, EXT_GIC_ID_I2C5, EXT_GIC_ID_I2C6,
	146	EXT_GIC_ID_I2C7 },
	147	/* int combiner group 28 */
358d615b	148	{ EXT_GIC_ID_SPI0, EXT_GIC_ID_SPI1, EXT_GIC_ID_SPI2 , EXT_GIC_ID_USB_HOST},
8e03cf1e EV	149	/* int combiner group 29 */
	150	{ EXT_GIC_ID_HSMMC0, EXT_GIC_ID_HSMMC1, EXT_GIC_ID_HSMMC2,
	151	EXT_GIC_ID_HSMMC3, EXT_GIC_ID_SDMMC },
	152	/* int combiner group 30 */
	153	{ EXT_GIC_ID_MIPI_CSI_4LANE, EXT_GIC_ID_MIPI_CSI_2LANE },
	154	/* int combiner group 31 */
	155	{ EXT_GIC_ID_MIPI_DSI_4LANE, EXT_GIC_ID_MIPI_DSI_2LANE },
	156	/* int combiner group 32 */
	157	{ EXT_GIC_ID_FIMC0, EXT_GIC_ID_FIMC1 },
	158	/* int combiner group 33 */
	159	{ EXT_GIC_ID_FIMC2, EXT_GIC_ID_FIMC3 },
	160	/* int combiner group 34 */
	161	{ EXT_GIC_ID_ONENAND_AUDI, EXT_GIC_ID_NFC },
	162	/* int combiner group 35 */
	163	{ 0, 0, 0, EXT_GIC_ID_MCT_L1, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
	164	/* int combiner group 36 */
	165	{ EXT_GIC_ID_MIXER },
	166	/* int combiner group 37 */
	167	{ EXT_GIC_ID_EXTINT4, EXT_GIC_ID_EXTINT5, EXT_GIC_ID_EXTINT6,
	168	EXT_GIC_ID_EXTINT7 },
	169	/* groups 38-50 */
	170	{ }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { },
	171	/* int combiner group 51 */
	172	{ EXT_GIC_ID_MCT_L0, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
	173	/* group 52 */
	174	{ },
	175	/* int combiner group 53 */
	176	{ EXT_GIC_ID_WDT, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
	177	/* groups 54-63 */
	178	{ }, { }, { }, { }, { }, { }, { }, { }, { }, { }
	179	};
	180
	181	#define EXYNOS4210_GIC_NIRQ 160
8e03cf1e EV	182
	183	#define EXYNOS4210_EXT_GIC_CPU_REGION_SIZE 0x10000
	184	#define EXYNOS4210_EXT_GIC_DIST_REGION_SIZE 0x10000
	185
	186	#define EXYNOS4210_EXT_GIC_PER_CPU_OFFSET 0x8000
	187	#define EXYNOS4210_EXT_GIC_CPU_GET_OFFSET(n) \
	188	((n) * EXYNOS4210_EXT_GIC_PER_CPU_OFFSET)
	189	#define EXYNOS4210_EXT_GIC_DIST_GET_OFFSET(n) \
	190	((n) * EXYNOS4210_EXT_GIC_PER_CPU_OFFSET)
	191
	192	#define EXYNOS4210_GIC_CPU_REGION_SIZE 0x100
	193	#define EXYNOS4210_GIC_DIST_REGION_SIZE 0x1000
	194
	195	static void exynos4210_irq_handler(void *opaque, int irq, int level)
	196	{
	197	Exynos4210Irq s = (Exynos4210Irq )opaque;
	198
	199	/* Bypass */
	200	qemu_set_irq(s->board_irqs[irq], level);
8e03cf1e EV	201	}
	202
	203	/*
	204	* Initialize exynos4210 IRQ subsystem stub.
	205	*/
	206	qemu_irq exynos4210_init_irq(Exynos4210Irq s)
	207	{
	208	return qemu_allocate_irqs(exynos4210_irq_handler, s,
	209	EXYNOS4210_MAX_INT_COMBINER_IN_IRQ);
	210	}
	211
	212	/*
	213	* Initialize board IRQs.
	214	* These IRQs contain splitted Int/External Combiner and External Gic IRQs.
	215	*/
	216	void exynos4210_init_board_irqs(Exynos4210Irq *s)
	217	{
	218	uint32_t grp, bit, irq_id, n;
	219
	220	for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) {
8e03cf1e EV	221	irq_id = 0;
	222	if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4) \|\|
	223	n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4)) {
	224	/* MCT_G0 is passed to External GIC */
	225	irq_id = EXT_GIC_ID_MCT_G0;
	226	}
	227	if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5) \|\|
	228	n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 5)) {
	229	/* MCT_G1 is passed to External and GIC */
	230	irq_id = EXT_GIC_ID_MCT_G1;
	231	}
	232	if (irq_id) {
	233	s->board_irqs[n] = qemu_irq_split(s->int_combiner_irq[n],
	234	s->ext_gic_irq[irq_id-32]);
9ff7f5bd SZ	235	} else {
	236	s->board_irqs[n] = qemu_irq_split(s->int_combiner_irq[n],
	237	s->ext_combiner_irq[n]);
8e03cf1e	238	}
8e03cf1e EV	239	}
	240	for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) {
	241	/* these IDs are passed to Internal Combiner and External GIC */
	242	grp = EXYNOS4210_COMBINER_GET_GRP_NUM(n);
	243	bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n);
	244	irq_id = combiner_grp_to_gic_id[grp -
	245	EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit];
	246
	247	if (irq_id) {
	248	s->board_irqs[n] = qemu_irq_split(s->int_combiner_irq[n],
	249	s->ext_gic_irq[irq_id-32]);
	250	}
	251	}
	252	}
	253
	254	/*
	255	* Get IRQ number from exynos4210 IRQ subsystem stub.
	256	* To identify IRQ source use internal combiner group and bit number
	257	* grp - group number
	258	* bit - bit number inside group
	259	*/
	260	uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit)
	261	{
	262	return EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit);
	263	}
	264
	265	/******* GIC part *******/
	266
78c6abbd	267	#define TYPE_EXYNOS4210_GIC "exynos4210.gic"
8063396b	268	OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210GicState, EXYNOS4210_GIC)
78c6abbd	269
db1015e9	270	struct Exynos4210GicState {
78c6abbd AF	271	SysBusDevice parent_obj;
78c6abbd AF	272
8e03cf1e EV	273	MemoryRegion cpu_container;
8e03cf1e EV	274	MemoryRegion dist_container;
386e2955 PM	275	MemoryRegion cpu_alias[EXYNOS4210_NCPUS];
386e2955 PM	276	MemoryRegion dist_alias[EXYNOS4210_NCPUS];
8e03cf1e	277	uint32_t num_cpu;
23b92f60	278	DeviceState *gic;
db1015e9	279	};
8e03cf1e	280
23b92f60 PM	281	static void exynos4210_gic_set_irq(void *opaque, int irq, int level)
	282	{
	283	Exynos4210GicState s = (Exynos4210GicState )opaque;
	284	qemu_set_irq(qdev_get_gpio_in(s->gic, irq), level);
	285	}
	286
1ddc9b98	287	static void exynos4210_gic_realize(DeviceState dev, Error *errp)
8e03cf1e	288	{
1ddc9b98	289	Object *obj = OBJECT(dev);
68d71616 XZ	290	Exynos4210GicState *s = EXYNOS4210_GIC(obj);
68d71616 XZ	291	SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
8e03cf1e EV	292	const char cpu_prefix[] = "exynos4210-gic-alias_cpu";
	293	const char dist_prefix[] = "exynos4210-gic-alias_dist";
	294	char cpu_alias_name[sizeof(cpu_prefix) + 3];
	295	char dist_alias_name[sizeof(cpu_prefix) + 3];
ee78356e	296	SysBusDevice *gicbusdev;
16250732	297	uint32_t n = s->num_cpu;
ee78356e	298	uint32_t i;
23b92f60	299
3e80f690	300	s->gic = qdev_new("arm_gic");
23b92f60 PM	301	qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu);
23b92f60 PM	302	qdev_prop_set_uint32(s->gic, "num-irq", EXYNOS4210_GIC_NIRQ);
ee78356e	303	gicbusdev = SYS_BUS_DEVICE(s->gic);
3c6ef471	304	sysbus_realize_and_unref(gicbusdev, &error_fatal);
23b92f60 PM	305
23b92f60 PM	306	/* Pass through outbound IRQ lines from the GIC */
ee78356e	307	sysbus_pass_irq(sbd, gicbusdev);
8e03cf1e	308
23b92f60	309	/* Pass through inbound GPIO lines to the GIC */
78c6abbd	310	qdev_init_gpio_in(dev, exynos4210_gic_set_irq,
23b92f60	311	EXYNOS4210_GIC_NIRQ - 32);
8e03cf1e	312
68d71616	313	memory_region_init(&s->cpu_container, obj, "exynos4210-cpu-container",
8e03cf1e	314	EXYNOS4210_EXT_GIC_CPU_REGION_SIZE);
68d71616	315	memory_region_init(&s->dist_container, obj, "exynos4210-dist-container",
8e03cf1e EV	316	EXYNOS4210_EXT_GIC_DIST_REGION_SIZE);
8e03cf1e EV	317
16250732 DG	318	/*
	319	* This clues in gcc that our on-stack buffers do, in fact have
	320	* enough room for the cpu numbers. gcc 9.2.1 on 32-bit x86
	321	* doesn't figure this out, otherwise and gives spurious warnings.
	322	*/
	323	assert(n <= EXYNOS4210_NCPUS);
	324	for (i = 0; i < n; i++) {
8e03cf1e EV	325	/* Map CPU interface per SMP Core */
8e03cf1e EV	326	sprintf(cpu_alias_name, "%s%x", cpu_prefix, i);
68d71616	327	memory_region_init_alias(&s->cpu_alias[i], obj,
8e03cf1e	328	cpu_alias_name,
ee78356e	329	sysbus_mmio_get_region(gicbusdev, 1),
8e03cf1e EV	330	0,
	331	EXYNOS4210_GIC_CPU_REGION_SIZE);
	332	memory_region_add_subregion(&s->cpu_container,
	333	EXYNOS4210_EXT_GIC_CPU_GET_OFFSET(i), &s->cpu_alias[i]);
	334
	335	/* Map Distributor per SMP Core */
	336	sprintf(dist_alias_name, "%s%x", dist_prefix, i);
68d71616	337	memory_region_init_alias(&s->dist_alias[i], obj,
8e03cf1e	338	dist_alias_name,
ee78356e	339	sysbus_mmio_get_region(gicbusdev, 0),
8e03cf1e EV	340	0,
	341	EXYNOS4210_GIC_DIST_REGION_SIZE);
	342	memory_region_add_subregion(&s->dist_container,
	343	EXYNOS4210_EXT_GIC_DIST_GET_OFFSET(i), &s->dist_alias[i]);
	344	}
	345
78c6abbd AF	346	sysbus_init_mmio(sbd, &s->cpu_container);
78c6abbd AF	347	sysbus_init_mmio(sbd, &s->dist_container);
8e03cf1e EV	348	}
	349
	350	static Property exynos4210_gic_properties[] = {
	351	DEFINE_PROP_UINT32("num-cpu", Exynos4210GicState, num_cpu, 1),
	352	DEFINE_PROP_END_OF_LIST(),
	353	};
	354
	355	static void exynos4210_gic_class_init(ObjectClass klass, void data)
	356	{
	357	DeviceClass *dc = DEVICE_CLASS(klass);
8e03cf1e	358
4f67d30b	359	device_class_set_props(dc, exynos4210_gic_properties);
1ddc9b98	360	dc->realize = exynos4210_gic_realize;
8e03cf1e EV	361	}
8e03cf1e EV	362
8c43a6f0	363	static const TypeInfo exynos4210_gic_info = {
78c6abbd	364	.name = TYPE_EXYNOS4210_GIC,
8e03cf1e EV	365	.parent = TYPE_SYS_BUS_DEVICE,
	366	.instance_size = sizeof(Exynos4210GicState),
	367	.class_init = exynos4210_gic_class_init,
	368	};
	369
	370	static void exynos4210_gic_register_types(void)
	371	{
	372	type_register_static(&exynos4210_gic_info);
	373	}
	374
	375	type_init(exynos4210_gic_register_types)
	376
61558e7a EV	377	/* IRQ OR Gate struct.
	378	*
	379	* This device models an OR gate. There are n_in input qdev gpio lines and one
	380	* output sysbus IRQ line. The output IRQ level is formed as OR between all
	381	* gpio inputs.
8e03cf1e	382	*/
c5e22ae3 AF	383
c5e22ae3 AF	384	#define TYPE_EXYNOS4210_IRQ_GATE "exynos4210.irq_gate"
8063396b	385	OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210IRQGateState, EXYNOS4210_IRQ_GATE)
c5e22ae3	386
db1015e9	387	struct Exynos4210IRQGateState {
c5e22ae3	388	SysBusDevice parent_obj;
8e03cf1e	389
61558e7a EV	390	uint32_t n_in; /* inputs amount */
	391	uint32_t level; / input levels */
	392	qemu_irq out; /* output IRQ */
db1015e9	393	};
8e03cf1e	394
61558e7a EV	395	static Property exynos4210_irq_gate_properties[] = {
	396	DEFINE_PROP_UINT32("n_in", Exynos4210IRQGateState, n_in, 1),
	397	DEFINE_PROP_END_OF_LIST(),
	398	};
	399
8e03cf1e EV	400	static const VMStateDescription vmstate_exynos4210_irq_gate = {
8e03cf1e EV	401	.name = "exynos4210.irq_gate",
61558e7a EV	402	.version_id = 2,
61558e7a EV	403	.minimum_version_id = 2,
8e03cf1e	404	.fields = (VMStateField[]) {
59046ec2	405	VMSTATE_VBUFFER_UINT32(level, Exynos4210IRQGateState, 1, NULL, n_in),
8e03cf1e EV	406	VMSTATE_END_OF_LIST()
	407	}
	408	};
	409
61558e7a	410	/* Process a change in IRQ input. */
8e03cf1e EV	411	static void exynos4210_irq_gate_handler(void *opaque, int irq, int level)
8e03cf1e EV	412	{
61558e7a EV	413	Exynos4210IRQGateState s = (Exynos4210IRQGateState )opaque;
61558e7a EV	414	uint32_t i;
8e03cf1e	415
61558e7a	416	assert(irq < s->n_in);
8e03cf1e	417
61558e7a EV	418	s->level[irq] = level;
	419
	420	for (i = 0; i < s->n_in; i++) {
	421	if (s->level[i] >= 1) {
	422	qemu_irq_raise(s->out);
	423	return;
	424	}
8e03cf1e EV	425	}
8e03cf1e EV	426
61558e7a	427	qemu_irq_lower(s->out);
8e03cf1e EV	428	}
	429
	430	static void exynos4210_irq_gate_reset(DeviceState *d)
	431	{
c5e22ae3	432	Exynos4210IRQGateState *s = EXYNOS4210_IRQ_GATE(d);
8e03cf1e	433
61558e7a	434	memset(s->level, 0, s->n_in * sizeof(*s->level));
8e03cf1e EV	435	}
	436
	437	/*
	438	* IRQ Gate initialization.
	439	*/
68d71616 XZ	440	static void exynos4210_irq_gate_init(Object *obj)
	441	{
	442	Exynos4210IRQGateState *s = EXYNOS4210_IRQ_GATE(obj);
	443	SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
	444
	445	sysbus_init_irq(sbd, &s->out);
	446	}
	447
	448	static void exynos4210_irq_gate_realize(DeviceState dev, Error *errp)
8e03cf1e	449	{
c5e22ae3	450	Exynos4210IRQGateState *s = EXYNOS4210_IRQ_GATE(dev);
8e03cf1e EV	451
	452	/* Allocate general purpose input signals and connect a handler to each of
	453	* them */
c5e22ae3	454	qdev_init_gpio_in(dev, exynos4210_irq_gate_handler, s->n_in);
8e03cf1e	455
61558e7a	456	s->level = g_malloc0(s->n_in * sizeof(*s->level));
8e03cf1e EV	457	}
	458
	459	static void exynos4210_irq_gate_class_init(ObjectClass klass, void data)
	460	{
	461	DeviceClass *dc = DEVICE_CLASS(klass);
8e03cf1e	462
8e03cf1e EV	463	dc->reset = exynos4210_irq_gate_reset;
8e03cf1e EV	464	dc->vmsd = &vmstate_exynos4210_irq_gate;
4f67d30b	465	device_class_set_props(dc, exynos4210_irq_gate_properties);
68d71616	466	dc->realize = exynos4210_irq_gate_realize;
8e03cf1e EV	467	}
8e03cf1e EV	468
8c43a6f0	469	static const TypeInfo exynos4210_irq_gate_info = {
c5e22ae3	470	.name = TYPE_EXYNOS4210_IRQ_GATE,
8e03cf1e EV	471	.parent = TYPE_SYS_BUS_DEVICE,
8e03cf1e EV	472	.instance_size = sizeof(Exynos4210IRQGateState),
68d71616	473	.instance_init = exynos4210_irq_gate_init,
8e03cf1e EV	474	.class_init = exynos4210_irq_gate_class_init,
	475	};
	476
	477	static void exynos4210_irq_gate_register_types(void)
	478	{
	479	type_register_static(&exynos4210_irq_gate_info);
	480	}
	481
	482	type_init(exynos4210_irq_gate_register_types)