[mirror_qemu.git] / hw / intc / grlib_irqmp.c

/*
 * QEMU GRLIB IRQMP Emulator
 *
 * (Multiprocessor and extended interrupt not supported)
 *
 * Copyright (c) 2010-2011 AdaCore
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "qemu/osdep.h"
#include "hw/sysbus.h"
#include "cpu.h"

#include "hw/sparc/grlib.h"

#include "trace.h"

#define IRQMP_MAX_CPU 16
#define IRQMP_REG_SIZE 256      /* Size of memory mapped registers */

/* Memory mapped register offsets */
#define LEVEL_OFFSET     0x00
#define PENDING_OFFSET   0x04
#define FORCE0_OFFSET    0x08
#define CLEAR_OFFSET     0x0C
#define MP_STATUS_OFFSET 0x10
#define BROADCAST_OFFSET 0x14
#define MASK_OFFSET      0x40
#define FORCE_OFFSET     0x80
#define EXTENDED_OFFSET  0xC0

#define TYPE_GRLIB_IRQMP "grlib,irqmp"
#define GRLIB_IRQMP(obj) OBJECT_CHECK(IRQMP, (obj), TYPE_GRLIB_IRQMP)

typedef struct IRQMPState IRQMPState;

typedef struct IRQMP {
    SysBusDevice parent_obj;

    MemoryRegion iomem;

    void *set_pil_in;
    void *set_pil_in_opaque;

    IRQMPState *state;
} IRQMP;

struct IRQMPState {
    uint32_t level;
    uint32_t pending;
    uint32_t clear;
    uint32_t broadcast;

    uint32_t mask[IRQMP_MAX_CPU];
    uint32_t force[IRQMP_MAX_CPU];
    uint32_t extended[IRQMP_MAX_CPU];

    IRQMP    *parent;
};

static void grlib_irqmp_check_irqs(IRQMPState *state)
{
    uint32_t      pend   = 0;
    uint32_t      level0 = 0;
    uint32_t      level1 = 0;
    set_pil_in_fn set_pil_in;

    assert(state != NULL);
    assert(state->parent != NULL);

    /* IRQ for CPU 0 (no SMP support) */
    pend = (state->pending | state->force[0])
        & state->mask[0];

    level0 = pend & ~state->level;
    level1 = pend &  state->level;

    trace_grlib_irqmp_check_irqs(state->pending, state->force[0],
                                 state->mask[0], level1, level0);

    set_pil_in = (set_pil_in_fn)state->parent->set_pil_in;

    /* Trigger level1 interrupt first and level0 if there is no level1 */
    if (level1 != 0) {
        set_pil_in(state->parent->set_pil_in_opaque, level1);
    } else {
        set_pil_in(state->parent->set_pil_in_opaque, level0);
    }
}

void grlib_irqmp_ack(DeviceState *dev, int intno)
{
    IRQMP        *irqmp = GRLIB_IRQMP(dev);
    IRQMPState   *state;
    uint32_t      mask;

    state = irqmp->state;
    assert(state != NULL);

    intno &= 15;
    mask = 1 << intno;

    trace_grlib_irqmp_ack(intno);

    /* Clear registers */
    state->pending  &= ~mask;
    state->force[0] &= ~mask; /* Only CPU 0 (No SMP support) */

    grlib_irqmp_check_irqs(state);
}

void grlib_irqmp_set_irq(void *opaque, int irq, int level)
{
    IRQMP      *irqmp = GRLIB_IRQMP(opaque);
    IRQMPState *s;
    int         i = 0;

    s = irqmp->state;
    assert(s         != NULL);
    assert(s->parent != NULL);


    if (level) {
        trace_grlib_irqmp_set_irq(irq);

        if (s->broadcast & 1 << irq) {
            /* Broadcasted IRQ */
            for (i = 0; i < IRQMP_MAX_CPU; i++) {
                s->force[i] |= 1 << irq;
            }
        } else {
            s->pending |= 1 << irq;
        }
        grlib_irqmp_check_irqs(s);

    }
}

static uint64_t grlib_irqmp_read(void *opaque, hwaddr addr,
                                 unsigned size)
{
    IRQMP      *irqmp = opaque;
    IRQMPState *state;

    assert(irqmp != NULL);
    state = irqmp->state;
    assert(state != NULL);

    addr &= 0xff;

    /* global registers */
    switch (addr) {
    case LEVEL_OFFSET:
        return state->level;

    case PENDING_OFFSET:
        return state->pending;

    case FORCE0_OFFSET:
        /* This register is an "alias" for the force register of CPU 0 */
        return state->force[0];

    case CLEAR_OFFSET:
    case MP_STATUS_OFFSET:
        /* Always read as 0 */
        return 0;

    case BROADCAST_OFFSET:
        return state->broadcast;

    default:
        break;
    }

    /* mask registers */
    if (addr >= MASK_OFFSET && addr < FORCE_OFFSET) {
        int cpu = (addr - MASK_OFFSET) / 4;
        assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);

        return state->mask[cpu];
    }

    /* force registers */
    if (addr >= FORCE_OFFSET && addr < EXTENDED_OFFSET) {
        int cpu = (addr - FORCE_OFFSET) / 4;
        assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);

        return state->force[cpu];
    }

    /* extended (not supported) */
    if (addr >= EXTENDED_OFFSET && addr < IRQMP_REG_SIZE) {
        int cpu = (addr - EXTENDED_OFFSET) / 4;
        assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);

        return state->extended[cpu];
    }

    trace_grlib_irqmp_readl_unknown(addr);
    return 0;
}

static void grlib_irqmp_write(void *opaque, hwaddr addr,
                              uint64_t value, unsigned size)
{
    IRQMP      *irqmp = opaque;
    IRQMPState *state;

    assert(irqmp != NULL);
    state = irqmp->state;
    assert(state != NULL);

    addr &= 0xff;

    /* global registers */
    switch (addr) {
    case LEVEL_OFFSET:
        value &= 0xFFFF << 1; /* clean up the value */
        state->level = value;
        return;

    case PENDING_OFFSET:
        /* Read Only */
        return;

    case FORCE0_OFFSET:
        /* This register is an "alias" for the force register of CPU 0 */

        value &= 0xFFFE; /* clean up the value */
        state->force[0] = value;
        grlib_irqmp_check_irqs(irqmp->state);
        return;

    case CLEAR_OFFSET:
        value &= ~1; /* clean up the value */
        state->pending &= ~value;
        return;

    case MP_STATUS_OFFSET:
        /* Read Only (no SMP support) */
        return;

    case BROADCAST_OFFSET:
        value &= 0xFFFE; /* clean up the value */
        state->broadcast = value;
        return;

    default:
        break;
    }

    /* mask registers */
    if (addr >= MASK_OFFSET && addr < FORCE_OFFSET) {
        int cpu = (addr - MASK_OFFSET) / 4;
        assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);

        value &= ~1; /* clean up the value */
        state->mask[cpu] = value;
        grlib_irqmp_check_irqs(irqmp->state);
        return;
    }

    /* force registers */
    if (addr >= FORCE_OFFSET && addr < EXTENDED_OFFSET) {
        int cpu = (addr - FORCE_OFFSET) / 4;
        assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);

        uint32_t force = value & 0xFFFE;
        uint32_t clear = (value >> 16) & 0xFFFE;
        uint32_t old   = state->force[cpu];

        state->force[cpu] = (old | force) & ~clear;
        grlib_irqmp_check_irqs(irqmp->state);
        return;
    }

    /* extended (not supported) */
    if (addr >= EXTENDED_OFFSET && addr < IRQMP_REG_SIZE) {
        int cpu = (addr - EXTENDED_OFFSET) / 4;
        assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);

        value &= 0xF; /* clean up the value */
        state->extended[cpu] = value;
        return;
    }

    trace_grlib_irqmp_writel_unknown(addr, value);
}

static const MemoryRegionOps grlib_irqmp_ops = {
    .read = grlib_irqmp_read,
    .write = grlib_irqmp_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
    .valid = {
        .min_access_size = 4,
        .max_access_size = 4,
    },
};

static void grlib_irqmp_reset(DeviceState *d)
{
    IRQMP *irqmp = GRLIB_IRQMP(d);
    assert(irqmp->state != NULL);

    memset(irqmp->state, 0, sizeof *irqmp->state);
    irqmp->state->parent = irqmp;
}

static int grlib_irqmp_init(SysBusDevice *dev)
{
    IRQMP *irqmp = GRLIB_IRQMP(dev);

    /* Check parameters */
    if (irqmp->set_pil_in == NULL) {
        return -1;
    }

    memory_region_init_io(&irqmp->iomem, OBJECT(dev), &grlib_irqmp_ops, irqmp,
                          "irqmp", IRQMP_REG_SIZE);

    irqmp->state = g_malloc0(sizeof *irqmp->state);

    sysbus_init_mmio(dev, &irqmp->iomem);

    return 0;
}

static Property grlib_irqmp_properties[] = {
    DEFINE_PROP_PTR("set_pil_in", IRQMP, set_pil_in),
    DEFINE_PROP_PTR("set_pil_in_opaque", IRQMP, set_pil_in_opaque),
    DEFINE_PROP_END_OF_LIST(),
};

static void grlib_irqmp_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);

    k->init = grlib_irqmp_init;
    dc->reset = grlib_irqmp_reset;
    dc->props = grlib_irqmp_properties;
    /* Reason: pointer properties "set_pil_in", "set_pil_in_opaque" */
    dc->cannot_instantiate_with_device_add_yet = true;
}

static const TypeInfo grlib_irqmp_info = {
    .name          = TYPE_GRLIB_IRQMP,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(IRQMP),
    .class_init    = grlib_irqmp_class_init,
};

static void grlib_irqmp_register_types(void)
{
    type_register_static(&grlib_irqmp_info);
}

type_init(grlib_irqmp_register_types)
Commit	Line	Data
3f10bcbb FC	1	/*
	2	* QEMU GRLIB IRQMP Emulator
	3	*
	4	* (Multiprocessor and extended interrupt not supported)
	5	*
	6	* Copyright (c) 2010-2011 AdaCore
	7	*
	8	* Permission is hereby granted, free of charge, to any person obtaining a copy
	9	* of this software and associated documentation files (the "Software"), to deal
	10	* in the Software without restriction, including without limitation the rights
	11	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	12	* copies of the Software, and to permit persons to whom the Software is
	13	* furnished to do so, subject to the following conditions:
	14	*
	15	* The above copyright notice and this permission notice shall be included in
	16	* all copies or substantial portions of the Software.
	17	*
	18	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	19	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	20	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	21	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	22	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	23	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	24	* THE SOFTWARE.
	25	*/
	26
db5ebe5f	27	#include "qemu/osdep.h"
83c9f4ca	28	#include "hw/sysbus.h"
3f10bcbb FC	29	#include "cpu.h"
3f10bcbb FC	30
0d09e41a	31	#include "hw/sparc/grlib.h"
3f10bcbb FC	32
	33	#include "trace.h"
	34
	35	#define IRQMP_MAX_CPU 16
	36	#define IRQMP_REG_SIZE 256 /* Size of memory mapped registers */
	37
	38	/* Memory mapped register offsets */
	39	#define LEVEL_OFFSET 0x00
	40	#define PENDING_OFFSET 0x04
	41	#define FORCE0_OFFSET 0x08
	42	#define CLEAR_OFFSET 0x0C
	43	#define MP_STATUS_OFFSET 0x10
	44	#define BROADCAST_OFFSET 0x14
	45	#define MASK_OFFSET 0x40
	46	#define FORCE_OFFSET 0x80
	47	#define EXTENDED_OFFSET 0xC0
	48
730bf932 AF	49	#define TYPE_GRLIB_IRQMP "grlib,irqmp"
	50	#define GRLIB_IRQMP(obj) OBJECT_CHECK(IRQMP, (obj), TYPE_GRLIB_IRQMP)
	51
3f10bcbb FC	52	typedef struct IRQMPState IRQMPState;
	53
	54	typedef struct IRQMP {
730bf932 AF	55	SysBusDevice parent_obj;
730bf932 AF	56
847b52c1	57	MemoryRegion iomem;
3f10bcbb FC	58
	59	void *set_pil_in;
	60	void *set_pil_in_opaque;
	61
	62	IRQMPState *state;
	63	} IRQMP;
	64
	65	struct IRQMPState {
	66	uint32_t level;
	67	uint32_t pending;
	68	uint32_t clear;
	69	uint32_t broadcast;
	70
	71	uint32_t mask[IRQMP_MAX_CPU];
	72	uint32_t force[IRQMP_MAX_CPU];
	73	uint32_t extended[IRQMP_MAX_CPU];
	74
	75	IRQMP *parent;
	76	};
	77
	78	static void grlib_irqmp_check_irqs(IRQMPState *state)
	79	{
	80	uint32_t pend = 0;
	81	uint32_t level0 = 0;
	82	uint32_t level1 = 0;
	83	set_pil_in_fn set_pil_in;
	84
	85	assert(state != NULL);
	86	assert(state->parent != NULL);
	87
	88	/* IRQ for CPU 0 (no SMP support) */
	89	pend = (state->pending \| state->force[0])
	90	& state->mask[0];
	91
	92	level0 = pend & ~state->level;
	93	level1 = pend & state->level;
	94
	95	trace_grlib_irqmp_check_irqs(state->pending, state->force[0],
	96	state->mask[0], level1, level0);
	97
	98	set_pil_in = (set_pil_in_fn)state->parent->set_pil_in;
	99
	100	/* Trigger level1 interrupt first and level0 if there is no level1 */
	101	if (level1 != 0) {
	102	set_pil_in(state->parent->set_pil_in_opaque, level1);
	103	} else {
	104	set_pil_in(state->parent->set_pil_in_opaque, level0);
	105	}
	106	}
	107
	108	void grlib_irqmp_ack(DeviceState *dev, int intno)
	109	{
730bf932	110	IRQMP *irqmp = GRLIB_IRQMP(dev);
3f10bcbb FC	111	IRQMPState *state;
	112	uint32_t mask;
	113
3f10bcbb FC	114	state = irqmp->state;
	115	assert(state != NULL);
	116
	117	intno &= 15;
	118	mask = 1 << intno;
	119
	120	trace_grlib_irqmp_ack(intno);
	121
	122	/* Clear registers */
	123	state->pending &= ~mask;
	124	state->force[0] &= ~mask; /* Only CPU 0 (No SMP support) */
	125
	126	grlib_irqmp_check_irqs(state);
	127	}
	128
	129	void grlib_irqmp_set_irq(void *opaque, int irq, int level)
	130	{
730bf932	131	IRQMP *irqmp = GRLIB_IRQMP(opaque);
3f10bcbb FC	132	IRQMPState *s;
	133	int i = 0;
	134
3f10bcbb FC	135	s = irqmp->state;
	136	assert(s != NULL);
	137	assert(s->parent != NULL);
	138
	139
	140	if (level) {
	141	trace_grlib_irqmp_set_irq(irq);
	142
	143	if (s->broadcast & 1 << irq) {
	144	/* Broadcasted IRQ */
	145	for (i = 0; i < IRQMP_MAX_CPU; i++) {
	146	s->force[i] \|= 1 << irq;
	147	}
	148	} else {
	149	s->pending \|= 1 << irq;
	150	}
	151	grlib_irqmp_check_irqs(s);
	152
	153	}
	154	}
	155
a8170e5e	156	static uint64_t grlib_irqmp_read(void *opaque, hwaddr addr,
847b52c1	157	unsigned size)
3f10bcbb FC	158	{
	159	IRQMP *irqmp = opaque;
	160	IRQMPState *state;
	161
	162	assert(irqmp != NULL);
	163	state = irqmp->state;
	164	assert(state != NULL);
	165
	166	addr &= 0xff;
	167
	168	/* global registers */
	169	switch (addr) {
	170	case LEVEL_OFFSET:
	171	return state->level;
	172
	173	case PENDING_OFFSET:
	174	return state->pending;
	175
	176	case FORCE0_OFFSET:
	177	/* This register is an "alias" for the force register of CPU 0 */
	178	return state->force[0];
	179
	180	case CLEAR_OFFSET:
	181	case MP_STATUS_OFFSET:
	182	/* Always read as 0 */
	183	return 0;
	184
	185	case BROADCAST_OFFSET:
	186	return state->broadcast;
	187
	188	default:
	189	break;
	190	}
	191
	192	/* mask registers */
	193	if (addr >= MASK_OFFSET && addr < FORCE_OFFSET) {
	194	int cpu = (addr - MASK_OFFSET) / 4;
	195	assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);
	196
	197	return state->mask[cpu];
	198	}
	199
	200	/* force registers */
	201	if (addr >= FORCE_OFFSET && addr < EXTENDED_OFFSET) {
	202	int cpu = (addr - FORCE_OFFSET) / 4;
	203	assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);
	204
	205	return state->force[cpu];
	206	}
	207
	208	/* extended (not supported) */
	209	if (addr >= EXTENDED_OFFSET && addr < IRQMP_REG_SIZE) {
	210	int cpu = (addr - EXTENDED_OFFSET) / 4;
	211	assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);
	212
	213	return state->extended[cpu];
	214	}
	215
b4548fcc	216	trace_grlib_irqmp_readl_unknown(addr);
3f10bcbb FC	217	return 0;
	218	}
	219
a8170e5e	220	static void grlib_irqmp_write(void *opaque, hwaddr addr,
847b52c1	221	uint64_t value, unsigned size)
3f10bcbb FC	222	{
	223	IRQMP *irqmp = opaque;
	224	IRQMPState *state;
	225
	226	assert(irqmp != NULL);
	227	state = irqmp->state;
	228	assert(state != NULL);
	229
	230	addr &= 0xff;
	231
	232	/* global registers */
	233	switch (addr) {
	234	case LEVEL_OFFSET:
	235	value &= 0xFFFF << 1; /* clean up the value */
	236	state->level = value;
	237	return;
	238
	239	case PENDING_OFFSET:
	240	/* Read Only */
	241	return;
	242
	243	case FORCE0_OFFSET:
	244	/* This register is an "alias" for the force register of CPU 0 */
	245
	246	value &= 0xFFFE; /* clean up the value */
	247	state->force[0] = value;
	248	grlib_irqmp_check_irqs(irqmp->state);
	249	return;
	250
	251	case CLEAR_OFFSET:
	252	value &= ~1; /* clean up the value */
	253	state->pending &= ~value;
	254	return;
	255
	256	case MP_STATUS_OFFSET:
	257	/* Read Only (no SMP support) */
	258	return;
	259
	260	case BROADCAST_OFFSET:
	261	value &= 0xFFFE; /* clean up the value */
	262	state->broadcast = value;
	263	return;
	264
	265	default:
	266	break;
	267	}
	268
	269	/* mask registers */
	270	if (addr >= MASK_OFFSET && addr < FORCE_OFFSET) {
	271	int cpu = (addr - MASK_OFFSET) / 4;
	272	assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);
	273
	274	value &= ~1; /* clean up the value */
	275	state->mask[cpu] = value;
	276	grlib_irqmp_check_irqs(irqmp->state);
	277	return;
	278	}
	279
	280	/* force registers */
	281	if (addr >= FORCE_OFFSET && addr < EXTENDED_OFFSET) {
	282	int cpu = (addr - FORCE_OFFSET) / 4;
	283	assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);
	284
	285	uint32_t force = value & 0xFFFE;
286	uint32_t clear = (value >> 16) & 0xFFFE;
287	uint32_t old = state->force[cpu];
288
289	state->force[cpu] = (old \| force) & ~clear;
290	grlib_irqmp_check_irqs(irqmp->state);
291	return;
292	}
293
294	/* extended (not supported) */
295	if (addr >= EXTENDED_OFFSET && addr < IRQMP_REG_SIZE) {
296	int cpu = (addr - EXTENDED_OFFSET) / 4;
297	assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);
298
299	value &= 0xF; /* clean up the value */
300	state->extended[cpu] = value;
301	return;
302	}
303
b4548fcc	304	trace_grlib_irqmp_writel_unknown(addr, value);
3f10bcbb FC	305	}
3f10bcbb FC	306
847b52c1 AK	307	static const MemoryRegionOps grlib_irqmp_ops = {
	308	.read = grlib_irqmp_read,
	309	.write = grlib_irqmp_write,
	310	.endianness = DEVICE_NATIVE_ENDIAN,
	311	.valid = {
	312	.min_access_size = 4,
	313	.max_access_size = 4,
	314	},
3f10bcbb FC	315	};
	316
	317	static void grlib_irqmp_reset(DeviceState *d)
	318	{
730bf932	319	IRQMP *irqmp = GRLIB_IRQMP(d);
3f10bcbb FC	320	assert(irqmp->state != NULL);
	321
	322	memset(irqmp->state, 0, sizeof *irqmp->state);
	323	irqmp->state->parent = irqmp;
	324	}
	325
	326	static int grlib_irqmp_init(SysBusDevice *dev)
	327	{
730bf932	328	IRQMP *irqmp = GRLIB_IRQMP(dev);
3f10bcbb FC	329
	330	/* Check parameters */
	331	if (irqmp->set_pil_in == NULL) {
	332	return -1;
	333	}
	334
1437c94b	335	memory_region_init_io(&irqmp->iomem, OBJECT(dev), &grlib_irqmp_ops, irqmp,
847b52c1	336	"irqmp", IRQMP_REG_SIZE);
3f10bcbb	337
7267c094	338	irqmp->state = g_malloc0(sizeof *irqmp->state);
3f10bcbb	339
750ecd44	340	sysbus_init_mmio(dev, &irqmp->iomem);
3f10bcbb FC	341
	342	return 0;
	343	}
	344
999e12bb AL	345	static Property grlib_irqmp_properties[] = {
	346	DEFINE_PROP_PTR("set_pil_in", IRQMP, set_pil_in),
	347	DEFINE_PROP_PTR("set_pil_in_opaque", IRQMP, set_pil_in_opaque),
	348	DEFINE_PROP_END_OF_LIST(),
	349	};
	350
	351	static void grlib_irqmp_class_init(ObjectClass klass, void data)
	352	{
39bffca2	353	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	354	SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
	355
	356	k->init = grlib_irqmp_init;
39bffca2 AL	357	dc->reset = grlib_irqmp_reset;
39bffca2 AL	358	dc->props = grlib_irqmp_properties;
1b111dc1 MA	359	/* Reason: pointer properties "set_pil_in", "set_pil_in_opaque" */
1b111dc1 MA	360	dc->cannot_instantiate_with_device_add_yet = true;
999e12bb AL	361	}
999e12bb AL	362
8c43a6f0	363	static const TypeInfo grlib_irqmp_info = {
730bf932	364	.name = TYPE_GRLIB_IRQMP,
39bffca2 AL	365	.parent = TYPE_SYS_BUS_DEVICE,
	366	.instance_size = sizeof(IRQMP),
	367	.class_init = grlib_irqmp_class_init,
3f10bcbb FC	368	};
3f10bcbb FC	369
83f7d43a	370	static void grlib_irqmp_register_types(void)
3f10bcbb	371	{
39bffca2	372	type_register_static(&grlib_irqmp_info);
3f10bcbb FC	373	}
3f10bcbb FC	374
83f7d43a	375	type_init(grlib_irqmp_register_types)