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Commit | Line | Data |
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80cabfad FB |
1 | /* |
2 | * QEMU 8259 interrupt controller emulation | |
5fafdf24 | 3 | * |
80cabfad | 4 | * Copyright (c) 2003-2004 Fabrice Bellard |
5fafdf24 | 5 | * |
80cabfad FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
64552b6b | 24 | |
90191d07 | 25 | #include "qemu/osdep.h" |
852c27e2 | 26 | #include "hw/intc/i8259.h" |
64552b6b | 27 | #include "hw/irq.h" |
0d09e41a | 28 | #include "hw/isa/isa.h" |
1de7afc9 | 29 | #include "qemu/timer.h" |
03dd024f | 30 | #include "qemu/log.h" |
0d09e41a | 31 | #include "hw/isa/i8259_internal.h" |
0880a873 | 32 | #include "trace.h" |
80cabfad FB |
33 | |
34 | /* debug PIC */ | |
35 | //#define DEBUG_PIC | |
36 | ||
b41a2cd1 FB |
37 | //#define DEBUG_IRQ_LATENCY |
38 | ||
d1eebf4e | 39 | #define TYPE_I8259 "isa-i8259" |
d2628b7d AF |
40 | #define PIC_CLASS(class) OBJECT_CLASS_CHECK(PICClass, (class), TYPE_I8259) |
41 | #define PIC_GET_CLASS(obj) OBJECT_GET_CLASS(PICClass, (obj), TYPE_I8259) | |
42 | ||
43 | /** | |
44 | * PICClass: | |
45 | * @parent_realize: The parent's realizefn. | |
46 | */ | |
47 | typedef struct PICClass { | |
48 | PICCommonClass parent_class; | |
49 | ||
50 | DeviceRealize parent_realize; | |
51 | } PICClass; | |
d1eebf4e | 52 | |
747c70af JK |
53 | #ifdef DEBUG_IRQ_LATENCY |
54 | static int64_t irq_time[16]; | |
55 | #endif | |
9aa78c42 | 56 | DeviceState *isa_pic; |
512709f5 | 57 | static PICCommonState *slave_pic; |
4a0fb71e | 58 | |
80cabfad FB |
59 | /* return the highest priority found in mask (highest = smallest |
60 | number). Return 8 if no irq */ | |
512709f5 | 61 | static int get_priority(PICCommonState *s, int mask) |
80cabfad FB |
62 | { |
63 | int priority; | |
81a02f93 JK |
64 | |
65 | if (mask == 0) { | |
80cabfad | 66 | return 8; |
81a02f93 | 67 | } |
80cabfad | 68 | priority = 0; |
81a02f93 | 69 | while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0) { |
80cabfad | 70 | priority++; |
81a02f93 | 71 | } |
80cabfad FB |
72 | return priority; |
73 | } | |
74 | ||
75 | /* return the pic wanted interrupt. return -1 if none */ | |
512709f5 | 76 | static int pic_get_irq(PICCommonState *s) |
80cabfad FB |
77 | { |
78 | int mask, cur_priority, priority; | |
79 | ||
80 | mask = s->irr & ~s->imr; | |
81 | priority = get_priority(s, mask); | |
81a02f93 | 82 | if (priority == 8) { |
80cabfad | 83 | return -1; |
81a02f93 | 84 | } |
80cabfad FB |
85 | /* compute current priority. If special fully nested mode on the |
86 | master, the IRQ coming from the slave is not taken into account | |
87 | for the priority computation. */ | |
88 | mask = s->isr; | |
81a02f93 | 89 | if (s->special_mask) { |
84678711 | 90 | mask &= ~s->imr; |
81a02f93 | 91 | } |
25985396 | 92 | if (s->special_fully_nested_mode && s->master) { |
80cabfad | 93 | mask &= ~(1 << 2); |
25985396 | 94 | } |
80cabfad FB |
95 | cur_priority = get_priority(s, mask); |
96 | if (priority < cur_priority) { | |
97 | /* higher priority found: an irq should be generated */ | |
98 | return (priority + s->priority_add) & 7; | |
99 | } else { | |
100 | return -1; | |
101 | } | |
102 | } | |
103 | ||
b76750c1 | 104 | /* Update INT output. Must be called every time the output may have changed. */ |
512709f5 | 105 | static void pic_update_irq(PICCommonState *s) |
80cabfad | 106 | { |
b76750c1 | 107 | int irq; |
80cabfad | 108 | |
b76750c1 | 109 | irq = pic_get_irq(s); |
80cabfad | 110 | if (irq >= 0) { |
0880a873 | 111 | trace_pic_update_irq(s->master, s->imr, s->irr, s->priority_add); |
747c70af | 112 | qemu_irq_raise(s->int_out[0]); |
d96e1737 | 113 | } else { |
747c70af | 114 | qemu_irq_lower(s->int_out[0]); |
4de9b249 | 115 | } |
80cabfad FB |
116 | } |
117 | ||
62026017 | 118 | /* set irq level. If an edge is detected, then the IRR is set to 1 */ |
747c70af | 119 | static void pic_set_irq(void *opaque, int irq, int level) |
62026017 | 120 | { |
512709f5 | 121 | PICCommonState *s = opaque; |
747c70af | 122 | int mask = 1 << irq; |
747c70af | 123 | int irq_index = s->master ? irq : irq + 8; |
0880a873 PX |
124 | |
125 | trace_pic_set_irq(s->master, irq, level); | |
1b23190a | 126 | pic_stat_update_irq(irq_index, level); |
f260f736 | 127 | |
747c70af JK |
128 | #ifdef DEBUG_IRQ_LATENCY |
129 | if (level) { | |
bc72ad67 | 130 | irq_time[irq_index] = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
747c70af JK |
131 | } |
132 | #endif | |
133 | ||
62026017 JK |
134 | if (s->elcr & mask) { |
135 | /* level triggered */ | |
136 | if (level) { | |
137 | s->irr |= mask; | |
138 | s->last_irr |= mask; | |
139 | } else { | |
140 | s->irr &= ~mask; | |
141 | s->last_irr &= ~mask; | |
142 | } | |
143 | } else { | |
144 | /* edge triggered */ | |
145 | if (level) { | |
146 | if ((s->last_irr & mask) == 0) { | |
147 | s->irr |= mask; | |
148 | } | |
149 | s->last_irr |= mask; | |
150 | } else { | |
151 | s->last_irr &= ~mask; | |
152 | } | |
153 | } | |
b76750c1 | 154 | pic_update_irq(s); |
62026017 JK |
155 | } |
156 | ||
80cabfad | 157 | /* acknowledge interrupt 'irq' */ |
512709f5 | 158 | static void pic_intack(PICCommonState *s, int irq) |
80cabfad FB |
159 | { |
160 | if (s->auto_eoi) { | |
81a02f93 | 161 | if (s->rotate_on_auto_eoi) { |
80cabfad | 162 | s->priority_add = (irq + 1) & 7; |
81a02f93 | 163 | } |
80cabfad FB |
164 | } else { |
165 | s->isr |= (1 << irq); | |
166 | } | |
0ecf89aa | 167 | /* We don't clear a level sensitive interrupt here */ |
81a02f93 | 168 | if (!(s->elcr & (1 << irq))) { |
0ecf89aa | 169 | s->irr &= ~(1 << irq); |
81a02f93 | 170 | } |
b76750c1 | 171 | pic_update_irq(s); |
80cabfad FB |
172 | } |
173 | ||
9aa78c42 | 174 | int pic_read_irq(DeviceState *d) |
80cabfad | 175 | { |
29bb5317 | 176 | PICCommonState *s = PIC_COMMON(d); |
80cabfad FB |
177 | int irq, irq2, intno; |
178 | ||
c17725f4 | 179 | irq = pic_get_irq(s); |
15aeac38 | 180 | if (irq >= 0) { |
15aeac38 | 181 | if (irq == 2) { |
c17725f4 | 182 | irq2 = pic_get_irq(slave_pic); |
15aeac38 | 183 | if (irq2 >= 0) { |
c17725f4 | 184 | pic_intack(slave_pic, irq2); |
15aeac38 FB |
185 | } else { |
186 | /* spurious IRQ on slave controller */ | |
187 | irq2 = 7; | |
188 | } | |
c17725f4 | 189 | intno = slave_pic->irq_base + irq2; |
15aeac38 | 190 | } else { |
c17725f4 | 191 | intno = s->irq_base + irq; |
15aeac38 | 192 | } |
c17725f4 | 193 | pic_intack(s, irq); |
15aeac38 FB |
194 | } else { |
195 | /* spurious IRQ on host controller */ | |
196 | irq = 7; | |
c17725f4 | 197 | intno = s->irq_base + irq; |
15aeac38 | 198 | } |
3b46e624 | 199 | |
78ef2b69 JK |
200 | if (irq == 2) { |
201 | irq = irq2 + 8; | |
202 | } | |
0880a873 | 203 | |
80cabfad | 204 | #ifdef DEBUG_IRQ_LATENCY |
5fafdf24 TS |
205 | printf("IRQ%d latency=%0.3fus\n", |
206 | irq, | |
bc72ad67 | 207 | (double)(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - |
73bcb24d | 208 | irq_time[irq]) * 1000000.0 / NANOSECONDS_PER_SECOND); |
80cabfad | 209 | #endif |
0880a873 PX |
210 | |
211 | trace_pic_interrupt(irq, intno); | |
80cabfad FB |
212 | return intno; |
213 | } | |
214 | ||
512709f5 | 215 | static void pic_init_reset(PICCommonState *s) |
d7d02e3c | 216 | { |
512709f5 | 217 | pic_reset_common(s); |
b76750c1 | 218 | pic_update_irq(s); |
d7d02e3c FB |
219 | } |
220 | ||
747c70af | 221 | static void pic_reset(DeviceState *dev) |
86fbf97c | 222 | { |
29bb5317 | 223 | PICCommonState *s = PIC_COMMON(dev); |
86fbf97c | 224 | |
86fbf97c | 225 | s->elcr = 0; |
aa24822b | 226 | pic_init_reset(s); |
86fbf97c JK |
227 | } |
228 | ||
a8170e5e | 229 | static void pic_ioport_write(void *opaque, hwaddr addr64, |
098d314a | 230 | uint64_t val64, unsigned size) |
80cabfad | 231 | { |
512709f5 | 232 | PICCommonState *s = opaque; |
098d314a RH |
233 | uint32_t addr = addr64; |
234 | uint32_t val = val64; | |
d7d02e3c | 235 | int priority, cmd, irq; |
80cabfad | 236 | |
0880a873 PX |
237 | trace_pic_ioport_write(s->master, addr, val); |
238 | ||
80cabfad FB |
239 | if (addr == 0) { |
240 | if (val & 0x10) { | |
86fbf97c | 241 | pic_init_reset(s); |
80cabfad FB |
242 | s->init_state = 1; |
243 | s->init4 = val & 1; | |
2053152b | 244 | s->single_mode = val & 2; |
81a02f93 | 245 | if (val & 0x08) { |
8cbad670 HP |
246 | qemu_log_mask(LOG_UNIMP, |
247 | "i8259: level sensitive irq not supported\n"); | |
81a02f93 | 248 | } |
80cabfad | 249 | } else if (val & 0x08) { |
81a02f93 | 250 | if (val & 0x04) { |
80cabfad | 251 | s->poll = 1; |
81a02f93 JK |
252 | } |
253 | if (val & 0x02) { | |
80cabfad | 254 | s->read_reg_select = val & 1; |
81a02f93 JK |
255 | } |
256 | if (val & 0x40) { | |
80cabfad | 257 | s->special_mask = (val >> 5) & 1; |
81a02f93 | 258 | } |
80cabfad FB |
259 | } else { |
260 | cmd = val >> 5; | |
81a02f93 | 261 | switch (cmd) { |
80cabfad FB |
262 | case 0: |
263 | case 4: | |
264 | s->rotate_on_auto_eoi = cmd >> 2; | |
265 | break; | |
266 | case 1: /* end of interrupt */ | |
267 | case 5: | |
268 | priority = get_priority(s, s->isr); | |
269 | if (priority != 8) { | |
270 | irq = (priority + s->priority_add) & 7; | |
271 | s->isr &= ~(1 << irq); | |
81a02f93 | 272 | if (cmd == 5) { |
80cabfad | 273 | s->priority_add = (irq + 1) & 7; |
81a02f93 | 274 | } |
b76750c1 | 275 | pic_update_irq(s); |
80cabfad FB |
276 | } |
277 | break; | |
278 | case 3: | |
279 | irq = val & 7; | |
280 | s->isr &= ~(1 << irq); | |
b76750c1 | 281 | pic_update_irq(s); |
80cabfad FB |
282 | break; |
283 | case 6: | |
284 | s->priority_add = (val + 1) & 7; | |
b76750c1 | 285 | pic_update_irq(s); |
80cabfad FB |
286 | break; |
287 | case 7: | |
288 | irq = val & 7; | |
289 | s->isr &= ~(1 << irq); | |
290 | s->priority_add = (irq + 1) & 7; | |
b76750c1 | 291 | pic_update_irq(s); |
80cabfad FB |
292 | break; |
293 | default: | |
294 | /* no operation */ | |
295 | break; | |
296 | } | |
297 | } | |
298 | } else { | |
81a02f93 | 299 | switch (s->init_state) { |
80cabfad FB |
300 | case 0: |
301 | /* normal mode */ | |
302 | s->imr = val; | |
b76750c1 | 303 | pic_update_irq(s); |
80cabfad FB |
304 | break; |
305 | case 1: | |
306 | s->irq_base = val & 0xf8; | |
2bb081f7 | 307 | s->init_state = s->single_mode ? (s->init4 ? 3 : 0) : 2; |
80cabfad FB |
308 | break; |
309 | case 2: | |
310 | if (s->init4) { | |
311 | s->init_state = 3; | |
312 | } else { | |
313 | s->init_state = 0; | |
314 | } | |
315 | break; | |
316 | case 3: | |
317 | s->special_fully_nested_mode = (val >> 4) & 1; | |
318 | s->auto_eoi = (val >> 1) & 1; | |
319 | s->init_state = 0; | |
320 | break; | |
321 | } | |
322 | } | |
323 | } | |
324 | ||
a8170e5e | 325 | static uint64_t pic_ioport_read(void *opaque, hwaddr addr, |
098d314a | 326 | unsigned size) |
80cabfad | 327 | { |
512709f5 | 328 | PICCommonState *s = opaque; |
80cabfad FB |
329 | int ret; |
330 | ||
80cabfad | 331 | if (s->poll) { |
8d484caa JK |
332 | ret = pic_get_irq(s); |
333 | if (ret >= 0) { | |
334 | pic_intack(s, ret); | |
335 | ret |= 0x80; | |
336 | } else { | |
337 | ret = 0; | |
338 | } | |
80cabfad FB |
339 | s->poll = 0; |
340 | } else { | |
341 | if (addr == 0) { | |
81a02f93 | 342 | if (s->read_reg_select) { |
80cabfad | 343 | ret = s->isr; |
81a02f93 | 344 | } else { |
80cabfad | 345 | ret = s->irr; |
81a02f93 | 346 | } |
80cabfad FB |
347 | } else { |
348 | ret = s->imr; | |
349 | } | |
350 | } | |
0880a873 | 351 | trace_pic_ioport_read(s->master, addr, ret); |
80cabfad FB |
352 | return ret; |
353 | } | |
354 | ||
9aa78c42 | 355 | int pic_get_output(DeviceState *d) |
d96e1737 | 356 | { |
29bb5317 | 357 | PICCommonState *s = PIC_COMMON(d); |
9aa78c42 | 358 | |
c17725f4 | 359 | return (pic_get_irq(s) >= 0); |
d96e1737 JK |
360 | } |
361 | ||
a8170e5e | 362 | static void elcr_ioport_write(void *opaque, hwaddr addr, |
098d314a | 363 | uint64_t val, unsigned size) |
660de336 | 364 | { |
512709f5 | 365 | PICCommonState *s = opaque; |
660de336 FB |
366 | s->elcr = val & s->elcr_mask; |
367 | } | |
368 | ||
a8170e5e | 369 | static uint64_t elcr_ioport_read(void *opaque, hwaddr addr, |
098d314a | 370 | unsigned size) |
660de336 | 371 | { |
512709f5 | 372 | PICCommonState *s = opaque; |
660de336 FB |
373 | return s->elcr; |
374 | } | |
375 | ||
098d314a RH |
376 | static const MemoryRegionOps pic_base_ioport_ops = { |
377 | .read = pic_ioport_read, | |
378 | .write = pic_ioport_write, | |
379 | .impl = { | |
380 | .min_access_size = 1, | |
381 | .max_access_size = 1, | |
382 | }, | |
383 | }; | |
384 | ||
385 | static const MemoryRegionOps pic_elcr_ioport_ops = { | |
386 | .read = elcr_ioport_read, | |
387 | .write = elcr_ioport_write, | |
388 | .impl = { | |
389 | .min_access_size = 1, | |
390 | .max_access_size = 1, | |
391 | }, | |
392 | }; | |
393 | ||
a7737e44 | 394 | static void pic_realize(DeviceState *dev, Error **errp) |
b0a21b53 | 395 | { |
d2628b7d AF |
396 | PICCommonState *s = PIC_COMMON(dev); |
397 | PICClass *pc = PIC_GET_CLASS(dev); | |
29bb5317 | 398 | |
1437c94b PB |
399 | memory_region_init_io(&s->base_io, OBJECT(s), &pic_base_ioport_ops, s, |
400 | "pic", 2); | |
401 | memory_region_init_io(&s->elcr_io, OBJECT(s), &pic_elcr_ioport_ops, s, | |
402 | "elcr", 1); | |
098d314a | 403 | |
29bb5317 AF |
404 | qdev_init_gpio_out(dev, s->int_out, ARRAY_SIZE(s->int_out)); |
405 | qdev_init_gpio_in(dev, pic_set_irq, 8); | |
d2628b7d | 406 | |
a7737e44 | 407 | pc->parent_realize(dev, errp); |
b0a21b53 FB |
408 | } |
409 | ||
48a18b3c | 410 | qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq) |
80cabfad | 411 | { |
747c70af | 412 | qemu_irq *irq_set; |
d1eebf4e AF |
413 | DeviceState *dev; |
414 | ISADevice *isadev; | |
747c70af | 415 | int i; |
c17725f4 | 416 | |
8945c7f7 | 417 | irq_set = g_new0(qemu_irq, ISA_NUM_IRQS); |
c17725f4 | 418 | |
d1eebf4e AF |
419 | isadev = i8259_init_chip(TYPE_I8259, bus, true); |
420 | dev = DEVICE(isadev); | |
c17725f4 | 421 | |
d1eebf4e | 422 | qdev_connect_gpio_out(dev, 0, parent_irq); |
747c70af | 423 | for (i = 0 ; i < 8; i++) { |
d1eebf4e | 424 | irq_set[i] = qdev_get_gpio_in(dev, i); |
747c70af JK |
425 | } |
426 | ||
d1eebf4e | 427 | isa_pic = dev; |
747c70af | 428 | |
d1eebf4e AF |
429 | isadev = i8259_init_chip(TYPE_I8259, bus, false); |
430 | dev = DEVICE(isadev); | |
747c70af | 431 | |
d1eebf4e | 432 | qdev_connect_gpio_out(dev, 0, irq_set[2]); |
747c70af | 433 | for (i = 0 ; i < 8; i++) { |
d1eebf4e | 434 | irq_set[i + 8] = qdev_get_gpio_in(dev, i); |
747c70af JK |
435 | } |
436 | ||
29bb5317 | 437 | slave_pic = PIC_COMMON(dev); |
c17725f4 | 438 | |
747c70af JK |
439 | return irq_set; |
440 | } | |
441 | ||
8f04ee08 AL |
442 | static void i8259_class_init(ObjectClass *klass, void *data) |
443 | { | |
d2628b7d | 444 | PICClass *k = PIC_CLASS(klass); |
39bffca2 | 445 | DeviceClass *dc = DEVICE_CLASS(klass); |
8f04ee08 | 446 | |
bf853881 | 447 | device_class_set_parent_realize(dc, pic_realize, &k->parent_realize); |
39bffca2 | 448 | dc->reset = pic_reset; |
8f04ee08 AL |
449 | } |
450 | ||
8c43a6f0 | 451 | static const TypeInfo i8259_info = { |
d1eebf4e | 452 | .name = TYPE_I8259, |
39bffca2 AL |
453 | .instance_size = sizeof(PICCommonState), |
454 | .parent = TYPE_PIC_COMMON, | |
8f04ee08 | 455 | .class_init = i8259_class_init, |
d2628b7d | 456 | .class_size = sizeof(PICClass), |
747c70af JK |
457 | }; |
458 | ||
83f7d43a | 459 | static void pic_register_types(void) |
747c70af | 460 | { |
39bffca2 | 461 | type_register_static(&i8259_info); |
80cabfad | 462 | } |
512709f5 | 463 | |
83f7d43a | 464 | type_init(pic_register_types) |