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Commit | Line | Data |
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80cabfad FB |
1 | /* |
2 | * QEMU 8259 interrupt controller emulation | |
5fafdf24 | 3 | * |
80cabfad | 4 | * Copyright (c) 2003-2004 Fabrice Bellard |
5fafdf24 | 5 | * |
80cabfad FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
64552b6b | 24 | |
90191d07 | 25 | #include "qemu/osdep.h" |
852c27e2 | 26 | #include "hw/intc/i8259.h" |
64552b6b | 27 | #include "hw/irq.h" |
0d09e41a | 28 | #include "hw/isa/isa.h" |
1de7afc9 | 29 | #include "qemu/timer.h" |
03dd024f | 30 | #include "qemu/log.h" |
0d09e41a | 31 | #include "hw/isa/i8259_internal.h" |
0880a873 | 32 | #include "trace.h" |
db1015e9 | 33 | #include "qom/object.h" |
80cabfad FB |
34 | |
35 | /* debug PIC */ | |
36 | //#define DEBUG_PIC | |
37 | ||
b41a2cd1 FB |
38 | //#define DEBUG_IRQ_LATENCY |
39 | ||
d1eebf4e | 40 | #define TYPE_I8259 "isa-i8259" |
db1015e9 | 41 | typedef struct PICClass PICClass; |
8110fa1d EH |
42 | DECLARE_CLASS_CHECKERS(PICClass, PIC, |
43 | TYPE_I8259) | |
d2628b7d AF |
44 | |
45 | /** | |
46 | * PICClass: | |
47 | * @parent_realize: The parent's realizefn. | |
48 | */ | |
db1015e9 | 49 | struct PICClass { |
d2628b7d AF |
50 | PICCommonClass parent_class; |
51 | ||
52 | DeviceRealize parent_realize; | |
db1015e9 | 53 | }; |
d1eebf4e | 54 | |
747c70af JK |
55 | #ifdef DEBUG_IRQ_LATENCY |
56 | static int64_t irq_time[16]; | |
57 | #endif | |
2aaf0ec7 | 58 | PICCommonState *isa_pic; |
512709f5 | 59 | static PICCommonState *slave_pic; |
4a0fb71e | 60 | |
80cabfad FB |
61 | /* return the highest priority found in mask (highest = smallest |
62 | number). Return 8 if no irq */ | |
512709f5 | 63 | static int get_priority(PICCommonState *s, int mask) |
80cabfad FB |
64 | { |
65 | int priority; | |
81a02f93 JK |
66 | |
67 | if (mask == 0) { | |
80cabfad | 68 | return 8; |
81a02f93 | 69 | } |
80cabfad | 70 | priority = 0; |
81a02f93 | 71 | while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0) { |
80cabfad | 72 | priority++; |
81a02f93 | 73 | } |
80cabfad FB |
74 | return priority; |
75 | } | |
76 | ||
77 | /* return the pic wanted interrupt. return -1 if none */ | |
512709f5 | 78 | static int pic_get_irq(PICCommonState *s) |
80cabfad FB |
79 | { |
80 | int mask, cur_priority, priority; | |
81 | ||
82 | mask = s->irr & ~s->imr; | |
83 | priority = get_priority(s, mask); | |
81a02f93 | 84 | if (priority == 8) { |
80cabfad | 85 | return -1; |
81a02f93 | 86 | } |
80cabfad FB |
87 | /* compute current priority. If special fully nested mode on the |
88 | master, the IRQ coming from the slave is not taken into account | |
89 | for the priority computation. */ | |
90 | mask = s->isr; | |
81a02f93 | 91 | if (s->special_mask) { |
84678711 | 92 | mask &= ~s->imr; |
81a02f93 | 93 | } |
25985396 | 94 | if (s->special_fully_nested_mode && s->master) { |
80cabfad | 95 | mask &= ~(1 << 2); |
25985396 | 96 | } |
80cabfad FB |
97 | cur_priority = get_priority(s, mask); |
98 | if (priority < cur_priority) { | |
99 | /* higher priority found: an irq should be generated */ | |
100 | return (priority + s->priority_add) & 7; | |
101 | } else { | |
102 | return -1; | |
103 | } | |
104 | } | |
105 | ||
b76750c1 | 106 | /* Update INT output. Must be called every time the output may have changed. */ |
512709f5 | 107 | static void pic_update_irq(PICCommonState *s) |
80cabfad | 108 | { |
b76750c1 | 109 | int irq; |
80cabfad | 110 | |
b76750c1 | 111 | irq = pic_get_irq(s); |
80cabfad | 112 | if (irq >= 0) { |
0880a873 | 113 | trace_pic_update_irq(s->master, s->imr, s->irr, s->priority_add); |
747c70af | 114 | qemu_irq_raise(s->int_out[0]); |
d96e1737 | 115 | } else { |
747c70af | 116 | qemu_irq_lower(s->int_out[0]); |
4de9b249 | 117 | } |
80cabfad FB |
118 | } |
119 | ||
62026017 | 120 | /* set irq level. If an edge is detected, then the IRR is set to 1 */ |
747c70af | 121 | static void pic_set_irq(void *opaque, int irq, int level) |
62026017 | 122 | { |
512709f5 | 123 | PICCommonState *s = opaque; |
747c70af | 124 | int mask = 1 << irq; |
747c70af | 125 | int irq_index = s->master ? irq : irq + 8; |
0880a873 PX |
126 | |
127 | trace_pic_set_irq(s->master, irq, level); | |
1b23190a | 128 | pic_stat_update_irq(irq_index, level); |
f260f736 | 129 | |
747c70af JK |
130 | #ifdef DEBUG_IRQ_LATENCY |
131 | if (level) { | |
bc72ad67 | 132 | irq_time[irq_index] = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
747c70af JK |
133 | } |
134 | #endif | |
135 | ||
62026017 JK |
136 | if (s->elcr & mask) { |
137 | /* level triggered */ | |
138 | if (level) { | |
139 | s->irr |= mask; | |
140 | s->last_irr |= mask; | |
141 | } else { | |
142 | s->irr &= ~mask; | |
143 | s->last_irr &= ~mask; | |
144 | } | |
145 | } else { | |
146 | /* edge triggered */ | |
147 | if (level) { | |
148 | if ((s->last_irr & mask) == 0) { | |
149 | s->irr |= mask; | |
150 | } | |
151 | s->last_irr |= mask; | |
152 | } else { | |
153 | s->last_irr &= ~mask; | |
154 | } | |
155 | } | |
b76750c1 | 156 | pic_update_irq(s); |
62026017 JK |
157 | } |
158 | ||
80cabfad | 159 | /* acknowledge interrupt 'irq' */ |
512709f5 | 160 | static void pic_intack(PICCommonState *s, int irq) |
80cabfad FB |
161 | { |
162 | if (s->auto_eoi) { | |
81a02f93 | 163 | if (s->rotate_on_auto_eoi) { |
80cabfad | 164 | s->priority_add = (irq + 1) & 7; |
81a02f93 | 165 | } |
80cabfad FB |
166 | } else { |
167 | s->isr |= (1 << irq); | |
168 | } | |
0ecf89aa | 169 | /* We don't clear a level sensitive interrupt here */ |
81a02f93 | 170 | if (!(s->elcr & (1 << irq))) { |
0ecf89aa | 171 | s->irr &= ~(1 << irq); |
81a02f93 | 172 | } |
b76750c1 | 173 | pic_update_irq(s); |
80cabfad FB |
174 | } |
175 | ||
2aaf0ec7 | 176 | int pic_read_irq(PICCommonState *s) |
80cabfad | 177 | { |
52ad57a9 | 178 | int irq, intno; |
80cabfad | 179 | |
c17725f4 | 180 | irq = pic_get_irq(s); |
15aeac38 | 181 | if (irq >= 0) { |
52ad57a9 PMD |
182 | int irq2; |
183 | ||
15aeac38 | 184 | if (irq == 2) { |
c17725f4 | 185 | irq2 = pic_get_irq(slave_pic); |
15aeac38 | 186 | if (irq2 >= 0) { |
c17725f4 | 187 | pic_intack(slave_pic, irq2); |
15aeac38 FB |
188 | } else { |
189 | /* spurious IRQ on slave controller */ | |
190 | irq2 = 7; | |
191 | } | |
c17725f4 | 192 | intno = slave_pic->irq_base + irq2; |
52ad57a9 PMD |
193 | pic_intack(s, irq); |
194 | irq = irq2 + 8; | |
15aeac38 | 195 | } else { |
c17725f4 | 196 | intno = s->irq_base + irq; |
52ad57a9 | 197 | pic_intack(s, irq); |
15aeac38 FB |
198 | } |
199 | } else { | |
200 | /* spurious IRQ on host controller */ | |
201 | irq = 7; | |
c17725f4 | 202 | intno = s->irq_base + irq; |
15aeac38 | 203 | } |
3b46e624 | 204 | |
80cabfad | 205 | #ifdef DEBUG_IRQ_LATENCY |
5fafdf24 TS |
206 | printf("IRQ%d latency=%0.3fus\n", |
207 | irq, | |
bc72ad67 | 208 | (double)(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - |
73bcb24d | 209 | irq_time[irq]) * 1000000.0 / NANOSECONDS_PER_SECOND); |
80cabfad | 210 | #endif |
0880a873 PX |
211 | |
212 | trace_pic_interrupt(irq, intno); | |
80cabfad FB |
213 | return intno; |
214 | } | |
215 | ||
512709f5 | 216 | static void pic_init_reset(PICCommonState *s) |
d7d02e3c | 217 | { |
512709f5 | 218 | pic_reset_common(s); |
b76750c1 | 219 | pic_update_irq(s); |
d7d02e3c FB |
220 | } |
221 | ||
747c70af | 222 | static void pic_reset(DeviceState *dev) |
86fbf97c | 223 | { |
29bb5317 | 224 | PICCommonState *s = PIC_COMMON(dev); |
86fbf97c | 225 | |
86fbf97c | 226 | s->elcr = 0; |
aa24822b | 227 | pic_init_reset(s); |
86fbf97c JK |
228 | } |
229 | ||
a8170e5e | 230 | static void pic_ioport_write(void *opaque, hwaddr addr64, |
098d314a | 231 | uint64_t val64, unsigned size) |
80cabfad | 232 | { |
512709f5 | 233 | PICCommonState *s = opaque; |
098d314a RH |
234 | uint32_t addr = addr64; |
235 | uint32_t val = val64; | |
d7d02e3c | 236 | int priority, cmd, irq; |
80cabfad | 237 | |
0880a873 PX |
238 | trace_pic_ioport_write(s->master, addr, val); |
239 | ||
80cabfad FB |
240 | if (addr == 0) { |
241 | if (val & 0x10) { | |
86fbf97c | 242 | pic_init_reset(s); |
80cabfad FB |
243 | s->init_state = 1; |
244 | s->init4 = val & 1; | |
2053152b | 245 | s->single_mode = val & 2; |
81a02f93 | 246 | if (val & 0x08) { |
8cbad670 HP |
247 | qemu_log_mask(LOG_UNIMP, |
248 | "i8259: level sensitive irq not supported\n"); | |
81a02f93 | 249 | } |
80cabfad | 250 | } else if (val & 0x08) { |
81a02f93 | 251 | if (val & 0x04) { |
80cabfad | 252 | s->poll = 1; |
81a02f93 JK |
253 | } |
254 | if (val & 0x02) { | |
80cabfad | 255 | s->read_reg_select = val & 1; |
81a02f93 JK |
256 | } |
257 | if (val & 0x40) { | |
80cabfad | 258 | s->special_mask = (val >> 5) & 1; |
81a02f93 | 259 | } |
80cabfad FB |
260 | } else { |
261 | cmd = val >> 5; | |
81a02f93 | 262 | switch (cmd) { |
80cabfad FB |
263 | case 0: |
264 | case 4: | |
265 | s->rotate_on_auto_eoi = cmd >> 2; | |
266 | break; | |
267 | case 1: /* end of interrupt */ | |
268 | case 5: | |
269 | priority = get_priority(s, s->isr); | |
270 | if (priority != 8) { | |
271 | irq = (priority + s->priority_add) & 7; | |
272 | s->isr &= ~(1 << irq); | |
81a02f93 | 273 | if (cmd == 5) { |
80cabfad | 274 | s->priority_add = (irq + 1) & 7; |
81a02f93 | 275 | } |
b76750c1 | 276 | pic_update_irq(s); |
80cabfad FB |
277 | } |
278 | break; | |
279 | case 3: | |
280 | irq = val & 7; | |
281 | s->isr &= ~(1 << irq); | |
b76750c1 | 282 | pic_update_irq(s); |
80cabfad FB |
283 | break; |
284 | case 6: | |
285 | s->priority_add = (val + 1) & 7; | |
b76750c1 | 286 | pic_update_irq(s); |
80cabfad FB |
287 | break; |
288 | case 7: | |
289 | irq = val & 7; | |
290 | s->isr &= ~(1 << irq); | |
291 | s->priority_add = (irq + 1) & 7; | |
b76750c1 | 292 | pic_update_irq(s); |
80cabfad FB |
293 | break; |
294 | default: | |
295 | /* no operation */ | |
296 | break; | |
297 | } | |
298 | } | |
299 | } else { | |
81a02f93 | 300 | switch (s->init_state) { |
80cabfad FB |
301 | case 0: |
302 | /* normal mode */ | |
303 | s->imr = val; | |
b76750c1 | 304 | pic_update_irq(s); |
80cabfad FB |
305 | break; |
306 | case 1: | |
307 | s->irq_base = val & 0xf8; | |
2bb081f7 | 308 | s->init_state = s->single_mode ? (s->init4 ? 3 : 0) : 2; |
80cabfad FB |
309 | break; |
310 | case 2: | |
311 | if (s->init4) { | |
312 | s->init_state = 3; | |
313 | } else { | |
314 | s->init_state = 0; | |
315 | } | |
316 | break; | |
317 | case 3: | |
318 | s->special_fully_nested_mode = (val >> 4) & 1; | |
319 | s->auto_eoi = (val >> 1) & 1; | |
320 | s->init_state = 0; | |
321 | break; | |
322 | } | |
323 | } | |
324 | } | |
325 | ||
a8170e5e | 326 | static uint64_t pic_ioport_read(void *opaque, hwaddr addr, |
098d314a | 327 | unsigned size) |
80cabfad | 328 | { |
512709f5 | 329 | PICCommonState *s = opaque; |
80cabfad FB |
330 | int ret; |
331 | ||
80cabfad | 332 | if (s->poll) { |
8d484caa JK |
333 | ret = pic_get_irq(s); |
334 | if (ret >= 0) { | |
335 | pic_intack(s, ret); | |
336 | ret |= 0x80; | |
337 | } else { | |
338 | ret = 0; | |
339 | } | |
80cabfad FB |
340 | s->poll = 0; |
341 | } else { | |
342 | if (addr == 0) { | |
81a02f93 | 343 | if (s->read_reg_select) { |
80cabfad | 344 | ret = s->isr; |
81a02f93 | 345 | } else { |
80cabfad | 346 | ret = s->irr; |
81a02f93 | 347 | } |
80cabfad FB |
348 | } else { |
349 | ret = s->imr; | |
350 | } | |
351 | } | |
0880a873 | 352 | trace_pic_ioport_read(s->master, addr, ret); |
80cabfad FB |
353 | return ret; |
354 | } | |
355 | ||
2aaf0ec7 | 356 | int pic_get_output(PICCommonState *s) |
d96e1737 | 357 | { |
c17725f4 | 358 | return (pic_get_irq(s) >= 0); |
d96e1737 JK |
359 | } |
360 | ||
a8170e5e | 361 | static void elcr_ioport_write(void *opaque, hwaddr addr, |
098d314a | 362 | uint64_t val, unsigned size) |
660de336 | 363 | { |
512709f5 | 364 | PICCommonState *s = opaque; |
660de336 FB |
365 | s->elcr = val & s->elcr_mask; |
366 | } | |
367 | ||
a8170e5e | 368 | static uint64_t elcr_ioport_read(void *opaque, hwaddr addr, |
098d314a | 369 | unsigned size) |
660de336 | 370 | { |
512709f5 | 371 | PICCommonState *s = opaque; |
660de336 FB |
372 | return s->elcr; |
373 | } | |
374 | ||
098d314a RH |
375 | static const MemoryRegionOps pic_base_ioport_ops = { |
376 | .read = pic_ioport_read, | |
377 | .write = pic_ioport_write, | |
378 | .impl = { | |
379 | .min_access_size = 1, | |
380 | .max_access_size = 1, | |
381 | }, | |
382 | }; | |
383 | ||
384 | static const MemoryRegionOps pic_elcr_ioport_ops = { | |
385 | .read = elcr_ioport_read, | |
386 | .write = elcr_ioport_write, | |
387 | .impl = { | |
388 | .min_access_size = 1, | |
389 | .max_access_size = 1, | |
390 | }, | |
391 | }; | |
392 | ||
a7737e44 | 393 | static void pic_realize(DeviceState *dev, Error **errp) |
b0a21b53 | 394 | { |
d2628b7d AF |
395 | PICCommonState *s = PIC_COMMON(dev); |
396 | PICClass *pc = PIC_GET_CLASS(dev); | |
29bb5317 | 397 | |
1437c94b PB |
398 | memory_region_init_io(&s->base_io, OBJECT(s), &pic_base_ioport_ops, s, |
399 | "pic", 2); | |
400 | memory_region_init_io(&s->elcr_io, OBJECT(s), &pic_elcr_ioport_ops, s, | |
401 | "elcr", 1); | |
098d314a | 402 | |
29bb5317 AF |
403 | qdev_init_gpio_out(dev, s->int_out, ARRAY_SIZE(s->int_out)); |
404 | qdev_init_gpio_in(dev, pic_set_irq, 8); | |
d2628b7d | 405 | |
a7737e44 | 406 | pc->parent_realize(dev, errp); |
b0a21b53 FB |
407 | } |
408 | ||
48a18b3c | 409 | qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq) |
80cabfad | 410 | { |
747c70af | 411 | qemu_irq *irq_set; |
d1eebf4e AF |
412 | DeviceState *dev; |
413 | ISADevice *isadev; | |
747c70af | 414 | int i; |
c17725f4 | 415 | |
8945c7f7 | 416 | irq_set = g_new0(qemu_irq, ISA_NUM_IRQS); |
c17725f4 | 417 | |
d1eebf4e AF |
418 | isadev = i8259_init_chip(TYPE_I8259, bus, true); |
419 | dev = DEVICE(isadev); | |
c17725f4 | 420 | |
d1eebf4e | 421 | qdev_connect_gpio_out(dev, 0, parent_irq); |
747c70af | 422 | for (i = 0 ; i < 8; i++) { |
d1eebf4e | 423 | irq_set[i] = qdev_get_gpio_in(dev, i); |
747c70af JK |
424 | } |
425 | ||
2aaf0ec7 | 426 | isa_pic = PIC_COMMON(dev); |
747c70af | 427 | |
d1eebf4e AF |
428 | isadev = i8259_init_chip(TYPE_I8259, bus, false); |
429 | dev = DEVICE(isadev); | |
747c70af | 430 | |
d1eebf4e | 431 | qdev_connect_gpio_out(dev, 0, irq_set[2]); |
747c70af | 432 | for (i = 0 ; i < 8; i++) { |
d1eebf4e | 433 | irq_set[i + 8] = qdev_get_gpio_in(dev, i); |
747c70af JK |
434 | } |
435 | ||
29bb5317 | 436 | slave_pic = PIC_COMMON(dev); |
c17725f4 | 437 | |
747c70af JK |
438 | return irq_set; |
439 | } | |
440 | ||
8f04ee08 AL |
441 | static void i8259_class_init(ObjectClass *klass, void *data) |
442 | { | |
d2628b7d | 443 | PICClass *k = PIC_CLASS(klass); |
39bffca2 | 444 | DeviceClass *dc = DEVICE_CLASS(klass); |
8f04ee08 | 445 | |
bf853881 | 446 | device_class_set_parent_realize(dc, pic_realize, &k->parent_realize); |
39bffca2 | 447 | dc->reset = pic_reset; |
8f04ee08 AL |
448 | } |
449 | ||
8c43a6f0 | 450 | static const TypeInfo i8259_info = { |
d1eebf4e | 451 | .name = TYPE_I8259, |
39bffca2 AL |
452 | .instance_size = sizeof(PICCommonState), |
453 | .parent = TYPE_PIC_COMMON, | |
8f04ee08 | 454 | .class_init = i8259_class_init, |
d2628b7d | 455 | .class_size = sizeof(PICClass), |
747c70af JK |
456 | }; |
457 | ||
83f7d43a | 458 | static void pic_register_types(void) |
747c70af | 459 | { |
39bffca2 | 460 | type_register_static(&i8259_info); |
80cabfad | 461 | } |
512709f5 | 462 | |
83f7d43a | 463 | type_init(pic_register_types) |