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i8259: generalize statistics into common code
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1/*
2 * QEMU 8259 - common bits of emulated and KVM kernel model
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 * Copyright (c) 2011 Jan Kiszka, Siemens AG
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
90191d07 25#include "qemu/osdep.h"
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26#include "hw/i386/pc.h"
27#include "hw/isa/i8259_internal.h"
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28#include "monitor/monitor.h"
29
30static int irq_level[16];
31static uint64_t irq_count[16];
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32
33void pic_reset_common(PICCommonState *s)
34{
35 s->last_irr = 0;
aa24822b 36 s->irr &= s->elcr;
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37 s->imr = 0;
38 s->isr = 0;
39 s->priority_add = 0;
40 s->irq_base = 0;
41 s->read_reg_select = 0;
42 s->poll = 0;
43 s->special_mask = 0;
44 s->init_state = 0;
45 s->auto_eoi = 0;
46 s->rotate_on_auto_eoi = 0;
47 s->special_fully_nested_mode = 0;
48 s->init4 = 0;
49 s->single_mode = 0;
50 /* Note: ELCR is not reset */
51}
52
44b1ff31 53static int pic_dispatch_pre_save(void *opaque)
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54{
55 PICCommonState *s = opaque;
8f04ee08 56 PICCommonClass *info = PIC_COMMON_GET_CLASS(s);
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57
58 if (info->pre_save) {
59 info->pre_save(s);
60 }
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61
62 return 0;
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63}
64
65static int pic_dispatch_post_load(void *opaque, int version_id)
66{
67 PICCommonState *s = opaque;
8f04ee08 68 PICCommonClass *info = PIC_COMMON_GET_CLASS(s);
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69
70 if (info->post_load) {
71 info->post_load(s);
72 }
73 return 0;
74}
75
db895a1e 76static void pic_common_realize(DeviceState *dev, Error **errp)
512709f5 77{
29bb5317 78 PICCommonState *s = PIC_COMMON(dev);
25a85359 79 ISADevice *isa = ISA_DEVICE(dev);
512709f5 80
25a85359 81 isa_register_ioport(isa, &s->base_io, s->iobase);
512709f5 82 if (s->elcr_addr != -1) {
25a85359 83 isa_register_ioport(isa, &s->elcr_io, s->elcr_addr);
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84 }
85
db895a1e 86 qdev_set_legacy_instance_id(dev, s->iobase, 1);
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87}
88
89ISADevice *i8259_init_chip(const char *name, ISABus *bus, bool master)
90{
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91 DeviceState *dev;
92 ISADevice *isadev;
512709f5 93
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94 isadev = isa_create(bus, name);
95 dev = DEVICE(isadev);
96 qdev_prop_set_uint32(dev, "iobase", master ? 0x20 : 0xa0);
97 qdev_prop_set_uint32(dev, "elcr_addr", master ? 0x4d0 : 0x4d1);
98 qdev_prop_set_uint8(dev, "elcr_mask", master ? 0xf8 : 0xde);
99 qdev_prop_set_bit(dev, "master", master);
100 qdev_init_nofail(dev);
512709f5 101
4a17cc4f 102 return isadev;
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103}
104
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105void pic_stat_update_irq(int irq, int level)
106{
107 if (level != irq_level[irq]) {
108 irq_level[irq] = level;
109 if (level == 1) {
110 irq_count[irq]++;
111 }
112 }
113}
114
115bool pic_get_statistics(InterruptStatsProvider *obj,
116 uint64_t **irq_counts, unsigned int *nb_irqs)
117{
118 PICCommonState *s = PIC_COMMON(obj);
119
120 if (s->master) {
121 *irq_counts = irq_count;
122 *nb_irqs = ARRAY_SIZE(irq_count);
123 } else {
124 *irq_counts = NULL;
125 *nb_irqs = 0;
126 }
127
128 return true;
129}
130
131void pic_print_info(InterruptStatsProvider *obj, Monitor *mon)
132{
133 PICCommonState *s = PIC_COMMON(obj);
134
135 monitor_printf(mon, "pic%d: irr=%02x imr=%02x isr=%02x hprio=%d "
136 "irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n",
137 s->master ? 0 : 1, s->irr, s->imr, s->isr, s->priority_add,
138 s->irq_base, s->read_reg_select, s->elcr,
139 s->special_fully_nested_mode);
140}
141
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142static const VMStateDescription vmstate_pic_common = {
143 .name = "i8259",
144 .version_id = 1,
145 .minimum_version_id = 1,
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146 .pre_save = pic_dispatch_pre_save,
147 .post_load = pic_dispatch_post_load,
148 .fields = (VMStateField[]) {
149 VMSTATE_UINT8(last_irr, PICCommonState),
150 VMSTATE_UINT8(irr, PICCommonState),
151 VMSTATE_UINT8(imr, PICCommonState),
152 VMSTATE_UINT8(isr, PICCommonState),
153 VMSTATE_UINT8(priority_add, PICCommonState),
154 VMSTATE_UINT8(irq_base, PICCommonState),
155 VMSTATE_UINT8(read_reg_select, PICCommonState),
156 VMSTATE_UINT8(poll, PICCommonState),
157 VMSTATE_UINT8(special_mask, PICCommonState),
158 VMSTATE_UINT8(init_state, PICCommonState),
159 VMSTATE_UINT8(auto_eoi, PICCommonState),
160 VMSTATE_UINT8(rotate_on_auto_eoi, PICCommonState),
161 VMSTATE_UINT8(special_fully_nested_mode, PICCommonState),
162 VMSTATE_UINT8(init4, PICCommonState),
163 VMSTATE_UINT8(single_mode, PICCommonState),
164 VMSTATE_UINT8(elcr, PICCommonState),
165 VMSTATE_END_OF_LIST()
166 }
167};
168
169static Property pic_properties_common[] = {
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170 DEFINE_PROP_UINT32("iobase", PICCommonState, iobase, -1),
171 DEFINE_PROP_UINT32("elcr_addr", PICCommonState, elcr_addr, -1),
172 DEFINE_PROP_UINT8("elcr_mask", PICCommonState, elcr_mask, -1),
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173 DEFINE_PROP_BIT("master", PICCommonState, master, 0, false),
174 DEFINE_PROP_END_OF_LIST(),
175};
176
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177static void pic_common_class_init(ObjectClass *klass, void *data)
178{
39bffca2 179 DeviceClass *dc = DEVICE_CLASS(klass);
8f04ee08 180
39bffca2 181 dc->vmsd = &vmstate_pic_common;
39bffca2 182 dc->props = pic_properties_common;
db895a1e 183 dc->realize = pic_common_realize;
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184 /*
185 * Reason: unlike ordinary ISA devices, the PICs need additional
186 * wiring: its IRQ input lines are set up by board code, and the
187 * wiring of the slave to the master is hard-coded in device model
188 * code.
189 */
e90f2a8c 190 dc->user_creatable = false;
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191}
192
8c43a6f0 193static const TypeInfo pic_common_type = {
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194 .name = TYPE_PIC_COMMON,
195 .parent = TYPE_ISA_DEVICE,
196 .instance_size = sizeof(PICCommonState),
197 .class_size = sizeof(PICCommonClass),
198 .class_init = pic_common_class_init,
199 .abstract = true,
200};
201
29bb5317 202static void pic_common_register_types(void)
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AL
203{
204 type_register_static(&pic_common_type);
205}
206
29bb5317 207type_init(pic_common_register_types)