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4ef66fa7 MW |
1 | /* |
2 | * LatticeMico32 CPU interrupt controller logic. | |
3 | * | |
4 | * Copyright (c) 2010 Michael Walle <michael@walle.cc> | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
61f3c91a | 9 | * version 2.1 of the License, or (at your option) any later version. |
4ef66fa7 MW |
10 | * |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
ea99dde1 | 20 | #include "qemu/osdep.h" |
4ef66fa7 | 21 | |
d6454270 | 22 | #include "migration/vmstate.h" |
83c9089e | 23 | #include "monitor/monitor.h" |
0b8fa32f | 24 | #include "qemu/module.h" |
83c9f4ca | 25 | #include "hw/sysbus.h" |
4ef66fa7 | 26 | #include "trace.h" |
0d09e41a | 27 | #include "hw/lm32/lm32_pic.h" |
7c468ec5 | 28 | #include "hw/intc/intc.h" |
64552b6b | 29 | #include "hw/irq.h" |
db1015e9 | 30 | #include "qom/object.h" |
4ef66fa7 | 31 | |
1f8a9eac | 32 | #define TYPE_LM32_PIC "lm32-pic" |
8063396b | 33 | OBJECT_DECLARE_SIMPLE_TYPE(LM32PicState, LM32_PIC) |
1f8a9eac | 34 | |
4ef66fa7 | 35 | struct LM32PicState { |
1f8a9eac AF |
36 | SysBusDevice parent_obj; |
37 | ||
4ef66fa7 MW |
38 | qemu_irq parent_irq; |
39 | uint32_t im; /* interrupt mask */ | |
40 | uint32_t ip; /* interrupt pending */ | |
41 | uint32_t irq_state; | |
42 | ||
43 | /* statistics */ | |
7c468ec5 | 44 | uint64_t stats_irq_count[32]; |
4ef66fa7 | 45 | }; |
4ef66fa7 | 46 | |
4ef66fa7 MW |
47 | static void update_irq(LM32PicState *s) |
48 | { | |
49 | s->ip |= s->irq_state; | |
50 | ||
51 | if (s->ip & s->im) { | |
52 | trace_lm32_pic_raise_irq(); | |
53 | qemu_irq_raise(s->parent_irq); | |
54 | } else { | |
55 | trace_lm32_pic_lower_irq(); | |
56 | qemu_irq_lower(s->parent_irq); | |
57 | } | |
58 | } | |
59 | ||
60 | static void irq_handler(void *opaque, int irq, int level) | |
61 | { | |
62 | LM32PicState *s = opaque; | |
63 | ||
64 | assert(irq < 32); | |
65 | trace_lm32_pic_interrupt(irq, level); | |
66 | ||
67 | if (level) { | |
68 | s->irq_state |= (1 << irq); | |
69 | s->stats_irq_count[irq]++; | |
70 | } else { | |
71 | s->irq_state &= ~(1 << irq); | |
72 | } | |
73 | ||
74 | update_irq(s); | |
75 | } | |
76 | ||
77 | void lm32_pic_set_im(DeviceState *d, uint32_t im) | |
78 | { | |
1f8a9eac | 79 | LM32PicState *s = LM32_PIC(d); |
4ef66fa7 MW |
80 | |
81 | trace_lm32_pic_set_im(im); | |
82 | s->im = im; | |
83 | ||
84 | update_irq(s); | |
85 | } | |
86 | ||
87 | void lm32_pic_set_ip(DeviceState *d, uint32_t ip) | |
88 | { | |
1f8a9eac | 89 | LM32PicState *s = LM32_PIC(d); |
4ef66fa7 MW |
90 | |
91 | trace_lm32_pic_set_ip(ip); | |
92 | ||
93 | /* ack interrupt */ | |
94 | s->ip &= ~ip; | |
95 | ||
96 | update_irq(s); | |
97 | } | |
98 | ||
99 | uint32_t lm32_pic_get_im(DeviceState *d) | |
100 | { | |
1f8a9eac | 101 | LM32PicState *s = LM32_PIC(d); |
4ef66fa7 MW |
102 | |
103 | trace_lm32_pic_get_im(s->im); | |
104 | return s->im; | |
105 | } | |
106 | ||
107 | uint32_t lm32_pic_get_ip(DeviceState *d) | |
108 | { | |
1f8a9eac | 109 | LM32PicState *s = LM32_PIC(d); |
4ef66fa7 MW |
110 | |
111 | trace_lm32_pic_get_ip(s->ip); | |
112 | return s->ip; | |
113 | } | |
114 | ||
115 | static void pic_reset(DeviceState *d) | |
116 | { | |
1f8a9eac | 117 | LM32PicState *s = LM32_PIC(d); |
4ef66fa7 MW |
118 | int i; |
119 | ||
120 | s->im = 0; | |
121 | s->ip = 0; | |
122 | s->irq_state = 0; | |
123 | for (i = 0; i < 32; i++) { | |
124 | s->stats_irq_count[i] = 0; | |
125 | } | |
126 | } | |
127 | ||
7c468ec5 HP |
128 | static bool lm32_get_statistics(InterruptStatsProvider *obj, |
129 | uint64_t **irq_counts, unsigned int *nb_irqs) | |
130 | { | |
131 | LM32PicState *s = LM32_PIC(obj); | |
132 | *irq_counts = s->stats_irq_count; | |
133 | *nb_irqs = ARRAY_SIZE(s->stats_irq_count); | |
134 | return true; | |
135 | } | |
136 | ||
137 | static void lm32_print_info(InterruptStatsProvider *obj, Monitor *mon) | |
138 | { | |
139 | LM32PicState *s = LM32_PIC(obj); | |
140 | monitor_printf(mon, "lm32-pic: im=%08x ip=%08x irq_state=%08x\n", | |
141 | s->im, s->ip, s->irq_state); | |
142 | } | |
143 | ||
5e502d31 | 144 | static void lm32_pic_init(Object *obj) |
4ef66fa7 | 145 | { |
5e502d31 XZ |
146 | DeviceState *dev = DEVICE(obj); |
147 | LM32PicState *s = LM32_PIC(obj); | |
148 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | |
4ef66fa7 | 149 | |
1f8a9eac AF |
150 | qdev_init_gpio_in(dev, irq_handler, 32); |
151 | sysbus_init_irq(sbd, &s->parent_irq); | |
4ef66fa7 MW |
152 | } |
153 | ||
154 | static const VMStateDescription vmstate_lm32_pic = { | |
155 | .name = "lm32-pic", | |
7c468ec5 HP |
156 | .version_id = 2, |
157 | .minimum_version_id = 2, | |
35d08458 | 158 | .fields = (VMStateField[]) { |
4ef66fa7 MW |
159 | VMSTATE_UINT32(im, LM32PicState), |
160 | VMSTATE_UINT32(ip, LM32PicState), | |
161 | VMSTATE_UINT32(irq_state, LM32PicState), | |
7c468ec5 | 162 | VMSTATE_UINT64_ARRAY(stats_irq_count, LM32PicState, 32), |
4ef66fa7 MW |
163 | VMSTATE_END_OF_LIST() |
164 | } | |
165 | }; | |
166 | ||
999e12bb AL |
167 | static void lm32_pic_class_init(ObjectClass *klass, void *data) |
168 | { | |
39bffca2 | 169 | DeviceClass *dc = DEVICE_CLASS(klass); |
7c468ec5 | 170 | InterruptStatsProviderClass *ic = INTERRUPT_STATS_PROVIDER_CLASS(klass); |
999e12bb | 171 | |
39bffca2 AL |
172 | dc->reset = pic_reset; |
173 | dc->vmsd = &vmstate_lm32_pic; | |
7c468ec5 HP |
174 | ic->get_statistics = lm32_get_statistics; |
175 | ic->print_info = lm32_print_info; | |
999e12bb AL |
176 | } |
177 | ||
8c43a6f0 | 178 | static const TypeInfo lm32_pic_info = { |
1f8a9eac | 179 | .name = TYPE_LM32_PIC, |
39bffca2 AL |
180 | .parent = TYPE_SYS_BUS_DEVICE, |
181 | .instance_size = sizeof(LM32PicState), | |
5e502d31 | 182 | .instance_init = lm32_pic_init, |
39bffca2 | 183 | .class_init = lm32_pic_class_init, |
7c468ec5 HP |
184 | .interfaces = (InterfaceInfo[]) { |
185 | { TYPE_INTERRUPT_STATS_PROVIDER }, | |
186 | { } | |
187 | }, | |
4ef66fa7 MW |
188 | }; |
189 | ||
83f7d43a | 190 | static void lm32_pic_register_types(void) |
4ef66fa7 | 191 | { |
39bffca2 | 192 | type_register_static(&lm32_pic_info); |
4ef66fa7 MW |
193 | } |
194 | ||
83f7d43a | 195 | type_init(lm32_pic_register_types) |