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1/*
2 * LatticeMico32 CPU interrupt controller logic.
3 *
4 * Copyright (c) 2010 Michael Walle <michael@walle.cc>
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
ea99dde1 20#include "qemu/osdep.h"
4ef66fa7 21
83c9f4ca 22#include "hw/hw.h"
d6454270 23#include "migration/vmstate.h"
83c9089e 24#include "monitor/monitor.h"
0b8fa32f 25#include "qemu/module.h"
83c9f4ca 26#include "hw/sysbus.h"
4ef66fa7 27#include "trace.h"
0d09e41a 28#include "hw/lm32/lm32_pic.h"
7c468ec5 29#include "hw/intc/intc.h"
64552b6b 30#include "hw/irq.h"
4ef66fa7 31
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32#define TYPE_LM32_PIC "lm32-pic"
33#define LM32_PIC(obj) OBJECT_CHECK(LM32PicState, (obj), TYPE_LM32_PIC)
34
4ef66fa7 35struct LM32PicState {
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36 SysBusDevice parent_obj;
37
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38 qemu_irq parent_irq;
39 uint32_t im; /* interrupt mask */
40 uint32_t ip; /* interrupt pending */
41 uint32_t irq_state;
42
43 /* statistics */
7c468ec5 44 uint64_t stats_irq_count[32];
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45};
46typedef struct LM32PicState LM32PicState;
47
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48static void update_irq(LM32PicState *s)
49{
50 s->ip |= s->irq_state;
51
52 if (s->ip & s->im) {
53 trace_lm32_pic_raise_irq();
54 qemu_irq_raise(s->parent_irq);
55 } else {
56 trace_lm32_pic_lower_irq();
57 qemu_irq_lower(s->parent_irq);
58 }
59}
60
61static void irq_handler(void *opaque, int irq, int level)
62{
63 LM32PicState *s = opaque;
64
65 assert(irq < 32);
66 trace_lm32_pic_interrupt(irq, level);
67
68 if (level) {
69 s->irq_state |= (1 << irq);
70 s->stats_irq_count[irq]++;
71 } else {
72 s->irq_state &= ~(1 << irq);
73 }
74
75 update_irq(s);
76}
77
78void lm32_pic_set_im(DeviceState *d, uint32_t im)
79{
1f8a9eac 80 LM32PicState *s = LM32_PIC(d);
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81
82 trace_lm32_pic_set_im(im);
83 s->im = im;
84
85 update_irq(s);
86}
87
88void lm32_pic_set_ip(DeviceState *d, uint32_t ip)
89{
1f8a9eac 90 LM32PicState *s = LM32_PIC(d);
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91
92 trace_lm32_pic_set_ip(ip);
93
94 /* ack interrupt */
95 s->ip &= ~ip;
96
97 update_irq(s);
98}
99
100uint32_t lm32_pic_get_im(DeviceState *d)
101{
1f8a9eac 102 LM32PicState *s = LM32_PIC(d);
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103
104 trace_lm32_pic_get_im(s->im);
105 return s->im;
106}
107
108uint32_t lm32_pic_get_ip(DeviceState *d)
109{
1f8a9eac 110 LM32PicState *s = LM32_PIC(d);
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111
112 trace_lm32_pic_get_ip(s->ip);
113 return s->ip;
114}
115
116static void pic_reset(DeviceState *d)
117{
1f8a9eac 118 LM32PicState *s = LM32_PIC(d);
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119 int i;
120
121 s->im = 0;
122 s->ip = 0;
123 s->irq_state = 0;
124 for (i = 0; i < 32; i++) {
125 s->stats_irq_count[i] = 0;
126 }
127}
128
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129static bool lm32_get_statistics(InterruptStatsProvider *obj,
130 uint64_t **irq_counts, unsigned int *nb_irqs)
131{
132 LM32PicState *s = LM32_PIC(obj);
133 *irq_counts = s->stats_irq_count;
134 *nb_irqs = ARRAY_SIZE(s->stats_irq_count);
135 return true;
136}
137
138static void lm32_print_info(InterruptStatsProvider *obj, Monitor *mon)
139{
140 LM32PicState *s = LM32_PIC(obj);
141 monitor_printf(mon, "lm32-pic: im=%08x ip=%08x irq_state=%08x\n",
142 s->im, s->ip, s->irq_state);
143}
144
5e502d31 145static void lm32_pic_init(Object *obj)
4ef66fa7 146{
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147 DeviceState *dev = DEVICE(obj);
148 LM32PicState *s = LM32_PIC(obj);
149 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
4ef66fa7 150
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151 qdev_init_gpio_in(dev, irq_handler, 32);
152 sysbus_init_irq(sbd, &s->parent_irq);
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153}
154
155static const VMStateDescription vmstate_lm32_pic = {
156 .name = "lm32-pic",
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157 .version_id = 2,
158 .minimum_version_id = 2,
35d08458 159 .fields = (VMStateField[]) {
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160 VMSTATE_UINT32(im, LM32PicState),
161 VMSTATE_UINT32(ip, LM32PicState),
162 VMSTATE_UINT32(irq_state, LM32PicState),
7c468ec5 163 VMSTATE_UINT64_ARRAY(stats_irq_count, LM32PicState, 32),
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164 VMSTATE_END_OF_LIST()
165 }
166};
167
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168static void lm32_pic_class_init(ObjectClass *klass, void *data)
169{
39bffca2 170 DeviceClass *dc = DEVICE_CLASS(klass);
7c468ec5 171 InterruptStatsProviderClass *ic = INTERRUPT_STATS_PROVIDER_CLASS(klass);
999e12bb 172
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173 dc->reset = pic_reset;
174 dc->vmsd = &vmstate_lm32_pic;
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175 ic->get_statistics = lm32_get_statistics;
176 ic->print_info = lm32_print_info;
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177}
178
8c43a6f0 179static const TypeInfo lm32_pic_info = {
1f8a9eac 180 .name = TYPE_LM32_PIC,
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181 .parent = TYPE_SYS_BUS_DEVICE,
182 .instance_size = sizeof(LM32PicState),
5e502d31 183 .instance_init = lm32_pic_init,
39bffca2 184 .class_init = lm32_pic_class_init,
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185 .interfaces = (InterfaceInfo[]) {
186 { TYPE_INTERRUPT_STATS_PROVIDER },
187 { }
188 },
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189};
190
83f7d43a 191static void lm32_pic_register_types(void)
4ef66fa7 192{
39bffca2 193 type_register_static(&lm32_pic_info);
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194}
195
83f7d43a 196type_init(lm32_pic_register_types)