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d85937e6 SW |
1 | /* |
2 | * KVM in-kernel OpenPIC | |
3 | * | |
4 | * Copyright 2013 Freescale Semiconductor, Inc. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
25 | #include <sys/ioctl.h> | |
26 | #include "exec/address-spaces.h" | |
27 | #include "hw/hw.h" | |
28 | #include "hw/ppc/openpic.h" | |
29 | #include "hw/pci/msi.h" | |
30 | #include "hw/sysbus.h" | |
31 | #include "sysemu/kvm.h" | |
32 | #include "qemu/log.h" | |
33 | ||
dd49c038 AF |
34 | #define KVM_OPENPIC(obj) \ |
35 | OBJECT_CHECK(KVMOpenPICState, (obj), TYPE_KVM_OPENPIC) | |
36 | ||
d85937e6 | 37 | typedef struct KVMOpenPICState { |
dd49c038 AF |
38 | /*< private >*/ |
39 | SysBusDevice parent_obj; | |
40 | /*< public >*/ | |
41 | ||
d85937e6 SW |
42 | MemoryRegion mem; |
43 | MemoryListener mem_listener; | |
44 | uint32_t fd; | |
45 | uint32_t model; | |
46 | } KVMOpenPICState; | |
47 | ||
48 | static void kvm_openpic_set_irq(void *opaque, int n_IRQ, int level) | |
49 | { | |
50 | kvm_set_irq(kvm_state, n_IRQ, level); | |
51 | } | |
52 | ||
53 | static void kvm_openpic_reset(DeviceState *d) | |
54 | { | |
55 | qemu_log_mask(LOG_UNIMP, "%s: unimplemented\n", __func__); | |
56 | } | |
57 | ||
58 | static void kvm_openpic_write(void *opaque, hwaddr addr, uint64_t val, | |
59 | unsigned size) | |
60 | { | |
61 | KVMOpenPICState *opp = opaque; | |
62 | struct kvm_device_attr attr; | |
63 | uint32_t val32 = val; | |
64 | int ret; | |
65 | ||
66 | attr.group = KVM_DEV_MPIC_GRP_REGISTER; | |
67 | attr.attr = addr; | |
68 | attr.addr = (uint64_t)(unsigned long)&val32; | |
69 | ||
70 | ret = ioctl(opp->fd, KVM_SET_DEVICE_ATTR, &attr); | |
71 | if (ret < 0) { | |
72 | qemu_log_mask(LOG_UNIMP, "%s: %s %" PRIx64 "\n", __func__, | |
73 | strerror(errno), attr.attr); | |
74 | } | |
75 | } | |
76 | ||
77 | static uint64_t kvm_openpic_read(void *opaque, hwaddr addr, unsigned size) | |
78 | { | |
79 | KVMOpenPICState *opp = opaque; | |
80 | struct kvm_device_attr attr; | |
81 | uint32_t val = 0xdeadbeef; | |
82 | int ret; | |
83 | ||
84 | attr.group = KVM_DEV_MPIC_GRP_REGISTER; | |
85 | attr.attr = addr; | |
86 | attr.addr = (uint64_t)(unsigned long)&val; | |
87 | ||
88 | ret = ioctl(opp->fd, KVM_GET_DEVICE_ATTR, &attr); | |
89 | if (ret < 0) { | |
90 | qemu_log_mask(LOG_UNIMP, "%s: %s %" PRIx64 "\n", __func__, | |
91 | strerror(errno), attr.attr); | |
92 | return 0; | |
93 | } | |
94 | ||
95 | return val; | |
96 | } | |
97 | ||
98 | static const MemoryRegionOps kvm_openpic_mem_ops = { | |
99 | .write = kvm_openpic_write, | |
100 | .read = kvm_openpic_read, | |
101 | .endianness = DEVICE_BIG_ENDIAN, | |
102 | .impl = { | |
103 | .min_access_size = 4, | |
104 | .max_access_size = 4, | |
105 | }, | |
106 | }; | |
107 | ||
108 | static void kvm_openpic_region_add(MemoryListener *listener, | |
109 | MemoryRegionSection *section) | |
110 | { | |
111 | KVMOpenPICState *opp = container_of(listener, KVMOpenPICState, | |
112 | mem_listener); | |
113 | struct kvm_device_attr attr; | |
114 | uint64_t reg_base; | |
115 | int ret; | |
116 | ||
117 | if (section->address_space != &address_space_memory) { | |
118 | abort(); | |
119 | } | |
120 | ||
121 | reg_base = section->offset_within_address_space; | |
122 | ||
123 | attr.group = KVM_DEV_MPIC_GRP_MISC; | |
124 | attr.attr = KVM_DEV_MPIC_BASE_ADDR; | |
125 | attr.addr = (uint64_t)(unsigned long)®_base; | |
126 | ||
127 | ret = ioctl(opp->fd, KVM_SET_DEVICE_ATTR, &attr); | |
128 | if (ret < 0) { | |
129 | fprintf(stderr, "%s: %s %" PRIx64 "\n", __func__, | |
130 | strerror(errno), reg_base); | |
131 | } | |
132 | } | |
133 | ||
134 | static void kvm_openpic_region_del(MemoryListener *listener, | |
135 | MemoryRegionSection *section) | |
136 | { | |
137 | KVMOpenPICState *opp = container_of(listener, KVMOpenPICState, | |
138 | mem_listener); | |
139 | struct kvm_device_attr attr; | |
140 | uint64_t reg_base = 0; | |
141 | int ret; | |
142 | ||
143 | attr.group = KVM_DEV_MPIC_GRP_MISC; | |
144 | attr.attr = KVM_DEV_MPIC_BASE_ADDR; | |
145 | attr.addr = (uint64_t)(unsigned long)®_base; | |
146 | ||
147 | ret = ioctl(opp->fd, KVM_SET_DEVICE_ATTR, &attr); | |
148 | if (ret < 0) { | |
149 | fprintf(stderr, "%s: %s %" PRIx64 "\n", __func__, | |
150 | strerror(errno), reg_base); | |
151 | } | |
152 | } | |
153 | ||
dd49c038 AF |
154 | static void kvm_openpic_init(Object *obj) |
155 | { | |
156 | KVMOpenPICState *opp = KVM_OPENPIC(obj); | |
157 | ||
2c9b15ca | 158 | memory_region_init_io(&opp->mem, NULL, &kvm_openpic_mem_ops, opp, |
dd49c038 AF |
159 | "kvm-openpic", 0x40000); |
160 | } | |
161 | ||
162 | static void kvm_openpic_realize(DeviceState *dev, Error **errp) | |
d85937e6 | 163 | { |
dd49c038 AF |
164 | SysBusDevice *d = SYS_BUS_DEVICE(dev); |
165 | KVMOpenPICState *opp = KVM_OPENPIC(dev); | |
d85937e6 | 166 | KVMState *s = kvm_state; |
d85937e6 SW |
167 | int kvm_openpic_model; |
168 | struct kvm_create_device cd = {0}; | |
169 | int ret, i; | |
170 | ||
171 | if (!kvm_check_extension(s, KVM_CAP_DEVICE_CTRL)) { | |
dd49c038 AF |
172 | error_setg(errp, "Kernel is lacking Device Control API"); |
173 | return; | |
d85937e6 SW |
174 | } |
175 | ||
176 | switch (opp->model) { | |
177 | case OPENPIC_MODEL_FSL_MPIC_20: | |
178 | kvm_openpic_model = KVM_DEV_TYPE_FSL_MPIC_20; | |
179 | break; | |
180 | ||
181 | case OPENPIC_MODEL_FSL_MPIC_42: | |
182 | kvm_openpic_model = KVM_DEV_TYPE_FSL_MPIC_42; | |
183 | break; | |
184 | ||
185 | default: | |
dd49c038 AF |
186 | error_setg(errp, "Unsupported OpenPIC model %" PRIu32, opp->model); |
187 | return; | |
d85937e6 SW |
188 | } |
189 | ||
190 | cd.type = kvm_openpic_model; | |
191 | ret = kvm_vm_ioctl(s, KVM_CREATE_DEVICE, &cd); | |
192 | if (ret < 0) { | |
dd49c038 AF |
193 | error_setg(errp, "Can't create device %d: %s", |
194 | cd.type, strerror(errno)); | |
195 | return; | |
d85937e6 SW |
196 | } |
197 | opp->fd = cd.fd; | |
198 | ||
dd49c038 AF |
199 | sysbus_init_mmio(d, &opp->mem); |
200 | qdev_init_gpio_in(dev, kvm_openpic_set_irq, OPENPIC_MAX_IRQ); | |
d85937e6 SW |
201 | |
202 | opp->mem_listener.region_add = kvm_openpic_region_add; | |
203 | opp->mem_listener.region_add = kvm_openpic_region_del; | |
204 | memory_listener_register(&opp->mem_listener, &address_space_memory); | |
205 | ||
206 | /* indicate pic capabilities */ | |
207 | msi_supported = true; | |
208 | kvm_kernel_irqchip = true; | |
209 | kvm_async_interrupts_allowed = true; | |
210 | ||
211 | /* set up irq routing */ | |
212 | kvm_init_irq_routing(kvm_state); | |
213 | for (i = 0; i < 256; ++i) { | |
214 | kvm_irqchip_add_irq_route(kvm_state, i, 0, i); | |
215 | } | |
216 | ||
217 | kvm_irqfds_allowed = true; | |
218 | kvm_msi_via_irqfd_allowed = true; | |
219 | kvm_gsi_routing_allowed = true; | |
220 | ||
221 | kvm_irqchip_commit_routes(s); | |
d85937e6 SW |
222 | } |
223 | ||
224 | int kvm_openpic_connect_vcpu(DeviceState *d, CPUState *cs) | |
225 | { | |
dd49c038 | 226 | KVMOpenPICState *opp = KVM_OPENPIC(d); |
d85937e6 SW |
227 | struct kvm_enable_cap encap = {}; |
228 | ||
229 | encap.cap = KVM_CAP_IRQ_MPIC; | |
230 | encap.args[0] = opp->fd; | |
231 | encap.args[1] = cs->cpu_index; | |
232 | ||
233 | return kvm_vcpu_ioctl(cs, KVM_ENABLE_CAP, &encap); | |
234 | } | |
235 | ||
236 | static Property kvm_openpic_properties[] = { | |
237 | DEFINE_PROP_UINT32("model", KVMOpenPICState, model, | |
238 | OPENPIC_MODEL_FSL_MPIC_20), | |
239 | DEFINE_PROP_END_OF_LIST(), | |
240 | }; | |
241 | ||
dd49c038 | 242 | static void kvm_openpic_class_init(ObjectClass *oc, void *data) |
d85937e6 | 243 | { |
dd49c038 | 244 | DeviceClass *dc = DEVICE_CLASS(oc); |
d85937e6 | 245 | |
dd49c038 | 246 | dc->realize = kvm_openpic_realize; |
d85937e6 SW |
247 | dc->props = kvm_openpic_properties; |
248 | dc->reset = kvm_openpic_reset; | |
249 | } | |
250 | ||
251 | static const TypeInfo kvm_openpic_info = { | |
dd49c038 | 252 | .name = TYPE_KVM_OPENPIC, |
d85937e6 SW |
253 | .parent = TYPE_SYS_BUS_DEVICE, |
254 | .instance_size = sizeof(KVMOpenPICState), | |
dd49c038 | 255 | .instance_init = kvm_openpic_init, |
d85937e6 SW |
256 | .class_init = kvm_openpic_class_init, |
257 | }; | |
258 | ||
259 | static void kvm_openpic_register_types(void) | |
260 | { | |
261 | type_register_static(&kvm_openpic_info); | |
262 | } | |
263 | ||
264 | type_init(kvm_openpic_register_types) |