]>
Commit | Line | Data |
---|---|---|
5fafdf24 | 1 | /* |
cdbdb648 PB |
2 | * Arm PrimeCell PL190 Vector Interrupt Controller |
3 | * | |
4 | * Copyright (c) 2006 CodeSourcery. | |
5 | * Written by Paul Brook | |
6 | * | |
8e31bf38 | 7 | * This code is licensed under the GPL. |
cdbdb648 PB |
8 | */ |
9 | ||
8ef94f0b | 10 | #include "qemu/osdep.h" |
83c9f4ca | 11 | #include "hw/sysbus.h" |
03dd024f | 12 | #include "qemu/log.h" |
0b8fa32f | 13 | #include "qemu/module.h" |
cdbdb648 PB |
14 | |
15 | /* The number of virtual priority levels. 16 user vectors plus the | |
16 | unvectored IRQ. Chained interrupts would require an additional level | |
17 | if implemented. */ | |
18 | ||
19 | #define PL190_NUM_PRIO 17 | |
20 | ||
7fc3266f AF |
21 | #define TYPE_PL190 "pl190" |
22 | #define PL190(obj) OBJECT_CHECK(PL190State, (obj), TYPE_PL190) | |
23 | ||
aefbc256 | 24 | typedef struct PL190State { |
7fc3266f AF |
25 | SysBusDevice parent_obj; |
26 | ||
7f8293bf | 27 | MemoryRegion iomem; |
cdbdb648 PB |
28 | uint32_t level; |
29 | uint32_t soft_level; | |
30 | uint32_t irq_enable; | |
31 | uint32_t fiq_select; | |
cdbdb648 PB |
32 | uint8_t vect_control[16]; |
33 | uint32_t vect_addr[PL190_NUM_PRIO]; | |
34 | /* Mask containing interrupts with higher priority than this one. */ | |
35 | uint32_t prio_mask[PL190_NUM_PRIO + 1]; | |
36 | int protected; | |
37 | /* Current priority level. */ | |
38 | int priority; | |
39 | int prev_prio[PL190_NUM_PRIO]; | |
d537cf6c PB |
40 | qemu_irq irq; |
41 | qemu_irq fiq; | |
aefbc256 | 42 | } PL190State; |
cdbdb648 PB |
43 | |
44 | static const unsigned char pl190_id[] = | |
45 | { 0x90, 0x11, 0x04, 0x00, 0x0D, 0xf0, 0x05, 0xb1 }; | |
46 | ||
aefbc256 | 47 | static inline uint32_t pl190_irq_level(PL190State *s) |
cdbdb648 PB |
48 | { |
49 | return (s->level | s->soft_level) & s->irq_enable & ~s->fiq_select; | |
50 | } | |
51 | ||
52 | /* Update interrupts. */ | |
aefbc256 | 53 | static void pl190_update(PL190State *s) |
cdbdb648 PB |
54 | { |
55 | uint32_t level = pl190_irq_level(s); | |
56 | int set; | |
57 | ||
58 | set = (level & s->prio_mask[s->priority]) != 0; | |
d537cf6c | 59 | qemu_set_irq(s->irq, set); |
cdbdb648 | 60 | set = ((s->level | s->soft_level) & s->fiq_select) != 0; |
d537cf6c | 61 | qemu_set_irq(s->fiq, set); |
cdbdb648 PB |
62 | } |
63 | ||
64 | static void pl190_set_irq(void *opaque, int irq, int level) | |
65 | { | |
aefbc256 | 66 | PL190State *s = (PL190State *)opaque; |
cdbdb648 PB |
67 | |
68 | if (level) | |
69 | s->level |= 1u << irq; | |
70 | else | |
71 | s->level &= ~(1u << irq); | |
72 | pl190_update(s); | |
73 | } | |
74 | ||
aefbc256 | 75 | static void pl190_update_vectors(PL190State *s) |
cdbdb648 PB |
76 | { |
77 | uint32_t mask; | |
78 | int i; | |
79 | int n; | |
80 | ||
81 | mask = 0; | |
82 | for (i = 0; i < 16; i++) | |
83 | { | |
84 | s->prio_mask[i] = mask; | |
85 | if (s->vect_control[i] & 0x20) | |
86 | { | |
87 | n = s->vect_control[i] & 0x1f; | |
88 | mask |= 1 << n; | |
89 | } | |
90 | } | |
91 | s->prio_mask[16] = mask; | |
92 | pl190_update(s); | |
93 | } | |
94 | ||
a8170e5e | 95 | static uint64_t pl190_read(void *opaque, hwaddr offset, |
7f8293bf | 96 | unsigned size) |
cdbdb648 | 97 | { |
aefbc256 | 98 | PL190State *s = (PL190State *)opaque; |
cdbdb648 PB |
99 | int i; |
100 | ||
cdbdb648 PB |
101 | if (offset >= 0xfe0 && offset < 0x1000) { |
102 | return pl190_id[(offset - 0xfe0) >> 2]; | |
103 | } | |
104 | if (offset >= 0x100 && offset < 0x140) { | |
105 | return s->vect_addr[(offset - 0x100) >> 2]; | |
106 | } | |
107 | if (offset >= 0x200 && offset < 0x240) { | |
108 | return s->vect_control[(offset - 0x200) >> 2]; | |
109 | } | |
110 | switch (offset >> 2) { | |
111 | case 0: /* IRQSTATUS */ | |
112 | return pl190_irq_level(s); | |
113 | case 1: /* FIQSATUS */ | |
114 | return (s->level | s->soft_level) & s->fiq_select; | |
115 | case 2: /* RAWINTR */ | |
116 | return s->level | s->soft_level; | |
117 | case 3: /* INTSELECT */ | |
118 | return s->fiq_select; | |
119 | case 4: /* INTENABLE */ | |
120 | return s->irq_enable; | |
121 | case 6: /* SOFTINT */ | |
122 | return s->soft_level; | |
123 | case 8: /* PROTECTION */ | |
124 | return s->protected; | |
125 | case 12: /* VECTADDR */ | |
126 | /* Read vector address at the start of an ISR. Increases the | |
14c126ba BF |
127 | * current priority level to that of the current interrupt. |
128 | * | |
129 | * Since an enabled interrupt X at priority P causes prio_mask[Y] | |
130 | * to have bit X set for all Y > P, this loop will stop with | |
131 | * i == the priority of the highest priority set interrupt. | |
132 | */ | |
133 | for (i = 0; i < s->priority; i++) { | |
134 | if ((s->level | s->soft_level) & s->prio_mask[i + 1]) { | |
135 | break; | |
136 | } | |
137 | } | |
138 | ||
cdbdb648 PB |
139 | /* Reading this value with no pending interrupts is undefined. |
140 | We return the default address. */ | |
141 | if (i == PL190_NUM_PRIO) | |
142 | return s->vect_addr[16]; | |
143 | if (i < s->priority) | |
144 | { | |
145 | s->prev_prio[i] = s->priority; | |
146 | s->priority = i; | |
147 | pl190_update(s); | |
148 | } | |
149 | return s->vect_addr[s->priority]; | |
150 | case 13: /* DEFVECTADDR */ | |
151 | return s->vect_addr[16]; | |
152 | default: | |
fd271e81 PM |
153 | qemu_log_mask(LOG_GUEST_ERROR, |
154 | "pl190_read: Bad offset %x\n", (int)offset); | |
cdbdb648 PB |
155 | return 0; |
156 | } | |
157 | } | |
158 | ||
a8170e5e | 159 | static void pl190_write(void *opaque, hwaddr offset, |
7f8293bf | 160 | uint64_t val, unsigned size) |
cdbdb648 | 161 | { |
aefbc256 | 162 | PL190State *s = (PL190State *)opaque; |
cdbdb648 | 163 | |
cdbdb648 PB |
164 | if (offset >= 0x100 && offset < 0x140) { |
165 | s->vect_addr[(offset - 0x100) >> 2] = val; | |
166 | pl190_update_vectors(s); | |
167 | return; | |
168 | } | |
169 | if (offset >= 0x200 && offset < 0x240) { | |
170 | s->vect_control[(offset - 0x200) >> 2] = val; | |
171 | pl190_update_vectors(s); | |
172 | return; | |
173 | } | |
174 | switch (offset >> 2) { | |
175 | case 0: /* SELECT */ | |
176 | /* This is a readonly register, but linux tries to write to it | |
177 | anyway. Ignore the write. */ | |
178 | break; | |
179 | case 3: /* INTSELECT */ | |
180 | s->fiq_select = val; | |
181 | break; | |
182 | case 4: /* INTENABLE */ | |
183 | s->irq_enable |= val; | |
184 | break; | |
185 | case 5: /* INTENCLEAR */ | |
186 | s->irq_enable &= ~val; | |
187 | break; | |
188 | case 6: /* SOFTINT */ | |
189 | s->soft_level |= val; | |
190 | break; | |
191 | case 7: /* SOFTINTCLEAR */ | |
192 | s->soft_level &= ~val; | |
193 | break; | |
194 | case 8: /* PROTECTION */ | |
195 | /* TODO: Protection (supervisor only access) is not implemented. */ | |
196 | s->protected = val & 1; | |
197 | break; | |
198 | case 12: /* VECTADDR */ | |
199 | /* Restore the previous priority level. The value written is | |
200 | ignored. */ | |
201 | if (s->priority < PL190_NUM_PRIO) | |
202 | s->priority = s->prev_prio[s->priority]; | |
203 | break; | |
204 | case 13: /* DEFVECTADDR */ | |
730986e4 | 205 | s->vect_addr[16] = val; |
cdbdb648 PB |
206 | break; |
207 | case 0xc0: /* ITCR */ | |
2ac71179 | 208 | if (val) { |
2d746989 | 209 | qemu_log_mask(LOG_UNIMP, "pl190: Test mode not implemented\n"); |
2ac71179 | 210 | } |
cdbdb648 PB |
211 | break; |
212 | default: | |
fd271e81 PM |
213 | qemu_log_mask(LOG_GUEST_ERROR, |
214 | "pl190_write: Bad offset %x\n", (int)offset); | |
cdbdb648 PB |
215 | return; |
216 | } | |
217 | pl190_update(s); | |
218 | } | |
219 | ||
7f8293bf AK |
220 | static const MemoryRegionOps pl190_ops = { |
221 | .read = pl190_read, | |
222 | .write = pl190_write, | |
223 | .endianness = DEVICE_NATIVE_ENDIAN, | |
cdbdb648 PB |
224 | }; |
225 | ||
ac49d750 | 226 | static void pl190_reset(DeviceState *d) |
cdbdb648 | 227 | { |
7fc3266f AF |
228 | PL190State *s = PL190(d); |
229 | int i; | |
cdbdb648 | 230 | |
7fc3266f AF |
231 | for (i = 0; i < 16; i++) { |
232 | s->vect_addr[i] = 0; | |
233 | s->vect_control[i] = 0; | |
cdbdb648 | 234 | } |
7fc3266f AF |
235 | s->vect_addr[16] = 0; |
236 | s->prio_mask[17] = 0xffffffff; | |
237 | s->priority = PL190_NUM_PRIO; | |
238 | pl190_update_vectors(s); | |
cdbdb648 PB |
239 | } |
240 | ||
e3be8b4f | 241 | static void pl190_init(Object *obj) |
cdbdb648 | 242 | { |
e3be8b4f XZ |
243 | DeviceState *dev = DEVICE(obj); |
244 | PL190State *s = PL190(obj); | |
245 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | |
cdbdb648 | 246 | |
e3be8b4f | 247 | memory_region_init_io(&s->iomem, obj, &pl190_ops, s, "pl190", 0x1000); |
7fc3266f AF |
248 | sysbus_init_mmio(sbd, &s->iomem); |
249 | qdev_init_gpio_in(dev, pl190_set_irq, 32); | |
250 | sysbus_init_irq(sbd, &s->irq); | |
251 | sysbus_init_irq(sbd, &s->fiq); | |
cdbdb648 | 252 | } |
97aff481 | 253 | |
ac49d750 PM |
254 | static const VMStateDescription vmstate_pl190 = { |
255 | .name = "pl190", | |
256 | .version_id = 1, | |
257 | .minimum_version_id = 1, | |
258 | .fields = (VMStateField[]) { | |
aefbc256 AF |
259 | VMSTATE_UINT32(level, PL190State), |
260 | VMSTATE_UINT32(soft_level, PL190State), | |
261 | VMSTATE_UINT32(irq_enable, PL190State), | |
262 | VMSTATE_UINT32(fiq_select, PL190State), | |
263 | VMSTATE_UINT8_ARRAY(vect_control, PL190State, 16), | |
264 | VMSTATE_UINT32_ARRAY(vect_addr, PL190State, PL190_NUM_PRIO), | |
265 | VMSTATE_UINT32_ARRAY(prio_mask, PL190State, PL190_NUM_PRIO+1), | |
266 | VMSTATE_INT32(protected, PL190State), | |
267 | VMSTATE_INT32(priority, PL190State), | |
268 | VMSTATE_INT32_ARRAY(prev_prio, PL190State, PL190_NUM_PRIO), | |
ac49d750 PM |
269 | VMSTATE_END_OF_LIST() |
270 | } | |
271 | }; | |
272 | ||
999e12bb AL |
273 | static void pl190_class_init(ObjectClass *klass, void *data) |
274 | { | |
39bffca2 | 275 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 276 | |
39bffca2 AL |
277 | dc->reset = pl190_reset; |
278 | dc->vmsd = &vmstate_pl190; | |
999e12bb AL |
279 | } |
280 | ||
8c43a6f0 | 281 | static const TypeInfo pl190_info = { |
7fc3266f | 282 | .name = TYPE_PL190, |
39bffca2 | 283 | .parent = TYPE_SYS_BUS_DEVICE, |
aefbc256 | 284 | .instance_size = sizeof(PL190State), |
e3be8b4f | 285 | .instance_init = pl190_init, |
39bffca2 | 286 | .class_init = pl190_class_init, |
ac49d750 PM |
287 | }; |
288 | ||
83f7d43a | 289 | static void pl190_register_types(void) |
97aff481 | 290 | { |
39bffca2 | 291 | type_register_static(&pl190_info); |
97aff481 PB |
292 | } |
293 | ||
83f7d43a | 294 | type_init(pl190_register_types) |