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Commit | Line | Data |
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5c8556a6 GX |
1 | /* |
2 | * INTC device simulation in PKUnity SoC | |
3 | * | |
4 | * Copyright (C) 2010-2012 Guan Xuetao | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation, or any later version. | |
9 | * See the COPYING file in the top-level directory. | |
10 | */ | |
0b8fa32f | 11 | |
5af98cc5 | 12 | #include "qemu/osdep.h" |
64552b6b | 13 | #include "hw/irq.h" |
83c9f4ca | 14 | #include "hw/sysbus.h" |
db1015e9 | 15 | #include "qom/object.h" |
5c8556a6 GX |
16 | |
17 | #undef DEBUG_PUV3 | |
0d09e41a | 18 | #include "hw/unicore32/puv3.h" |
0b8fa32f | 19 | #include "qemu/module.h" |
3b34ee67 | 20 | #include "qemu/log.h" |
5c8556a6 | 21 | |
1ecdf402 | 22 | #define TYPE_PUV3_INTC "puv3_intc" |
db1015e9 | 23 | typedef struct PUV3INTCState PUV3INTCState; |
8110fa1d EH |
24 | DECLARE_INSTANCE_CHECKER(PUV3INTCState, PUV3_INTC, |
25 | TYPE_PUV3_INTC) | |
1ecdf402 | 26 | |
db1015e9 | 27 | struct PUV3INTCState { |
1ecdf402 AF |
28 | SysBusDevice parent_obj; |
29 | ||
5c8556a6 GX |
30 | MemoryRegion iomem; |
31 | qemu_irq parent_irq; | |
32 | ||
33 | uint32_t reg_ICMR; | |
34 | uint32_t reg_ICPR; | |
db1015e9 | 35 | }; |
5c8556a6 GX |
36 | |
37 | /* Update interrupt status after enabled or pending bits have been changed. */ | |
38 | static void puv3_intc_update(PUV3INTCState *s) | |
39 | { | |
40 | if (s->reg_ICMR & s->reg_ICPR) { | |
41 | qemu_irq_raise(s->parent_irq); | |
42 | } else { | |
43 | qemu_irq_lower(s->parent_irq); | |
44 | } | |
45 | } | |
46 | ||
47 | /* Process a change in an external INTC input. */ | |
48 | static void puv3_intc_handler(void *opaque, int irq, int level) | |
49 | { | |
50 | PUV3INTCState *s = opaque; | |
51 | ||
52 | DPRINTF("irq 0x%x, level 0x%x\n", irq, level); | |
53 | if (level) { | |
54 | s->reg_ICPR |= (1 << irq); | |
55 | } else { | |
56 | s->reg_ICPR &= ~(1 << irq); | |
57 | } | |
58 | puv3_intc_update(s); | |
59 | } | |
60 | ||
a8170e5e | 61 | static uint64_t puv3_intc_read(void *opaque, hwaddr offset, |
5c8556a6 GX |
62 | unsigned size) |
63 | { | |
64 | PUV3INTCState *s = opaque; | |
65 | uint32_t ret = 0; | |
66 | ||
67 | switch (offset) { | |
68 | case 0x04: /* INTC_ICMR */ | |
69 | ret = s->reg_ICMR; | |
70 | break; | |
71 | case 0x0c: /* INTC_ICIP */ | |
72 | ret = s->reg_ICPR; /* the same value with ICPR */ | |
73 | break; | |
74 | default: | |
3b34ee67 PMD |
75 | qemu_log_mask(LOG_GUEST_ERROR, |
76 | "%s: Bad read offset 0x%"HWADDR_PRIx"\n", | |
77 | __func__, offset); | |
5c8556a6 GX |
78 | } |
79 | DPRINTF("offset 0x%x, value 0x%x\n", offset, ret); | |
80 | return ret; | |
81 | } | |
82 | ||
a8170e5e | 83 | static void puv3_intc_write(void *opaque, hwaddr offset, |
5c8556a6 GX |
84 | uint64_t value, unsigned size) |
85 | { | |
86 | PUV3INTCState *s = opaque; | |
87 | ||
88 | DPRINTF("offset 0x%x, value 0x%x\n", offset, value); | |
89 | switch (offset) { | |
90 | case 0x00: /* INTC_ICLR */ | |
91 | case 0x14: /* INTC_ICCR */ | |
92 | break; | |
93 | case 0x04: /* INTC_ICMR */ | |
94 | s->reg_ICMR = value; | |
95 | break; | |
96 | default: | |
3b34ee67 PMD |
97 | qemu_log_mask(LOG_GUEST_ERROR, |
98 | "%s: Bad write offset 0x%"HWADDR_PRIx"\n", | |
99 | __func__, offset); | |
5c8556a6 GX |
100 | return; |
101 | } | |
102 | puv3_intc_update(s); | |
103 | } | |
104 | ||
105 | static const MemoryRegionOps puv3_intc_ops = { | |
106 | .read = puv3_intc_read, | |
107 | .write = puv3_intc_write, | |
108 | .impl = { | |
109 | .min_access_size = 4, | |
110 | .max_access_size = 4, | |
111 | }, | |
112 | .endianness = DEVICE_NATIVE_ENDIAN, | |
113 | }; | |
114 | ||
2f59de88 | 115 | static void puv3_intc_realize(DeviceState *dev, Error **errp) |
5c8556a6 | 116 | { |
1ecdf402 | 117 | PUV3INTCState *s = PUV3_INTC(dev); |
2f59de88 | 118 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
5c8556a6 | 119 | |
1ecdf402 AF |
120 | qdev_init_gpio_in(dev, puv3_intc_handler, PUV3_IRQS_NR); |
121 | sysbus_init_irq(sbd, &s->parent_irq); | |
5c8556a6 GX |
122 | |
123 | s->reg_ICMR = 0; | |
124 | s->reg_ICPR = 0; | |
125 | ||
1437c94b | 126 | memory_region_init_io(&s->iomem, OBJECT(s), &puv3_intc_ops, s, "puv3_intc", |
1ecdf402 AF |
127 | PUV3_REGS_OFFSET); |
128 | sysbus_init_mmio(sbd, &s->iomem); | |
5c8556a6 GX |
129 | } |
130 | ||
131 | static void puv3_intc_class_init(ObjectClass *klass, void *data) | |
132 | { | |
2f59de88 MZ |
133 | DeviceClass *dc = DEVICE_CLASS(klass); |
134 | dc->realize = puv3_intc_realize; | |
5c8556a6 GX |
135 | } |
136 | ||
137 | static const TypeInfo puv3_intc_info = { | |
1ecdf402 | 138 | .name = TYPE_PUV3_INTC, |
5c8556a6 GX |
139 | .parent = TYPE_SYS_BUS_DEVICE, |
140 | .instance_size = sizeof(PUV3INTCState), | |
141 | .class_init = puv3_intc_class_init, | |
142 | }; | |
143 | ||
144 | static void puv3_intc_register_type(void) | |
145 | { | |
146 | type_register_static(&puv3_intc_info); | |
147 | } | |
148 | ||
149 | type_init(puv3_intc_register_type) |