[mirror_qemu.git] / hw / intc / riscv_aclint.c

/*
 * RISC-V ACLINT (Advanced Core Local Interruptor)
 * URL: https://github.com/riscv/riscv-aclint
 *
 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
 * Copyright (c) 2017 SiFive, Inc.
 * Copyright (c) 2021 Western Digital Corporation or its affiliates.
 *
 * This provides real-time clock, timer and interprocessor interrupts.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2 or later, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "qemu/log.h"
#include "qemu/module.h"
#include "hw/sysbus.h"
#include "target/riscv/cpu.h"
#include "hw/qdev-properties.h"
#include "hw/intc/riscv_aclint.h"
#include "qemu/timer.h"
#include "hw/irq.h"

typedef struct riscv_aclint_mtimer_callback {
    RISCVAclintMTimerState *s;
    int num;
} riscv_aclint_mtimer_callback;

static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq)
{
    return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
        timebase_freq, NANOSECONDS_PER_SECOND);
}

/*
 * Called when timecmp is written to update the QEMU timer or immediately
 * trigger timer interrupt if mtimecmp <= current timer value.
 */
static void riscv_aclint_mtimer_write_timecmp(RISCVAclintMTimerState *mtimer,
                                              RISCVCPU *cpu,
                                              int hartid,
                                              uint64_t value,
                                              uint32_t timebase_freq)
{
    uint64_t next;
    uint64_t diff;

    uint64_t rtc_r = cpu_riscv_read_rtc(timebase_freq);

    cpu->env.timecmp = value;
    if (cpu->env.timecmp <= rtc_r) {
        /*
         * If we're setting an MTIMECMP value in the "past",
         * immediately raise the timer interrupt
         */
        qemu_irq_raise(mtimer->timer_irqs[hartid - mtimer->hartid_base]);
        return;
    }

    /* otherwise, set up the future timer interrupt */
    qemu_irq_lower(mtimer->timer_irqs[hartid - mtimer->hartid_base]);
    diff = cpu->env.timecmp - rtc_r;
    /* back to ns (note args switched in muldiv64) */
    uint64_t ns_diff = muldiv64(diff, NANOSECONDS_PER_SECOND, timebase_freq);

    /*
     * check if ns_diff overflowed and check if the addition would potentially
     * overflow
     */
    if ((NANOSECONDS_PER_SECOND > timebase_freq && ns_diff < diff) ||
        ns_diff > INT64_MAX) {
        next = INT64_MAX;
    } else {
        /*
         * as it is very unlikely qemu_clock_get_ns will return a value
         * greater than INT64_MAX, no additional check is needed for an
         * unsigned integer overflow.
         */
        next = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + ns_diff;
        /*
         * if ns_diff is INT64_MAX next may still be outside the range
         * of a signed integer.
         */
        next = MIN(next, INT64_MAX);
    }

    timer_mod(cpu->env.timer, next);
}

/*
 * Callback used when the timer set using timer_mod expires.
 * Should raise the timer interrupt line
 */
static void riscv_aclint_mtimer_cb(void *opaque)
{
    riscv_aclint_mtimer_callback *state = opaque;

    qemu_irq_raise(state->s->timer_irqs[state->num]);
}

/* CPU read MTIMER register */
static uint64_t riscv_aclint_mtimer_read(void *opaque, hwaddr addr,
    unsigned size)
{
    RISCVAclintMTimerState *mtimer = opaque;

    if (addr >= mtimer->timecmp_base &&
        addr < (mtimer->timecmp_base + (mtimer->num_harts << 3))) {
        size_t hartid = mtimer->hartid_base +
                        ((addr - mtimer->timecmp_base) >> 3);
        CPUState *cpu = qemu_get_cpu(hartid);
        CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
        if (!env) {
            qemu_log_mask(LOG_GUEST_ERROR,
                          "aclint-mtimer: invalid hartid: %zu", hartid);
        } else if ((addr & 0x7) == 0) {
            /* timecmp_lo */
            uint64_t timecmp = env->timecmp;
            return timecmp & 0xFFFFFFFF;
        } else if ((addr & 0x7) == 4) {
            /* timecmp_hi */
            uint64_t timecmp = env->timecmp;
            return (timecmp >> 32) & 0xFFFFFFFF;
        } else {
            qemu_log_mask(LOG_UNIMP,
                          "aclint-mtimer: invalid read: %08x", (uint32_t)addr);
            return 0;
        }
    } else if (addr == mtimer->time_base) {
        /* time_lo */
        return cpu_riscv_read_rtc(mtimer->timebase_freq) & 0xFFFFFFFF;
    } else if (addr == mtimer->time_base + 4) {
        /* time_hi */
        return (cpu_riscv_read_rtc(mtimer->timebase_freq) >> 32) & 0xFFFFFFFF;
    }

    qemu_log_mask(LOG_UNIMP,
                  "aclint-mtimer: invalid read: %08x", (uint32_t)addr);
    return 0;
}

/* CPU write MTIMER register */
static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr,
    uint64_t value, unsigned size)
{
    RISCVAclintMTimerState *mtimer = opaque;

    if (addr >= mtimer->timecmp_base &&
        addr < (mtimer->timecmp_base + (mtimer->num_harts << 3))) {
        size_t hartid = mtimer->hartid_base +
                        ((addr - mtimer->timecmp_base) >> 3);
        CPUState *cpu = qemu_get_cpu(hartid);
        CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
        if (!env) {
            qemu_log_mask(LOG_GUEST_ERROR,
                          "aclint-mtimer: invalid hartid: %zu", hartid);
        } else if ((addr & 0x7) == 0) {
            /* timecmp_lo */
            uint64_t timecmp_hi = env->timecmp >> 32;
            riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid,
                timecmp_hi << 32 | (value & 0xFFFFFFFF),
                mtimer->timebase_freq);
            return;
        } else if ((addr & 0x7) == 4) {
            /* timecmp_hi */
            uint64_t timecmp_lo = env->timecmp;
            riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid,
                value << 32 | (timecmp_lo & 0xFFFFFFFF),
                mtimer->timebase_freq);
        } else {
            qemu_log_mask(LOG_UNIMP,
                          "aclint-mtimer: invalid timecmp write: %08x",
                          (uint32_t)addr);
        }
        return;
    } else if (addr == mtimer->time_base) {
        /* time_lo */
        qemu_log_mask(LOG_UNIMP,
                      "aclint-mtimer: time_lo write not implemented");
        return;
    } else if (addr == mtimer->time_base + 4) {
        /* time_hi */
        qemu_log_mask(LOG_UNIMP,
                      "aclint-mtimer: time_hi write not implemented");
        return;
    }

    qemu_log_mask(LOG_UNIMP,
                  "aclint-mtimer: invalid write: %08x", (uint32_t)addr);
}

static const MemoryRegionOps riscv_aclint_mtimer_ops = {
    .read = riscv_aclint_mtimer_read,
    .write = riscv_aclint_mtimer_write,
    .endianness = DEVICE_LITTLE_ENDIAN,
    .valid = {
        .min_access_size = 4,
        .max_access_size = 8
    },
    .impl = {
        .min_access_size = 4,
        .max_access_size = 8,
    }
};

static Property riscv_aclint_mtimer_properties[] = {
    DEFINE_PROP_UINT32("hartid-base", RISCVAclintMTimerState,
        hartid_base, 0),
    DEFINE_PROP_UINT32("num-harts", RISCVAclintMTimerState, num_harts, 1),
    DEFINE_PROP_UINT32("timecmp-base", RISCVAclintMTimerState,
        timecmp_base, RISCV_ACLINT_DEFAULT_MTIMECMP),
    DEFINE_PROP_UINT32("time-base", RISCVAclintMTimerState,
        time_base, RISCV_ACLINT_DEFAULT_MTIME),
    DEFINE_PROP_UINT32("aperture-size", RISCVAclintMTimerState,
        aperture_size, RISCV_ACLINT_DEFAULT_MTIMER_SIZE),
    DEFINE_PROP_UINT32("timebase-freq", RISCVAclintMTimerState,
        timebase_freq, 0),
    DEFINE_PROP_END_OF_LIST(),
};

static void riscv_aclint_mtimer_realize(DeviceState *dev, Error **errp)
{
    RISCVAclintMTimerState *s = RISCV_ACLINT_MTIMER(dev);
    int i;

    memory_region_init_io(&s->mmio, OBJECT(dev), &riscv_aclint_mtimer_ops,
                          s, TYPE_RISCV_ACLINT_MTIMER, s->aperture_size);
    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);

    s->timer_irqs = g_new(qemu_irq, s->num_harts);
    qdev_init_gpio_out(dev, s->timer_irqs, s->num_harts);

    /* Claim timer interrupt bits */
    for (i = 0; i < s->num_harts; i++) {
        RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(s->hartid_base + i));
        if (riscv_cpu_claim_interrupts(cpu, MIP_MTIP) < 0) {
            error_report("MTIP already claimed");
            exit(1);
        }
    }
}

static void riscv_aclint_mtimer_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    dc->realize = riscv_aclint_mtimer_realize;
    device_class_set_props(dc, riscv_aclint_mtimer_properties);
}

static const TypeInfo riscv_aclint_mtimer_info = {
    .name          = TYPE_RISCV_ACLINT_MTIMER,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(RISCVAclintMTimerState),
    .class_init    = riscv_aclint_mtimer_class_init,
};

/*
 * Create ACLINT MTIMER device.
 */
DeviceState *riscv_aclint_mtimer_create(hwaddr addr, hwaddr size,
    uint32_t hartid_base, uint32_t num_harts,
    uint32_t timecmp_base, uint32_t time_base, uint32_t timebase_freq,
    bool provide_rdtime)
{
    int i;
    DeviceState *dev = qdev_new(TYPE_RISCV_ACLINT_MTIMER);

    assert(num_harts <= RISCV_ACLINT_MAX_HARTS);
    assert(!(addr & 0x7));
    assert(!(timecmp_base & 0x7));
    assert(!(time_base & 0x7));

    qdev_prop_set_uint32(dev, "hartid-base", hartid_base);
    qdev_prop_set_uint32(dev, "num-harts", num_harts);
    qdev_prop_set_uint32(dev, "timecmp-base", timecmp_base);
    qdev_prop_set_uint32(dev, "time-base", time_base);
    qdev_prop_set_uint32(dev, "aperture-size", size);
    qdev_prop_set_uint32(dev, "timebase-freq", timebase_freq);
    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);

    for (i = 0; i < num_harts; i++) {
        CPUState *cpu = qemu_get_cpu(hartid_base + i);
        RISCVCPU *rvcpu = RISCV_CPU(cpu);
        CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
        riscv_aclint_mtimer_callback *cb =
            g_new0(riscv_aclint_mtimer_callback, 1);

        if (!env) {
            g_free(cb);
            continue;
        }
        if (provide_rdtime) {
            riscv_cpu_set_rdtime_fn(env, cpu_riscv_read_rtc, timebase_freq);
        }

        cb->s = RISCV_ACLINT_MTIMER(dev);
        cb->num = i;
        env->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
                                  &riscv_aclint_mtimer_cb, cb);
        env->timecmp = 0;

        qdev_connect_gpio_out(dev, i,
                              qdev_get_gpio_in(DEVICE(rvcpu), IRQ_M_TIMER));
    }

    return dev;
}

/* CPU read [M|S]SWI register */
static uint64_t riscv_aclint_swi_read(void *opaque, hwaddr addr,
    unsigned size)
{
    RISCVAclintSwiState *swi = opaque;

    if (addr < (swi->num_harts << 2)) {
        size_t hartid = swi->hartid_base + (addr >> 2);
        CPUState *cpu = qemu_get_cpu(hartid);
        CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
        if (!env) {
            qemu_log_mask(LOG_GUEST_ERROR,
                          "aclint-swi: invalid hartid: %zu", hartid);
        } else if ((addr & 0x3) == 0) {
            return (swi->sswi) ? 0 : ((env->mip & MIP_MSIP) > 0);
        }
    }

    qemu_log_mask(LOG_UNIMP,
                  "aclint-swi: invalid read: %08x", (uint32_t)addr);
    return 0;
}

/* CPU write [M|S]SWI register */
static void riscv_aclint_swi_write(void *opaque, hwaddr addr, uint64_t value,
        unsigned size)
{
    RISCVAclintSwiState *swi = opaque;

    if (addr < (swi->num_harts << 2)) {
        size_t hartid = swi->hartid_base + (addr >> 2);
        CPUState *cpu = qemu_get_cpu(hartid);
        CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
        if (!env) {
            qemu_log_mask(LOG_GUEST_ERROR,
                          "aclint-swi: invalid hartid: %zu", hartid);
        } else if ((addr & 0x3) == 0) {
            if (value & 0x1) {
                qemu_irq_raise(swi->soft_irqs[hartid - swi->hartid_base]);
            } else {
                if (!swi->sswi) {
                    qemu_irq_lower(swi->soft_irqs[hartid - swi->hartid_base]);
                }
            }
            return;
        }
    }

    qemu_log_mask(LOG_UNIMP,
                  "aclint-swi: invalid write: %08x", (uint32_t)addr);
}

static const MemoryRegionOps riscv_aclint_swi_ops = {
    .read = riscv_aclint_swi_read,
    .write = riscv_aclint_swi_write,
    .endianness = DEVICE_LITTLE_ENDIAN,
    .valid = {
        .min_access_size = 4,
        .max_access_size = 4
    }
};

static Property riscv_aclint_swi_properties[] = {
    DEFINE_PROP_UINT32("hartid-base", RISCVAclintSwiState, hartid_base, 0),
    DEFINE_PROP_UINT32("num-harts", RISCVAclintSwiState, num_harts, 1),
    DEFINE_PROP_UINT32("sswi", RISCVAclintSwiState, sswi, false),
    DEFINE_PROP_END_OF_LIST(),
};

static void riscv_aclint_swi_realize(DeviceState *dev, Error **errp)
{
    RISCVAclintSwiState *swi = RISCV_ACLINT_SWI(dev);
    int i;

    memory_region_init_io(&swi->mmio, OBJECT(dev), &riscv_aclint_swi_ops, swi,
                          TYPE_RISCV_ACLINT_SWI, RISCV_ACLINT_SWI_SIZE);
    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &swi->mmio);

    swi->soft_irqs = g_new(qemu_irq, swi->num_harts);
    qdev_init_gpio_out(dev, swi->soft_irqs, swi->num_harts);

    /* Claim software interrupt bits */
    for (i = 0; i < swi->num_harts; i++) {
        RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(swi->hartid_base + i));
        /* We don't claim mip.SSIP because it is writeable by software */
        if (riscv_cpu_claim_interrupts(cpu, swi->sswi ? 0 : MIP_MSIP) < 0) {
            error_report("MSIP already claimed");
            exit(1);
        }
    }
}

static void riscv_aclint_swi_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    dc->realize = riscv_aclint_swi_realize;
    device_class_set_props(dc, riscv_aclint_swi_properties);
}

static const TypeInfo riscv_aclint_swi_info = {
    .name          = TYPE_RISCV_ACLINT_SWI,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(RISCVAclintSwiState),
    .class_init    = riscv_aclint_swi_class_init,
};

/*
 * Create ACLINT [M|S]SWI device.
 */
DeviceState *riscv_aclint_swi_create(hwaddr addr, uint32_t hartid_base,
    uint32_t num_harts, bool sswi)
{
    int i;
    DeviceState *dev = qdev_new(TYPE_RISCV_ACLINT_SWI);

    assert(num_harts <= RISCV_ACLINT_MAX_HARTS);
    assert(!(addr & 0x3));

    qdev_prop_set_uint32(dev, "hartid-base", hartid_base);
    qdev_prop_set_uint32(dev, "num-harts", num_harts);
    qdev_prop_set_uint32(dev, "sswi", sswi ? true : false);
    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);

    for (i = 0; i < num_harts; i++) {
        CPUState *cpu = qemu_get_cpu(hartid_base + i);
        RISCVCPU *rvcpu = RISCV_CPU(cpu);

        qdev_connect_gpio_out(dev, i,
                              qdev_get_gpio_in(DEVICE(rvcpu),
                                  (sswi) ? IRQ_S_SOFT : IRQ_M_SOFT));
    }

    return dev;
}

static void riscv_aclint_register_types(void)
{
    type_register_static(&riscv_aclint_mtimer_info);
    type_register_static(&riscv_aclint_swi_info);
}

type_init(riscv_aclint_register_types)
Commit	Line	Data
1c77c410	1	/*
b8fb878a AP	2	* RISC-V ACLINT (Advanced Core Local Interruptor)
b8fb878a AP	3	* URL: https://github.com/riscv/riscv-aclint
1c77c410 MC	4	*
	5	* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
	6	* Copyright (c) 2017 SiFive, Inc.
b8fb878a	7	* Copyright (c) 2021 Western Digital Corporation or its affiliates.
1c77c410 MC	8	*
	9	* This provides real-time clock, timer and interprocessor interrupts.
	10	*
	11	* This program is free software; you can redistribute it and/or modify it
	12	* under the terms and conditions of the GNU General Public License,
	13	* version 2 or later, as published by the Free Software Foundation.
	14	*
	15	* This program is distributed in the hope it will be useful, but WITHOUT
	16	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	17	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	18	* more details.
	19	*
	20	* You should have received a copy of the GNU General Public License along with
	21	* this program. If not, see <http://www.gnu.org/licenses/>.
	22	*/
	23
	24	#include "qemu/osdep.h"
3e80f690	25	#include "qapi/error.h"
1c77c410	26	#include "qemu/error-report.h"
b8fb878a	27	#include "qemu/log.h"
0b8fa32f	28	#include "qemu/module.h"
1c77c410 MC	29	#include "hw/sysbus.h"
1c77c410 MC	30	#include "target/riscv/cpu.h"
a27bd6c7	31	#include "hw/qdev-properties.h"
cc63a182	32	#include "hw/intc/riscv_aclint.h"
1c77c410	33	#include "qemu/timer.h"
a714b8aa AF	34	#include "hw/irq.h"
a714b8aa AF	35
b8fb878a AP	36	typedef struct riscv_aclint_mtimer_callback {
b8fb878a AP	37	RISCVAclintMTimerState *s;
a714b8aa	38	int num;
b8fb878a	39	} riscv_aclint_mtimer_callback;
1c77c410	40
a47ef6e9	41	static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq)
1c77c410	42	{
2a8756ed	43	return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
a47ef6e9	44	timebase_freq, NANOSECONDS_PER_SECOND);
1c77c410 MC	45	}
	46
	47	/*
	48	* Called when timecmp is written to update the QEMU timer or immediately
	49	* trigger timer interrupt if mtimecmp <= current timer value.
	50	*/
b8fb878a AP	51	static void riscv_aclint_mtimer_write_timecmp(RISCVAclintMTimerState *mtimer,
	52	RISCVCPU *cpu,
	53	int hartid,
	54	uint64_t value,
	55	uint32_t timebase_freq)
1c77c410 MC	56	{
	57	uint64_t next;
	58	uint64_t diff;
	59
a47ef6e9	60	uint64_t rtc_r = cpu_riscv_read_rtc(timebase_freq);
1c77c410 MC	61
	62	cpu->env.timecmp = value;
	63	if (cpu->env.timecmp <= rtc_r) {
b8fb878a AP	64	/*
	65	* If we're setting an MTIMECMP value in the "past",
	66	* immediately raise the timer interrupt
	67	*/
	68	qemu_irq_raise(mtimer->timer_irqs[hartid - mtimer->hartid_base]);
1c77c410 MC	69	return;
	70	}
	71
	72	/* otherwise, set up the future timer interrupt */
b8fb878a	73	qemu_irq_lower(mtimer->timer_irqs[hartid - mtimer->hartid_base]);
1c77c410 MC	74	diff = cpu->env.timecmp - rtc_r;
1c77c410 MC	75	/* back to ns (note args switched in muldiv64) */
4dc06bb8 DH	76	uint64_t ns_diff = muldiv64(diff, NANOSECONDS_PER_SECOND, timebase_freq);
	77
	78	/*
	79	* check if ns_diff overflowed and check if the addition would potentially
	80	* overflow
	81	*/
	82	if ((NANOSECONDS_PER_SECOND > timebase_freq && ns_diff < diff) \|\|
	83	ns_diff > INT64_MAX) {
	84	next = INT64_MAX;
	85	} else {
	86	/*
	87	* as it is very unlikely qemu_clock_get_ns will return a value
	88	* greater than INT64_MAX, no additional check is needed for an
	89	* unsigned integer overflow.
	90	*/
	91	next = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + ns_diff;
	92	/*
	93	* if ns_diff is INT64_MAX next may still be outside the range
	94	* of a signed integer.
	95	*/
	96	next = MIN(next, INT64_MAX);
	97	}
	98
1c77c410 MC	99	timer_mod(cpu->env.timer, next);
	100	}
	101
	102	/*
	103	* Callback used when the timer set using timer_mod expires.
	104	* Should raise the timer interrupt line
	105	*/
b8fb878a	106	static void riscv_aclint_mtimer_cb(void *opaque)
1c77c410	107	{
b8fb878a	108	riscv_aclint_mtimer_callback *state = opaque;
a714b8aa AF	109
a714b8aa AF	110	qemu_irq_raise(state->s->timer_irqs[state->num]);
1c77c410 MC	111	}
1c77c410 MC	112
b8fb878a AP	113	/* CPU read MTIMER register */
	114	static uint64_t riscv_aclint_mtimer_read(void *opaque, hwaddr addr,
	115	unsigned size)
1c77c410	116	{
b8fb878a AP	117	RISCVAclintMTimerState *mtimer = opaque;
	118
	119	if (addr >= mtimer->timecmp_base &&
	120	addr < (mtimer->timecmp_base + (mtimer->num_harts << 3))) {
	121	size_t hartid = mtimer->hartid_base +
	122	((addr - mtimer->timecmp_base) >> 3);
1c77c410 MC	123	CPUState *cpu = qemu_get_cpu(hartid);
	124	CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
	125	if (!env) {
b8fb878a AP	126	qemu_log_mask(LOG_GUEST_ERROR,
b8fb878a AP	127	"aclint-mtimer: invalid hartid: %zu", hartid);
1c77c410 MC	128	} else if ((addr & 0x7) == 0) {
	129	/* timecmp_lo */
	130	uint64_t timecmp = env->timecmp;
	131	return timecmp & 0xFFFFFFFF;
	132	} else if ((addr & 0x7) == 4) {
	133	/* timecmp_hi */
	134	uint64_t timecmp = env->timecmp;
	135	return (timecmp >> 32) & 0xFFFFFFFF;
	136	} else {
b8fb878a AP	137	qemu_log_mask(LOG_UNIMP,
b8fb878a AP	138	"aclint-mtimer: invalid read: %08x", (uint32_t)addr);
1c77c410 MC	139	return 0;
1c77c410 MC	140	}
b8fb878a	141	} else if (addr == mtimer->time_base) {
1c77c410	142	/* time_lo */
b8fb878a AP	143	return cpu_riscv_read_rtc(mtimer->timebase_freq) & 0xFFFFFFFF;
b8fb878a AP	144	} else if (addr == mtimer->time_base + 4) {
1c77c410	145	/* time_hi */
b8fb878a	146	return (cpu_riscv_read_rtc(mtimer->timebase_freq) >> 32) & 0xFFFFFFFF;
1c77c410 MC	147	}
1c77c410 MC	148
b8fb878a AP	149	qemu_log_mask(LOG_UNIMP,
b8fb878a AP	150	"aclint-mtimer: invalid read: %08x", (uint32_t)addr);
1c77c410 MC	151	return 0;
	152	}
	153
b8fb878a AP	154	/* CPU write MTIMER register */
	155	static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr,
	156	uint64_t value, unsigned size)
1c77c410	157	{
b8fb878a	158	RISCVAclintMTimerState *mtimer = opaque;
1c77c410	159
b8fb878a AP	160	if (addr >= mtimer->timecmp_base &&
	161	addr < (mtimer->timecmp_base + (mtimer->num_harts << 3))) {
	162	size_t hartid = mtimer->hartid_base +
	163	((addr - mtimer->timecmp_base) >> 3);
1c77c410 MC	164	CPUState *cpu = qemu_get_cpu(hartid);
	165	CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
	166	if (!env) {
b8fb878a AP	167	qemu_log_mask(LOG_GUEST_ERROR,
b8fb878a AP	168	"aclint-mtimer: invalid hartid: %zu", hartid);
1c77c410 MC	169	} else if ((addr & 0x7) == 0) {
1c77c410 MC	170	/* timecmp_lo */
ef9e41df	171	uint64_t timecmp_hi = env->timecmp >> 32;
b8fb878a AP	172	riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid,
	173	timecmp_hi << 32 \| (value & 0xFFFFFFFF),
	174	mtimer->timebase_freq);
1c77c410 MC	175	return;
	176	} else if ((addr & 0x7) == 4) {
	177	/* timecmp_hi */
ef9e41df	178	uint64_t timecmp_lo = env->timecmp;
b8fb878a AP	179	riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid,
	180	value << 32 \| (timecmp_lo & 0xFFFFFFFF),
	181	mtimer->timebase_freq);
1c77c410	182	} else {
b8fb878a AP	183	qemu_log_mask(LOG_UNIMP,
	184	"aclint-mtimer: invalid timecmp write: %08x",
	185	(uint32_t)addr);
1c77c410 MC	186	}
1c77c410 MC	187	return;
b8fb878a	188	} else if (addr == mtimer->time_base) {
1c77c410	189	/* time_lo */
b8fb878a AP	190	qemu_log_mask(LOG_UNIMP,
b8fb878a AP	191	"aclint-mtimer: time_lo write not implemented");
1c77c410	192	return;
b8fb878a	193	} else if (addr == mtimer->time_base + 4) {
1c77c410	194	/* time_hi */
b8fb878a AP	195	qemu_log_mask(LOG_UNIMP,
b8fb878a AP	196	"aclint-mtimer: time_hi write not implemented");
1c77c410 MC	197	return;
	198	}
	199
b8fb878a AP	200	qemu_log_mask(LOG_UNIMP,
b8fb878a AP	201	"aclint-mtimer: invalid write: %08x", (uint32_t)addr);
1c77c410 MC	202	}
1c77c410 MC	203
b8fb878a AP	204	static const MemoryRegionOps riscv_aclint_mtimer_ops = {
	205	.read = riscv_aclint_mtimer_read,
	206	.write = riscv_aclint_mtimer_write,
1c77c410 MC	207	.endianness = DEVICE_LITTLE_ENDIAN,
	208	.valid = {
	209	.min_access_size = 4,
70b78d4e	210	.max_access_size = 8
231a90c0 FC	211	},
	212	.impl = {
	213	.min_access_size = 4,
	214	.max_access_size = 8,
1c77c410 MC	215	}
	216	};
	217
b8fb878a AP	218	static Property riscv_aclint_mtimer_properties[] = {
	219	DEFINE_PROP_UINT32("hartid-base", RISCVAclintMTimerState,
	220	hartid_base, 0),
	221	DEFINE_PROP_UINT32("num-harts", RISCVAclintMTimerState, num_harts, 1),
	222	DEFINE_PROP_UINT32("timecmp-base", RISCVAclintMTimerState,
	223	timecmp_base, RISCV_ACLINT_DEFAULT_MTIMECMP),
	224	DEFINE_PROP_UINT32("time-base", RISCVAclintMTimerState,
	225	time_base, RISCV_ACLINT_DEFAULT_MTIME),
	226	DEFINE_PROP_UINT32("aperture-size", RISCVAclintMTimerState,
	227	aperture_size, RISCV_ACLINT_DEFAULT_MTIMER_SIZE),
	228	DEFINE_PROP_UINT32("timebase-freq", RISCVAclintMTimerState,
	229	timebase_freq, 0),
1c77c410 MC	230	DEFINE_PROP_END_OF_LIST(),
	231	};
	232
b8fb878a	233	static void riscv_aclint_mtimer_realize(DeviceState dev, Error *errp)
1c77c410	234	{
b8fb878a AP	235	RISCVAclintMTimerState *s = RISCV_ACLINT_MTIMER(dev);
	236	int i;
	237
	238	memory_region_init_io(&s->mmio, OBJECT(dev), &riscv_aclint_mtimer_ops,
	239	s, TYPE_RISCV_ACLINT_MTIMER, s->aperture_size);
1c77c410	240	sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
a714b8aa	241
b21e2380	242	s->timer_irqs = g_new(qemu_irq, s->num_harts);
a714b8aa AF	243	qdev_init_gpio_out(dev, s->timer_irqs, s->num_harts);
a714b8aa AF	244
b8fb878a AP	245	/* Claim timer interrupt bits */
	246	for (i = 0; i < s->num_harts; i++) {
	247	RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(s->hartid_base + i));
	248	if (riscv_cpu_claim_interrupts(cpu, MIP_MTIP) < 0) {
	249	error_report("MTIP already claimed");
	250	exit(1);
	251	}
	252	}
1c77c410 MC	253	}
1c77c410 MC	254
b8fb878a	255	static void riscv_aclint_mtimer_class_init(ObjectClass klass, void data)
1c77c410 MC	256	{
1c77c410 MC	257	DeviceClass *dc = DEVICE_CLASS(klass);
b8fb878a AP	258	dc->realize = riscv_aclint_mtimer_realize;
b8fb878a AP	259	device_class_set_props(dc, riscv_aclint_mtimer_properties);
1c77c410 MC	260	}
1c77c410 MC	261
b8fb878a AP	262	static const TypeInfo riscv_aclint_mtimer_info = {
b8fb878a AP	263	.name = TYPE_RISCV_ACLINT_MTIMER,
1c77c410	264	.parent = TYPE_SYS_BUS_DEVICE,
b8fb878a AP	265	.instance_size = sizeof(RISCVAclintMTimerState),
b8fb878a AP	266	.class_init = riscv_aclint_mtimer_class_init,
1c77c410 MC	267	};
1c77c410 MC	268
1c77c410	269	/*
b8fb878a	270	* Create ACLINT MTIMER device.
1c77c410	271	*/
b8fb878a AP	272	DeviceState *riscv_aclint_mtimer_create(hwaddr addr, hwaddr size,
b8fb878a AP	273	uint32_t hartid_base, uint32_t num_harts,
a47ef6e9 BM	274	uint32_t timecmp_base, uint32_t time_base, uint32_t timebase_freq,
a47ef6e9 BM	275	bool provide_rdtime)
1c77c410 MC	276	{
1c77c410 MC	277	int i;
b8fb878a AP	278	DeviceState *dev = qdev_new(TYPE_RISCV_ACLINT_MTIMER);
	279
	280	assert(num_harts <= RISCV_ACLINT_MAX_HARTS);
	281	assert(!(addr & 0x7));
	282	assert(!(timecmp_base & 0x7));
	283	assert(!(time_base & 0x7));
a714b8aa	284
a714b8aa AF	285	qdev_prop_set_uint32(dev, "hartid-base", hartid_base);
a714b8aa AF	286	qdev_prop_set_uint32(dev, "num-harts", num_harts);
a714b8aa AF	287	qdev_prop_set_uint32(dev, "timecmp-base", timecmp_base);
	288	qdev_prop_set_uint32(dev, "time-base", time_base);
	289	qdev_prop_set_uint32(dev, "aperture-size", size);
	290	qdev_prop_set_uint32(dev, "timebase-freq", timebase_freq);
	291	sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
	292	sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
	293
1c77c410	294	for (i = 0; i < num_harts; i++) {
3bf03f08	295	CPUState *cpu = qemu_get_cpu(hartid_base + i);
a714b8aa	296	RISCVCPU *rvcpu = RISCV_CPU(cpu);
1c77c410	297	CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
b8fb878a	298	riscv_aclint_mtimer_callback *cb =
b21e2380	299	g_new0(riscv_aclint_mtimer_callback, 1);
a714b8aa	300
1c77c410	301	if (!env) {
a714b8aa	302	g_free(cb);
1c77c410 MC	303	continue;
1c77c410 MC	304	}
5f3616cc	305	if (provide_rdtime) {
a47ef6e9	306	riscv_cpu_set_rdtime_fn(env, cpu_riscv_read_rtc, timebase_freq);
5f3616cc	307	}
a714b8aa	308
b8fb878a	309	cb->s = RISCV_ACLINT_MTIMER(dev);
a714b8aa	310	cb->num = i;
1c77c410	311	env->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
b8fb878a	312	&riscv_aclint_mtimer_cb, cb);
1c77c410	313	env->timecmp = 0;
a714b8aa AF	314
	315	qdev_connect_gpio_out(dev, i,
	316	qdev_get_gpio_in(DEVICE(rvcpu), IRQ_M_TIMER));
1c77c410 MC	317	}
1c77c410 MC	318
1c77c410 MC	319	return dev;
1c77c410 MC	320	}
b8fb878a AP	321
	322	/* CPU read [M\|S]SWI register */
	323	static uint64_t riscv_aclint_swi_read(void *opaque, hwaddr addr,
	324	unsigned size)
	325	{
	326	RISCVAclintSwiState *swi = opaque;
	327
	328	if (addr < (swi->num_harts << 2)) {
	329	size_t hartid = swi->hartid_base + (addr >> 2);
	330	CPUState *cpu = qemu_get_cpu(hartid);
	331	CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
	332	if (!env) {
	333	qemu_log_mask(LOG_GUEST_ERROR,
	334	"aclint-swi: invalid hartid: %zu", hartid);
	335	} else if ((addr & 0x3) == 0) {
	336	return (swi->sswi) ? 0 : ((env->mip & MIP_MSIP) > 0);
	337	}
	338	}
	339
	340	qemu_log_mask(LOG_UNIMP,
	341	"aclint-swi: invalid read: %08x", (uint32_t)addr);
	342	return 0;
	343	}
	344
	345	/* CPU write [M\|S]SWI register */
	346	static void riscv_aclint_swi_write(void *opaque, hwaddr addr, uint64_t value,
	347	unsigned size)
	348	{
	349	RISCVAclintSwiState *swi = opaque;
	350
	351	if (addr < (swi->num_harts << 2)) {
	352	size_t hartid = swi->hartid_base + (addr >> 2);
	353	CPUState *cpu = qemu_get_cpu(hartid);
	354	CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
	355	if (!env) {
	356	qemu_log_mask(LOG_GUEST_ERROR,
	357	"aclint-swi: invalid hartid: %zu", hartid);
	358	} else if ((addr & 0x3) == 0) {
	359	if (value & 0x1) {
	360	qemu_irq_raise(swi->soft_irqs[hartid - swi->hartid_base]);
	361	} else {
	362	if (!swi->sswi) {
	363	qemu_irq_lower(swi->soft_irqs[hartid - swi->hartid_base]);
	364	}
	365	}
	366	return;
	367	}
	368	}
	369
	370	qemu_log_mask(LOG_UNIMP,
	371	"aclint-swi: invalid write: %08x", (uint32_t)addr);
	372	}
	373
	374	static const MemoryRegionOps riscv_aclint_swi_ops = {
	375	.read = riscv_aclint_swi_read,
	376	.write = riscv_aclint_swi_write,
	377	.endianness = DEVICE_LITTLE_ENDIAN,
	378	.valid = {
	379	.min_access_size = 4,
	380	.max_access_size = 4
	381	}
	382	};
	383
	384	static Property riscv_aclint_swi_properties[] = {
385	DEFINE_PROP_UINT32("hartid-base", RISCVAclintSwiState, hartid_base, 0),
386	DEFINE_PROP_UINT32("num-harts", RISCVAclintSwiState, num_harts, 1),
387	DEFINE_PROP_UINT32("sswi", RISCVAclintSwiState, sswi, false),
388	DEFINE_PROP_END_OF_LIST(),
389	};
390
391	static void riscv_aclint_swi_realize(DeviceState dev, Error *errp)
392	{
393	RISCVAclintSwiState *swi = RISCV_ACLINT_SWI(dev);
394	int i;
395
396	memory_region_init_io(&swi->mmio, OBJECT(dev), &riscv_aclint_swi_ops, swi,
397	TYPE_RISCV_ACLINT_SWI, RISCV_ACLINT_SWI_SIZE);
398	sysbus_init_mmio(SYS_BUS_DEVICE(dev), &swi->mmio);
399
b21e2380	400	swi->soft_irqs = g_new(qemu_irq, swi->num_harts);
b8fb878a AP	401	qdev_init_gpio_out(dev, swi->soft_irqs, swi->num_harts);
	402
	403	/* Claim software interrupt bits */
	404	for (i = 0; i < swi->num_harts; i++) {
	405	RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(swi->hartid_base + i));
	406	/* We don't claim mip.SSIP because it is writeable by software */
	407	if (riscv_cpu_claim_interrupts(cpu, swi->sswi ? 0 : MIP_MSIP) < 0) {
	408	error_report("MSIP already claimed");
	409	exit(1);
	410	}
	411	}
	412	}
	413
	414	static void riscv_aclint_swi_class_init(ObjectClass klass, void data)
	415	{
	416	DeviceClass *dc = DEVICE_CLASS(klass);
	417	dc->realize = riscv_aclint_swi_realize;
	418	device_class_set_props(dc, riscv_aclint_swi_properties);
	419	}
	420
	421	static const TypeInfo riscv_aclint_swi_info = {
	422	.name = TYPE_RISCV_ACLINT_SWI,
	423	.parent = TYPE_SYS_BUS_DEVICE,
	424	.instance_size = sizeof(RISCVAclintSwiState),
	425	.class_init = riscv_aclint_swi_class_init,
	426	};
	427
	428	/*
	429	* Create ACLINT [M\|S]SWI device.
	430	*/
	431	DeviceState *riscv_aclint_swi_create(hwaddr addr, uint32_t hartid_base,
	432	uint32_t num_harts, bool sswi)
	433	{
	434	int i;
	435	DeviceState *dev = qdev_new(TYPE_RISCV_ACLINT_SWI);
	436
	437	assert(num_harts <= RISCV_ACLINT_MAX_HARTS);
	438	assert(!(addr & 0x3));
	439
	440	qdev_prop_set_uint32(dev, "hartid-base", hartid_base);
	441	qdev_prop_set_uint32(dev, "num-harts", num_harts);
	442	qdev_prop_set_uint32(dev, "sswi", sswi ? true : false);
	443	sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
	444	sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
	445
	446	for (i = 0; i < num_harts; i++) {
	447	CPUState *cpu = qemu_get_cpu(hartid_base + i);
	448	RISCVCPU *rvcpu = RISCV_CPU(cpu);
	449
	450	qdev_connect_gpio_out(dev, i,
	451	qdev_get_gpio_in(DEVICE(rvcpu),
	452	(sswi) ? IRQ_S_SOFT : IRQ_M_SOFT));
	453	}
	454
	455	return dev;
	456	}
	457
	458	static void riscv_aclint_register_types(void)
	459	{
	460	type_register_static(&riscv_aclint_mtimer_info);
	461	type_register_static(&riscv_aclint_swi_info);
	462	}
	463
	464	type_init(riscv_aclint_register_types)