[mirror_qemu.git] / hw / intc / riscv_aclint.c

/*
 * RISC-V ACLINT (Advanced Core Local Interruptor)
 * URL: https://github.com/riscv/riscv-aclint
 *
 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
 * Copyright (c) 2017 SiFive, Inc.
 * Copyright (c) 2021 Western Digital Corporation or its affiliates.
 *
 * This provides real-time clock, timer and interprocessor interrupts.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2 or later, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "qemu/log.h"
#include "qemu/module.h"
#include "hw/sysbus.h"
#include "target/riscv/cpu.h"
#include "hw/qdev-properties.h"
#include "hw/intc/riscv_aclint.h"
#include "qemu/timer.h"
#include "hw/irq.h"

typedef struct riscv_aclint_mtimer_callback {
    RISCVAclintMTimerState *s;
    int num;
} riscv_aclint_mtimer_callback;

static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq)
{
    return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
        timebase_freq, NANOSECONDS_PER_SECOND);
}

/*
 * Called when timecmp is written to update the QEMU timer or immediately
 * trigger timer interrupt if mtimecmp <= current timer value.
 */
static void riscv_aclint_mtimer_write_timecmp(RISCVAclintMTimerState *mtimer,
                                              RISCVCPU *cpu,
                                              int hartid,
                                              uint64_t value,
                                              uint32_t timebase_freq)
{
    uint64_t next;
    uint64_t diff;

    uint64_t rtc_r = cpu_riscv_read_rtc(timebase_freq);

    cpu->env.timecmp = value;
    if (cpu->env.timecmp <= rtc_r) {
        /*
         * If we're setting an MTIMECMP value in the "past",
         * immediately raise the timer interrupt
         */
        qemu_irq_raise(mtimer->timer_irqs[hartid - mtimer->hartid_base]);
        return;
    }

    /* otherwise, set up the future timer interrupt */
    qemu_irq_lower(mtimer->timer_irqs[hartid - mtimer->hartid_base]);
    diff = cpu->env.timecmp - rtc_r;
    /* back to ns (note args switched in muldiv64) */
    uint64_t ns_diff = muldiv64(diff, NANOSECONDS_PER_SECOND, timebase_freq);

    /*
     * check if ns_diff overflowed and check if the addition would potentially
     * overflow
     */
    if ((NANOSECONDS_PER_SECOND > timebase_freq && ns_diff < diff) ||
        ns_diff > INT64_MAX) {
        next = INT64_MAX;
    } else {
        /*
         * as it is very unlikely qemu_clock_get_ns will return a value
         * greater than INT64_MAX, no additional check is needed for an
         * unsigned integer overflow.
         */
        next = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + ns_diff;
        /*
         * if ns_diff is INT64_MAX next may still be outside the range
         * of a signed integer.
         */
        next = MIN(next, INT64_MAX);
    }

    timer_mod(cpu->env.timer, next);
}

/*
 * Callback used when the timer set using timer_mod expires.
 * Should raise the timer interrupt line
 */
static void riscv_aclint_mtimer_cb(void *opaque)
{
    riscv_aclint_mtimer_callback *state = opaque;

    qemu_irq_raise(state->s->timer_irqs[state->num]);
}

/* CPU read MTIMER register */
static uint64_t riscv_aclint_mtimer_read(void *opaque, hwaddr addr,
    unsigned size)
{
    RISCVAclintMTimerState *mtimer = opaque;

    if (addr >= mtimer->timecmp_base &&
        addr < (mtimer->timecmp_base + (mtimer->num_harts << 3))) {
        size_t hartid = mtimer->hartid_base +
                        ((addr - mtimer->timecmp_base) >> 3);
        CPUState *cpu = qemu_get_cpu(hartid);
        CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
        if (!env) {
            qemu_log_mask(LOG_GUEST_ERROR,
                          "aclint-mtimer: invalid hartid: %zu", hartid);
        } else if ((addr & 0x7) == 0) {
            /* timecmp_lo for RV32/RV64 or timecmp for RV64 */
            uint64_t timecmp = env->timecmp;
            return (size == 4) ? (timecmp & 0xFFFFFFFF) : timecmp;
        } else if ((addr & 0x7) == 4) {
            /* timecmp_hi */
            uint64_t timecmp = env->timecmp;
            return (timecmp >> 32) & 0xFFFFFFFF;
        } else {
            qemu_log_mask(LOG_UNIMP,
                          "aclint-mtimer: invalid read: %08x", (uint32_t)addr);
            return 0;
        }
    } else if (addr == mtimer->time_base) {
        /* time_lo for RV32/RV64 or timecmp for RV64 */
        uint64_t rtc = cpu_riscv_read_rtc(mtimer->timebase_freq);
        return (size == 4) ? (rtc & 0xFFFFFFFF) : rtc;
    } else if (addr == mtimer->time_base + 4) {
        /* time_hi */
        return (cpu_riscv_read_rtc(mtimer->timebase_freq) >> 32) & 0xFFFFFFFF;
    }

    qemu_log_mask(LOG_UNIMP,
                  "aclint-mtimer: invalid read: %08x", (uint32_t)addr);
    return 0;
}

/* CPU write MTIMER register */
static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr,
    uint64_t value, unsigned size)
{
    RISCVAclintMTimerState *mtimer = opaque;

    if (addr >= mtimer->timecmp_base &&
        addr < (mtimer->timecmp_base + (mtimer->num_harts << 3))) {
        size_t hartid = mtimer->hartid_base +
                        ((addr - mtimer->timecmp_base) >> 3);
        CPUState *cpu = qemu_get_cpu(hartid);
        CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
        if (!env) {
            qemu_log_mask(LOG_GUEST_ERROR,
                          "aclint-mtimer: invalid hartid: %zu", hartid);
        } else if ((addr & 0x7) == 0) {
            if (size == 4) {
                /* timecmp_lo for RV32/RV64 */
                uint64_t timecmp_hi = env->timecmp >> 32;
                riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid,
                    timecmp_hi << 32 | (value & 0xFFFFFFFF),
                    mtimer->timebase_freq);
            } else {
                /* timecmp for RV64 */
                riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid,
                                                  value, mtimer->timebase_freq);
            }
        } else if ((addr & 0x7) == 4) {
            if (size == 4) {
                /* timecmp_hi for RV32/RV64 */
                uint64_t timecmp_lo = env->timecmp;
                riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid,
                    value << 32 | (timecmp_lo & 0xFFFFFFFF),
                    mtimer->timebase_freq);
            } else {
                qemu_log_mask(LOG_GUEST_ERROR,
                              "aclint-mtimer: invalid timecmp_hi write: %08x",
                              (uint32_t)addr);
            }
        } else {
            qemu_log_mask(LOG_UNIMP,
                          "aclint-mtimer: invalid timecmp write: %08x",
                          (uint32_t)addr);
        }
        return;
    } else if (addr == mtimer->time_base) {
        /* time_lo */
        qemu_log_mask(LOG_UNIMP,
                      "aclint-mtimer: time_lo write not implemented");
        return;
    } else if (addr == mtimer->time_base + 4) {
        /* time_hi */
        qemu_log_mask(LOG_UNIMP,
                      "aclint-mtimer: time_hi write not implemented");
        return;
    }

    qemu_log_mask(LOG_UNIMP,
                  "aclint-mtimer: invalid write: %08x", (uint32_t)addr);
}

static const MemoryRegionOps riscv_aclint_mtimer_ops = {
    .read = riscv_aclint_mtimer_read,
    .write = riscv_aclint_mtimer_write,
    .endianness = DEVICE_LITTLE_ENDIAN,
    .valid = {
        .min_access_size = 4,
        .max_access_size = 8
    },
    .impl = {
        .min_access_size = 4,
        .max_access_size = 8,
    }
};

static Property riscv_aclint_mtimer_properties[] = {
    DEFINE_PROP_UINT32("hartid-base", RISCVAclintMTimerState,
        hartid_base, 0),
    DEFINE_PROP_UINT32("num-harts", RISCVAclintMTimerState, num_harts, 1),
    DEFINE_PROP_UINT32("timecmp-base", RISCVAclintMTimerState,
        timecmp_base, RISCV_ACLINT_DEFAULT_MTIMECMP),
    DEFINE_PROP_UINT32("time-base", RISCVAclintMTimerState,
        time_base, RISCV_ACLINT_DEFAULT_MTIME),
    DEFINE_PROP_UINT32("aperture-size", RISCVAclintMTimerState,
        aperture_size, RISCV_ACLINT_DEFAULT_MTIMER_SIZE),
    DEFINE_PROP_UINT32("timebase-freq", RISCVAclintMTimerState,
        timebase_freq, 0),
    DEFINE_PROP_END_OF_LIST(),
};

static void riscv_aclint_mtimer_realize(DeviceState *dev, Error **errp)
{
    RISCVAclintMTimerState *s = RISCV_ACLINT_MTIMER(dev);
    int i;

    memory_region_init_io(&s->mmio, OBJECT(dev), &riscv_aclint_mtimer_ops,
                          s, TYPE_RISCV_ACLINT_MTIMER, s->aperture_size);
    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);

    s->timer_irqs = g_new(qemu_irq, s->num_harts);
    qdev_init_gpio_out(dev, s->timer_irqs, s->num_harts);

    /* Claim timer interrupt bits */
    for (i = 0; i < s->num_harts; i++) {
        RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(s->hartid_base + i));
        if (riscv_cpu_claim_interrupts(cpu, MIP_MTIP) < 0) {
            error_report("MTIP already claimed");
            exit(1);
        }
    }
}

static void riscv_aclint_mtimer_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    dc->realize = riscv_aclint_mtimer_realize;
    device_class_set_props(dc, riscv_aclint_mtimer_properties);
}

static const TypeInfo riscv_aclint_mtimer_info = {
    .name          = TYPE_RISCV_ACLINT_MTIMER,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(RISCVAclintMTimerState),
    .class_init    = riscv_aclint_mtimer_class_init,
};

/*
 * Create ACLINT MTIMER device.
 */
DeviceState *riscv_aclint_mtimer_create(hwaddr addr, hwaddr size,
    uint32_t hartid_base, uint32_t num_harts,
    uint32_t timecmp_base, uint32_t time_base, uint32_t timebase_freq,
    bool provide_rdtime)
{
    int i;
    DeviceState *dev = qdev_new(TYPE_RISCV_ACLINT_MTIMER);

    assert(num_harts <= RISCV_ACLINT_MAX_HARTS);
    assert(!(addr & 0x7));
    assert(!(timecmp_base & 0x7));
    assert(!(time_base & 0x7));

    qdev_prop_set_uint32(dev, "hartid-base", hartid_base);
    qdev_prop_set_uint32(dev, "num-harts", num_harts);
    qdev_prop_set_uint32(dev, "timecmp-base", timecmp_base);
    qdev_prop_set_uint32(dev, "time-base", time_base);
    qdev_prop_set_uint32(dev, "aperture-size", size);
    qdev_prop_set_uint32(dev, "timebase-freq", timebase_freq);
    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);

    for (i = 0; i < num_harts; i++) {
        CPUState *cpu = qemu_get_cpu(hartid_base + i);
        RISCVCPU *rvcpu = RISCV_CPU(cpu);
        CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
        riscv_aclint_mtimer_callback *cb =
            g_new0(riscv_aclint_mtimer_callback, 1);

        if (!env) {
            g_free(cb);
            continue;
        }
        if (provide_rdtime) {
            riscv_cpu_set_rdtime_fn(env, cpu_riscv_read_rtc, timebase_freq);
        }

        cb->s = RISCV_ACLINT_MTIMER(dev);
        cb->num = i;
        env->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
                                  &riscv_aclint_mtimer_cb, cb);
        env->timecmp = 0;

        qdev_connect_gpio_out(dev, i,
                              qdev_get_gpio_in(DEVICE(rvcpu), IRQ_M_TIMER));
    }

    return dev;
}

/* CPU read [M|S]SWI register */
static uint64_t riscv_aclint_swi_read(void *opaque, hwaddr addr,
    unsigned size)
{
    RISCVAclintSwiState *swi = opaque;

    if (addr < (swi->num_harts << 2)) {
        size_t hartid = swi->hartid_base + (addr >> 2);
        CPUState *cpu = qemu_get_cpu(hartid);
        CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
        if (!env) {
            qemu_log_mask(LOG_GUEST_ERROR,
                          "aclint-swi: invalid hartid: %zu", hartid);
        } else if ((addr & 0x3) == 0) {
            return (swi->sswi) ? 0 : ((env->mip & MIP_MSIP) > 0);
        }
    }

    qemu_log_mask(LOG_UNIMP,
                  "aclint-swi: invalid read: %08x", (uint32_t)addr);
    return 0;
}

/* CPU write [M|S]SWI register */
static void riscv_aclint_swi_write(void *opaque, hwaddr addr, uint64_t value,
        unsigned size)
{
    RISCVAclintSwiState *swi = opaque;

    if (addr < (swi->num_harts << 2)) {
        size_t hartid = swi->hartid_base + (addr >> 2);
        CPUState *cpu = qemu_get_cpu(hartid);
        CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
        if (!env) {
            qemu_log_mask(LOG_GUEST_ERROR,
                          "aclint-swi: invalid hartid: %zu", hartid);
        } else if ((addr & 0x3) == 0) {
            if (value & 0x1) {
                qemu_irq_raise(swi->soft_irqs[hartid - swi->hartid_base]);
            } else {
                if (!swi->sswi) {
                    qemu_irq_lower(swi->soft_irqs[hartid - swi->hartid_base]);
                }
            }
            return;
        }
    }

    qemu_log_mask(LOG_UNIMP,
                  "aclint-swi: invalid write: %08x", (uint32_t)addr);
}

static const MemoryRegionOps riscv_aclint_swi_ops = {
    .read = riscv_aclint_swi_read,
    .write = riscv_aclint_swi_write,
    .endianness = DEVICE_LITTLE_ENDIAN,
    .valid = {
        .min_access_size = 4,
        .max_access_size = 4
    }
};

static Property riscv_aclint_swi_properties[] = {
    DEFINE_PROP_UINT32("hartid-base", RISCVAclintSwiState, hartid_base, 0),
    DEFINE_PROP_UINT32("num-harts", RISCVAclintSwiState, num_harts, 1),
    DEFINE_PROP_UINT32("sswi", RISCVAclintSwiState, sswi, false),
    DEFINE_PROP_END_OF_LIST(),
};

static void riscv_aclint_swi_realize(DeviceState *dev, Error **errp)
{
    RISCVAclintSwiState *swi = RISCV_ACLINT_SWI(dev);
    int i;

    memory_region_init_io(&swi->mmio, OBJECT(dev), &riscv_aclint_swi_ops, swi,
                          TYPE_RISCV_ACLINT_SWI, RISCV_ACLINT_SWI_SIZE);
    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &swi->mmio);

    swi->soft_irqs = g_new(qemu_irq, swi->num_harts);
    qdev_init_gpio_out(dev, swi->soft_irqs, swi->num_harts);

    /* Claim software interrupt bits */
    for (i = 0; i < swi->num_harts; i++) {
        RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(swi->hartid_base + i));
        /* We don't claim mip.SSIP because it is writeable by software */
        if (riscv_cpu_claim_interrupts(cpu, swi->sswi ? 0 : MIP_MSIP) < 0) {
            error_report("MSIP already claimed");
            exit(1);
        }
    }
}

static void riscv_aclint_swi_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    dc->realize = riscv_aclint_swi_realize;
    device_class_set_props(dc, riscv_aclint_swi_properties);
}

static const TypeInfo riscv_aclint_swi_info = {
    .name          = TYPE_RISCV_ACLINT_SWI,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(RISCVAclintSwiState),
    .class_init    = riscv_aclint_swi_class_init,
};

/*
 * Create ACLINT [M|S]SWI device.
 */
DeviceState *riscv_aclint_swi_create(hwaddr addr, uint32_t hartid_base,
    uint32_t num_harts, bool sswi)
{
    int i;
    DeviceState *dev = qdev_new(TYPE_RISCV_ACLINT_SWI);

    assert(num_harts <= RISCV_ACLINT_MAX_HARTS);
    assert(!(addr & 0x3));

    qdev_prop_set_uint32(dev, "hartid-base", hartid_base);
    qdev_prop_set_uint32(dev, "num-harts", num_harts);
    qdev_prop_set_uint32(dev, "sswi", sswi ? true : false);
    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);

    for (i = 0; i < num_harts; i++) {
        CPUState *cpu = qemu_get_cpu(hartid_base + i);
        RISCVCPU *rvcpu = RISCV_CPU(cpu);

        qdev_connect_gpio_out(dev, i,
                              qdev_get_gpio_in(DEVICE(rvcpu),
                                  (sswi) ? IRQ_S_SOFT : IRQ_M_SOFT));
    }

    return dev;
}

static void riscv_aclint_register_types(void)
{
    type_register_static(&riscv_aclint_mtimer_info);
    type_register_static(&riscv_aclint_swi_info);
}

type_init(riscv_aclint_register_types)
Commit	Line	Data
1c77c410	1	/*
b8fb878a AP	2	* RISC-V ACLINT (Advanced Core Local Interruptor)
b8fb878a AP	3	* URL: https://github.com/riscv/riscv-aclint
1c77c410 MC	4	*
	5	* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
	6	* Copyright (c) 2017 SiFive, Inc.
b8fb878a	7	* Copyright (c) 2021 Western Digital Corporation or its affiliates.
1c77c410 MC	8	*
	9	* This provides real-time clock, timer and interprocessor interrupts.
	10	*
	11	* This program is free software; you can redistribute it and/or modify it
	12	* under the terms and conditions of the GNU General Public License,
	13	* version 2 or later, as published by the Free Software Foundation.
	14	*
	15	* This program is distributed in the hope it will be useful, but WITHOUT
	16	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	17	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	18	* more details.
	19	*
	20	* You should have received a copy of the GNU General Public License along with
	21	* this program. If not, see <http://www.gnu.org/licenses/>.
	22	*/
	23
	24	#include "qemu/osdep.h"
3e80f690	25	#include "qapi/error.h"
1c77c410	26	#include "qemu/error-report.h"
b8fb878a	27	#include "qemu/log.h"
0b8fa32f	28	#include "qemu/module.h"
1c77c410 MC	29	#include "hw/sysbus.h"
1c77c410 MC	30	#include "target/riscv/cpu.h"
a27bd6c7	31	#include "hw/qdev-properties.h"
cc63a182	32	#include "hw/intc/riscv_aclint.h"
1c77c410	33	#include "qemu/timer.h"
a714b8aa AF	34	#include "hw/irq.h"
a714b8aa AF	35
b8fb878a AP	36	typedef struct riscv_aclint_mtimer_callback {
b8fb878a AP	37	RISCVAclintMTimerState *s;
a714b8aa	38	int num;
b8fb878a	39	} riscv_aclint_mtimer_callback;
1c77c410	40
a47ef6e9	41	static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq)
1c77c410	42	{
2a8756ed	43	return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
a47ef6e9	44	timebase_freq, NANOSECONDS_PER_SECOND);
1c77c410 MC	45	}
	46
	47	/*
	48	* Called when timecmp is written to update the QEMU timer or immediately
	49	* trigger timer interrupt if mtimecmp <= current timer value.
	50	*/
b8fb878a AP	51	static void riscv_aclint_mtimer_write_timecmp(RISCVAclintMTimerState *mtimer,
	52	RISCVCPU *cpu,
	53	int hartid,
	54	uint64_t value,
	55	uint32_t timebase_freq)
1c77c410 MC	56	{
	57	uint64_t next;
	58	uint64_t diff;
	59
a47ef6e9	60	uint64_t rtc_r = cpu_riscv_read_rtc(timebase_freq);
1c77c410 MC	61
	62	cpu->env.timecmp = value;
	63	if (cpu->env.timecmp <= rtc_r) {
b8fb878a AP	64	/*
	65	* If we're setting an MTIMECMP value in the "past",
	66	* immediately raise the timer interrupt
	67	*/
	68	qemu_irq_raise(mtimer->timer_irqs[hartid - mtimer->hartid_base]);
1c77c410 MC	69	return;
	70	}
	71
	72	/* otherwise, set up the future timer interrupt */
b8fb878a	73	qemu_irq_lower(mtimer->timer_irqs[hartid - mtimer->hartid_base]);
1c77c410 MC	74	diff = cpu->env.timecmp - rtc_r;
1c77c410 MC	75	/* back to ns (note args switched in muldiv64) */
4dc06bb8 DH	76	uint64_t ns_diff = muldiv64(diff, NANOSECONDS_PER_SECOND, timebase_freq);
	77
	78	/*
	79	* check if ns_diff overflowed and check if the addition would potentially
	80	* overflow
	81	*/
	82	if ((NANOSECONDS_PER_SECOND > timebase_freq && ns_diff < diff) \|\|
	83	ns_diff > INT64_MAX) {
	84	next = INT64_MAX;
	85	} else {
	86	/*
	87	* as it is very unlikely qemu_clock_get_ns will return a value
	88	* greater than INT64_MAX, no additional check is needed for an
	89	* unsigned integer overflow.
	90	*/
	91	next = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + ns_diff;
	92	/*
	93	* if ns_diff is INT64_MAX next may still be outside the range
	94	* of a signed integer.
	95	*/
	96	next = MIN(next, INT64_MAX);
	97	}
	98
1c77c410 MC	99	timer_mod(cpu->env.timer, next);
	100	}
	101
	102	/*
	103	* Callback used when the timer set using timer_mod expires.
	104	* Should raise the timer interrupt line
	105	*/
b8fb878a	106	static void riscv_aclint_mtimer_cb(void *opaque)
1c77c410	107	{
b8fb878a	108	riscv_aclint_mtimer_callback *state = opaque;
a714b8aa AF	109
a714b8aa AF	110	qemu_irq_raise(state->s->timer_irqs[state->num]);
1c77c410 MC	111	}
1c77c410 MC	112
b8fb878a AP	113	/* CPU read MTIMER register */
	114	static uint64_t riscv_aclint_mtimer_read(void *opaque, hwaddr addr,
	115	unsigned size)
1c77c410	116	{
b8fb878a AP	117	RISCVAclintMTimerState *mtimer = opaque;
	118
	119	if (addr >= mtimer->timecmp_base &&
	120	addr < (mtimer->timecmp_base + (mtimer->num_harts << 3))) {
	121	size_t hartid = mtimer->hartid_base +
	122	((addr - mtimer->timecmp_base) >> 3);
1c77c410 MC	123	CPUState *cpu = qemu_get_cpu(hartid);
	124	CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
	125	if (!env) {
b8fb878a AP	126	qemu_log_mask(LOG_GUEST_ERROR,
b8fb878a AP	127	"aclint-mtimer: invalid hartid: %zu", hartid);
1c77c410	128	} else if ((addr & 0x7) == 0) {
d42df0ea	129	/* timecmp_lo for RV32/RV64 or timecmp for RV64 */
1c77c410	130	uint64_t timecmp = env->timecmp;
d42df0ea	131	return (size == 4) ? (timecmp & 0xFFFFFFFF) : timecmp;
1c77c410 MC	132	} else if ((addr & 0x7) == 4) {
	133	/* timecmp_hi */
	134	uint64_t timecmp = env->timecmp;
	135	return (timecmp >> 32) & 0xFFFFFFFF;
	136	} else {
b8fb878a AP	137	qemu_log_mask(LOG_UNIMP,
b8fb878a AP	138	"aclint-mtimer: invalid read: %08x", (uint32_t)addr);
1c77c410 MC	139	return 0;
1c77c410 MC	140	}
b8fb878a	141	} else if (addr == mtimer->time_base) {
d42df0ea FC	142	/* time_lo for RV32/RV64 or timecmp for RV64 */
	143	uint64_t rtc = cpu_riscv_read_rtc(mtimer->timebase_freq);
	144	return (size == 4) ? (rtc & 0xFFFFFFFF) : rtc;
b8fb878a	145	} else if (addr == mtimer->time_base + 4) {
1c77c410	146	/* time_hi */
b8fb878a	147	return (cpu_riscv_read_rtc(mtimer->timebase_freq) >> 32) & 0xFFFFFFFF;
1c77c410 MC	148	}
1c77c410 MC	149
b8fb878a AP	150	qemu_log_mask(LOG_UNIMP,
b8fb878a AP	151	"aclint-mtimer: invalid read: %08x", (uint32_t)addr);
1c77c410 MC	152	return 0;
	153	}
	154
b8fb878a AP	155	/* CPU write MTIMER register */
	156	static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr,
	157	uint64_t value, unsigned size)
1c77c410	158	{
b8fb878a	159	RISCVAclintMTimerState *mtimer = opaque;
1c77c410	160
b8fb878a AP	161	if (addr >= mtimer->timecmp_base &&
	162	addr < (mtimer->timecmp_base + (mtimer->num_harts << 3))) {
	163	size_t hartid = mtimer->hartid_base +
	164	((addr - mtimer->timecmp_base) >> 3);
1c77c410 MC	165	CPUState *cpu = qemu_get_cpu(hartid);
	166	CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
	167	if (!env) {
b8fb878a AP	168	qemu_log_mask(LOG_GUEST_ERROR,
b8fb878a AP	169	"aclint-mtimer: invalid hartid: %zu", hartid);
1c77c410	170	} else if ((addr & 0x7) == 0) {
d42df0ea FC	171	if (size == 4) {
	172	/* timecmp_lo for RV32/RV64 */
	173	uint64_t timecmp_hi = env->timecmp >> 32;
	174	riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid,
	175	timecmp_hi << 32 \| (value & 0xFFFFFFFF),
	176	mtimer->timebase_freq);
	177	} else {
	178	/* timecmp for RV64 */
	179	riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid,
	180	value, mtimer->timebase_freq);
	181	}
1c77c410	182	} else if ((addr & 0x7) == 4) {
d42df0ea FC	183	if (size == 4) {
	184	/* timecmp_hi for RV32/RV64 */
	185	uint64_t timecmp_lo = env->timecmp;
	186	riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid,
	187	value << 32 \| (timecmp_lo & 0xFFFFFFFF),
	188	mtimer->timebase_freq);
	189	} else {
	190	qemu_log_mask(LOG_GUEST_ERROR,
	191	"aclint-mtimer: invalid timecmp_hi write: %08x",
	192	(uint32_t)addr);
	193	}
1c77c410	194	} else {
b8fb878a AP	195	qemu_log_mask(LOG_UNIMP,
	196	"aclint-mtimer: invalid timecmp write: %08x",
	197	(uint32_t)addr);
1c77c410 MC	198	}
1c77c410 MC	199	return;
b8fb878a	200	} else if (addr == mtimer->time_base) {
1c77c410	201	/* time_lo */
b8fb878a AP	202	qemu_log_mask(LOG_UNIMP,
b8fb878a AP	203	"aclint-mtimer: time_lo write not implemented");
1c77c410	204	return;
b8fb878a	205	} else if (addr == mtimer->time_base + 4) {
1c77c410	206	/* time_hi */
b8fb878a AP	207	qemu_log_mask(LOG_UNIMP,
b8fb878a AP	208	"aclint-mtimer: time_hi write not implemented");
1c77c410 MC	209	return;
	210	}
	211
b8fb878a AP	212	qemu_log_mask(LOG_UNIMP,
b8fb878a AP	213	"aclint-mtimer: invalid write: %08x", (uint32_t)addr);
1c77c410 MC	214	}
1c77c410 MC	215
b8fb878a AP	216	static const MemoryRegionOps riscv_aclint_mtimer_ops = {
	217	.read = riscv_aclint_mtimer_read,
	218	.write = riscv_aclint_mtimer_write,
1c77c410 MC	219	.endianness = DEVICE_LITTLE_ENDIAN,
	220	.valid = {
	221	.min_access_size = 4,
70b78d4e	222	.max_access_size = 8
231a90c0 FC	223	},
	224	.impl = {
	225	.min_access_size = 4,
	226	.max_access_size = 8,
1c77c410 MC	227	}
	228	};
	229
b8fb878a AP	230	static Property riscv_aclint_mtimer_properties[] = {
	231	DEFINE_PROP_UINT32("hartid-base", RISCVAclintMTimerState,
	232	hartid_base, 0),
	233	DEFINE_PROP_UINT32("num-harts", RISCVAclintMTimerState, num_harts, 1),
	234	DEFINE_PROP_UINT32("timecmp-base", RISCVAclintMTimerState,
	235	timecmp_base, RISCV_ACLINT_DEFAULT_MTIMECMP),
	236	DEFINE_PROP_UINT32("time-base", RISCVAclintMTimerState,
	237	time_base, RISCV_ACLINT_DEFAULT_MTIME),
	238	DEFINE_PROP_UINT32("aperture-size", RISCVAclintMTimerState,
	239	aperture_size, RISCV_ACLINT_DEFAULT_MTIMER_SIZE),
	240	DEFINE_PROP_UINT32("timebase-freq", RISCVAclintMTimerState,
	241	timebase_freq, 0),
1c77c410 MC	242	DEFINE_PROP_END_OF_LIST(),
	243	};
	244
b8fb878a	245	static void riscv_aclint_mtimer_realize(DeviceState dev, Error *errp)
1c77c410	246	{
b8fb878a AP	247	RISCVAclintMTimerState *s = RISCV_ACLINT_MTIMER(dev);
	248	int i;
	249
	250	memory_region_init_io(&s->mmio, OBJECT(dev), &riscv_aclint_mtimer_ops,
	251	s, TYPE_RISCV_ACLINT_MTIMER, s->aperture_size);
1c77c410	252	sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
a714b8aa	253
b21e2380	254	s->timer_irqs = g_new(qemu_irq, s->num_harts);
a714b8aa AF	255	qdev_init_gpio_out(dev, s->timer_irqs, s->num_harts);
a714b8aa AF	256
b8fb878a AP	257	/* Claim timer interrupt bits */
	258	for (i = 0; i < s->num_harts; i++) {
	259	RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(s->hartid_base + i));
	260	if (riscv_cpu_claim_interrupts(cpu, MIP_MTIP) < 0) {
	261	error_report("MTIP already claimed");
	262	exit(1);
	263	}
	264	}
1c77c410 MC	265	}
1c77c410 MC	266
b8fb878a	267	static void riscv_aclint_mtimer_class_init(ObjectClass klass, void data)
1c77c410 MC	268	{
1c77c410 MC	269	DeviceClass *dc = DEVICE_CLASS(klass);
b8fb878a AP	270	dc->realize = riscv_aclint_mtimer_realize;
b8fb878a AP	271	device_class_set_props(dc, riscv_aclint_mtimer_properties);
1c77c410 MC	272	}
1c77c410 MC	273
b8fb878a AP	274	static const TypeInfo riscv_aclint_mtimer_info = {
b8fb878a AP	275	.name = TYPE_RISCV_ACLINT_MTIMER,
1c77c410	276	.parent = TYPE_SYS_BUS_DEVICE,
b8fb878a AP	277	.instance_size = sizeof(RISCVAclintMTimerState),
b8fb878a AP	278	.class_init = riscv_aclint_mtimer_class_init,
1c77c410 MC	279	};
1c77c410 MC	280
1c77c410	281	/*
b8fb878a	282	* Create ACLINT MTIMER device.
1c77c410	283	*/
b8fb878a AP	284	DeviceState *riscv_aclint_mtimer_create(hwaddr addr, hwaddr size,
b8fb878a AP	285	uint32_t hartid_base, uint32_t num_harts,
a47ef6e9 BM	286	uint32_t timecmp_base, uint32_t time_base, uint32_t timebase_freq,
a47ef6e9 BM	287	bool provide_rdtime)
1c77c410 MC	288	{
1c77c410 MC	289	int i;
b8fb878a AP	290	DeviceState *dev = qdev_new(TYPE_RISCV_ACLINT_MTIMER);
	291
	292	assert(num_harts <= RISCV_ACLINT_MAX_HARTS);
	293	assert(!(addr & 0x7));
	294	assert(!(timecmp_base & 0x7));
	295	assert(!(time_base & 0x7));
a714b8aa	296
a714b8aa AF	297	qdev_prop_set_uint32(dev, "hartid-base", hartid_base);
a714b8aa AF	298	qdev_prop_set_uint32(dev, "num-harts", num_harts);
a714b8aa AF	299	qdev_prop_set_uint32(dev, "timecmp-base", timecmp_base);
	300	qdev_prop_set_uint32(dev, "time-base", time_base);
	301	qdev_prop_set_uint32(dev, "aperture-size", size);
	302	qdev_prop_set_uint32(dev, "timebase-freq", timebase_freq);
	303	sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
	304	sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
	305
1c77c410	306	for (i = 0; i < num_harts; i++) {
3bf03f08	307	CPUState *cpu = qemu_get_cpu(hartid_base + i);
a714b8aa	308	RISCVCPU *rvcpu = RISCV_CPU(cpu);
1c77c410	309	CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
b8fb878a	310	riscv_aclint_mtimer_callback *cb =
b21e2380	311	g_new0(riscv_aclint_mtimer_callback, 1);
a714b8aa	312
1c77c410	313	if (!env) {
a714b8aa	314	g_free(cb);
1c77c410 MC	315	continue;
1c77c410 MC	316	}
5f3616cc	317	if (provide_rdtime) {
a47ef6e9	318	riscv_cpu_set_rdtime_fn(env, cpu_riscv_read_rtc, timebase_freq);
5f3616cc	319	}
a714b8aa	320
b8fb878a	321	cb->s = RISCV_ACLINT_MTIMER(dev);
a714b8aa	322	cb->num = i;
1c77c410	323	env->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
b8fb878a	324	&riscv_aclint_mtimer_cb, cb);
1c77c410	325	env->timecmp = 0;
a714b8aa AF	326
	327	qdev_connect_gpio_out(dev, i,
	328	qdev_get_gpio_in(DEVICE(rvcpu), IRQ_M_TIMER));
1c77c410 MC	329	}
1c77c410 MC	330
1c77c410 MC	331	return dev;
1c77c410 MC	332	}
b8fb878a AP	333
	334	/* CPU read [M\|S]SWI register */
	335	static uint64_t riscv_aclint_swi_read(void *opaque, hwaddr addr,
	336	unsigned size)
	337	{
	338	RISCVAclintSwiState *swi = opaque;
	339
	340	if (addr < (swi->num_harts << 2)) {
	341	size_t hartid = swi->hartid_base + (addr >> 2);
	342	CPUState *cpu = qemu_get_cpu(hartid);
	343	CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
	344	if (!env) {
	345	qemu_log_mask(LOG_GUEST_ERROR,
	346	"aclint-swi: invalid hartid: %zu", hartid);
	347	} else if ((addr & 0x3) == 0) {
	348	return (swi->sswi) ? 0 : ((env->mip & MIP_MSIP) > 0);
	349	}
	350	}
	351
	352	qemu_log_mask(LOG_UNIMP,
	353	"aclint-swi: invalid read: %08x", (uint32_t)addr);
	354	return 0;
	355	}
	356
	357	/* CPU write [M\|S]SWI register */
	358	static void riscv_aclint_swi_write(void *opaque, hwaddr addr, uint64_t value,
	359	unsigned size)
	360	{
	361	RISCVAclintSwiState *swi = opaque;
	362
	363	if (addr < (swi->num_harts << 2)) {
	364	size_t hartid = swi->hartid_base + (addr >> 2);
	365	CPUState *cpu = qemu_get_cpu(hartid);
	366	CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
	367	if (!env) {
	368	qemu_log_mask(LOG_GUEST_ERROR,
	369	"aclint-swi: invalid hartid: %zu", hartid);
	370	} else if ((addr & 0x3) == 0) {
	371	if (value & 0x1) {
	372	qemu_irq_raise(swi->soft_irqs[hartid - swi->hartid_base]);
	373	} else {
	374	if (!swi->sswi) {
	375	qemu_irq_lower(swi->soft_irqs[hartid - swi->hartid_base]);
	376	}
	377	}
	378	return;
	379	}
	380	}
	381
	382	qemu_log_mask(LOG_UNIMP,
	383	"aclint-swi: invalid write: %08x", (uint32_t)addr);
	384	}
	385
	386	static const MemoryRegionOps riscv_aclint_swi_ops = {
	387	.read = riscv_aclint_swi_read,
	388	.write = riscv_aclint_swi_write,
	389	.endianness = DEVICE_LITTLE_ENDIAN,
	390	.valid = {
	391	.min_access_size = 4,
	392	.max_access_size = 4
	393	}
	394	};
	395
	396	static Property riscv_aclint_swi_properties[] = {
397	DEFINE_PROP_UINT32("hartid-base", RISCVAclintSwiState, hartid_base, 0),
398	DEFINE_PROP_UINT32("num-harts", RISCVAclintSwiState, num_harts, 1),
399	DEFINE_PROP_UINT32("sswi", RISCVAclintSwiState, sswi, false),
400	DEFINE_PROP_END_OF_LIST(),
401	};
402
403	static void riscv_aclint_swi_realize(DeviceState dev, Error *errp)
404	{
405	RISCVAclintSwiState *swi = RISCV_ACLINT_SWI(dev);
406	int i;
407
408	memory_region_init_io(&swi->mmio, OBJECT(dev), &riscv_aclint_swi_ops, swi,
409	TYPE_RISCV_ACLINT_SWI, RISCV_ACLINT_SWI_SIZE);
410	sysbus_init_mmio(SYS_BUS_DEVICE(dev), &swi->mmio);
411
b21e2380	412	swi->soft_irqs = g_new(qemu_irq, swi->num_harts);
b8fb878a AP	413	qdev_init_gpio_out(dev, swi->soft_irqs, swi->num_harts);
	414
	415	/* Claim software interrupt bits */
	416	for (i = 0; i < swi->num_harts; i++) {
	417	RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(swi->hartid_base + i));
	418	/* We don't claim mip.SSIP because it is writeable by software */
	419	if (riscv_cpu_claim_interrupts(cpu, swi->sswi ? 0 : MIP_MSIP) < 0) {
	420	error_report("MSIP already claimed");
	421	exit(1);
	422	}
	423	}
	424	}
	425
	426	static void riscv_aclint_swi_class_init(ObjectClass klass, void data)
	427	{
	428	DeviceClass *dc = DEVICE_CLASS(klass);
	429	dc->realize = riscv_aclint_swi_realize;
	430	device_class_set_props(dc, riscv_aclint_swi_properties);
	431	}
	432
	433	static const TypeInfo riscv_aclint_swi_info = {
	434	.name = TYPE_RISCV_ACLINT_SWI,
	435	.parent = TYPE_SYS_BUS_DEVICE,
	436	.instance_size = sizeof(RISCVAclintSwiState),
	437	.class_init = riscv_aclint_swi_class_init,
	438	};
	439
	440	/*
	441	* Create ACLINT [M\|S]SWI device.
	442	*/
	443	DeviceState *riscv_aclint_swi_create(hwaddr addr, uint32_t hartid_base,
	444	uint32_t num_harts, bool sswi)
	445	{
	446	int i;
	447	DeviceState *dev = qdev_new(TYPE_RISCV_ACLINT_SWI);
	448
	449	assert(num_harts <= RISCV_ACLINT_MAX_HARTS);
	450	assert(!(addr & 0x3));
	451
	452	qdev_prop_set_uint32(dev, "hartid-base", hartid_base);
	453	qdev_prop_set_uint32(dev, "num-harts", num_harts);
	454	qdev_prop_set_uint32(dev, "sswi", sswi ? true : false);
	455	sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
	456	sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
	457
	458	for (i = 0; i < num_harts; i++) {
	459	CPUState *cpu = qemu_get_cpu(hartid_base + i);
	460	RISCVCPU *rvcpu = RISCV_CPU(cpu);
	461
	462	qdev_connect_gpio_out(dev, i,
	463	qdev_get_gpio_in(DEVICE(rvcpu),
	464	(sswi) ? IRQ_S_SOFT : IRQ_M_SOFT));
	465	}
	466
	467	return dev;
	468	}
	469
	470	static void riscv_aclint_register_types(void)
	471	{
	472	type_register_static(&riscv_aclint_mtimer_info);
	473	type_register_static(&riscv_aclint_swi_info);
	474	}
	475
	476	type_init(riscv_aclint_register_types)