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Commit | Line | Data |
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b5cec4c5 DG |
1 | /* |
2 | * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator | |
3 | * | |
4 | * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics | |
5 | * | |
6 | * Copyright (c) 2010,2011 David Gibson, IBM Corporation. | |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
9 | * of this software and associated documentation files (the "Software"), to deal | |
10 | * in the Software without restriction, including without limitation the rights | |
11 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
12 | * copies of the Software, and to permit persons to whom the Software is | |
13 | * furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice shall be included in | |
16 | * all copies or substantial portions of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
22 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
23 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
24 | * THE SOFTWARE. | |
25 | * | |
26 | */ | |
27 | ||
0d75590d | 28 | #include "qemu/osdep.h" |
da34e65c | 29 | #include "qapi/error.h" |
4771d756 PB |
30 | #include "qemu-common.h" |
31 | #include "cpu.h" | |
83c9f4ca | 32 | #include "hw/hw.h" |
500efa23 | 33 | #include "trace.h" |
5d87e4b7 | 34 | #include "qemu/timer.h" |
0d09e41a | 35 | #include "hw/ppc/xics.h" |
9ccff2a4 | 36 | #include "qemu/error-report.h" |
5a3d7b23 | 37 | #include "qapi/visitor.h" |
b1fc72f0 BH |
38 | #include "monitor/monitor.h" |
39 | #include "hw/intc/intc.h" | |
b5cec4c5 | 40 | |
b4f27d71 | 41 | void xics_cpu_destroy(XICSFabric *xi, PowerPCCPU *cpu) |
4a4b344c BR |
42 | { |
43 | CPUState *cs = CPU(cpu); | |
ad5d1add | 44 | ICPState *icp = ICP(cpu->intc); |
4a4b344c | 45 | |
8e4fba20 CLG |
46 | assert(icp); |
47 | assert(cs == icp->cs); | |
4a4b344c | 48 | |
8e4fba20 CLG |
49 | icp->output = NULL; |
50 | icp->cs = NULL; | |
4a4b344c BR |
51 | } |
52 | ||
ad5d1add | 53 | void xics_cpu_setup(XICSFabric *xi, PowerPCCPU *cpu, ICPState *icp) |
8ffe04ed AK |
54 | { |
55 | CPUState *cs = CPU(cpu); | |
56 | CPUPPCState *env = &cpu->env; | |
f0232434 | 57 | ICPStateClass *icpc; |
8ffe04ed | 58 | |
8e4fba20 | 59 | assert(icp); |
8ffe04ed | 60 | |
ad5d1add | 61 | cpu->intc = OBJECT(icp); |
8e4fba20 | 62 | icp->cs = cs; |
4a4b344c | 63 | |
8e4fba20 | 64 | icpc = ICP_GET_CLASS(icp); |
f0232434 | 65 | if (icpc->cpu_setup) { |
8e4fba20 | 66 | icpc->cpu_setup(icp, cpu); |
5eb92ccc AK |
67 | } |
68 | ||
8ffe04ed AK |
69 | switch (PPC_INPUT(env)) { |
70 | case PPC_FLAGS_INPUT_POWER7: | |
8e4fba20 | 71 | icp->output = env->irq_inputs[POWER7_INPUT_INT]; |
8ffe04ed AK |
72 | break; |
73 | ||
74 | case PPC_FLAGS_INPUT_970: | |
8e4fba20 | 75 | icp->output = env->irq_inputs[PPC970_INPUT_INT]; |
8ffe04ed AK |
76 | break; |
77 | ||
78 | default: | |
9ccff2a4 AK |
79 | error_report("XICS interrupt controller does not support this CPU " |
80 | "bus model"); | |
8ffe04ed AK |
81 | abort(); |
82 | } | |
83 | } | |
84 | ||
6449da45 | 85 | void icp_pic_print_info(ICPState *icp, Monitor *mon) |
b1fc72f0 | 86 | { |
b9038e78 CLG |
87 | int cpu_index = icp->cs ? icp->cs->cpu_index : -1; |
88 | ||
89 | if (!icp->output) { | |
90 | return; | |
91 | } | |
92 | monitor_printf(mon, "CPU %d XIRR=%08x (%p) PP=%02x MFRR=%02x\n", | |
93 | cpu_index, icp->xirr, icp->xirr_owner, | |
94 | icp->pending_priority, icp->mfrr); | |
95 | } | |
96 | ||
6449da45 | 97 | void ics_pic_print_info(ICSState *ics, Monitor *mon) |
b9038e78 | 98 | { |
b1fc72f0 BH |
99 | uint32_t i; |
100 | ||
b9038e78 CLG |
101 | monitor_printf(mon, "ICS %4x..%4x %p\n", |
102 | ics->offset, ics->offset + ics->nr_irqs - 1, ics); | |
b1fc72f0 | 103 | |
b9038e78 CLG |
104 | if (!ics->irqs) { |
105 | return; | |
b1fc72f0 BH |
106 | } |
107 | ||
b9038e78 CLG |
108 | for (i = 0; i < ics->nr_irqs; i++) { |
109 | ICSIRQState *irq = ics->irqs + i; | |
b1fc72f0 | 110 | |
b9038e78 | 111 | if (!(irq->flags & XICS_FLAGS_IRQ_MASK)) { |
b1fc72f0 BH |
112 | continue; |
113 | } | |
b9038e78 CLG |
114 | monitor_printf(mon, " %4x %s %02x %02x\n", |
115 | ics->offset + i, | |
116 | (irq->flags & XICS_FLAGS_IRQ_LSI) ? | |
117 | "LSI" : "MSI", | |
118 | irq->priority, irq->status); | |
b1fc72f0 BH |
119 | } |
120 | } | |
121 | ||
b5cec4c5 DG |
122 | /* |
123 | * ICP: Presentation layer | |
124 | */ | |
125 | ||
b5cec4c5 DG |
126 | #define XISR_MASK 0x00ffffff |
127 | #define CPPR_MASK 0xff000000 | |
128 | ||
8e4fba20 CLG |
129 | #define XISR(icp) (((icp)->xirr) & XISR_MASK) |
130 | #define CPPR(icp) (((icp)->xirr) >> 24) | |
b5cec4c5 | 131 | |
d4d7a59a BH |
132 | static void ics_reject(ICSState *ics, uint32_t nr) |
133 | { | |
134 | ICSStateClass *k = ICS_BASE_GET_CLASS(ics); | |
135 | ||
136 | if (k->reject) { | |
137 | k->reject(ics, nr); | |
138 | } | |
139 | } | |
140 | ||
7844e12b | 141 | void ics_resend(ICSState *ics) |
d4d7a59a BH |
142 | { |
143 | ICSStateClass *k = ICS_BASE_GET_CLASS(ics); | |
144 | ||
145 | if (k->resend) { | |
146 | k->resend(ics); | |
147 | } | |
148 | } | |
149 | ||
150 | static void ics_eoi(ICSState *ics, int nr) | |
151 | { | |
152 | ICSStateClass *k = ICS_BASE_GET_CLASS(ics); | |
153 | ||
154 | if (k->eoi) { | |
155 | k->eoi(ics, nr); | |
156 | } | |
157 | } | |
b5cec4c5 | 158 | |
8e4fba20 | 159 | static void icp_check_ipi(ICPState *icp) |
b5cec4c5 | 160 | { |
8e4fba20 | 161 | if (XISR(icp) && (icp->pending_priority <= icp->mfrr)) { |
b5cec4c5 DG |
162 | return; |
163 | } | |
164 | ||
8e4fba20 | 165 | trace_xics_icp_check_ipi(icp->cs->cpu_index, icp->mfrr); |
500efa23 | 166 | |
8e4fba20 CLG |
167 | if (XISR(icp) && icp->xirr_owner) { |
168 | ics_reject(icp->xirr_owner, XISR(icp)); | |
b5cec4c5 DG |
169 | } |
170 | ||
8e4fba20 CLG |
171 | icp->xirr = (icp->xirr & ~XISR_MASK) | XICS_IPI; |
172 | icp->pending_priority = icp->mfrr; | |
173 | icp->xirr_owner = NULL; | |
174 | qemu_irq_raise(icp->output); | |
b5cec4c5 DG |
175 | } |
176 | ||
8e4fba20 | 177 | void icp_resend(ICPState *icp) |
b5cec4c5 | 178 | { |
8e4fba20 | 179 | XICSFabric *xi = icp->xics; |
2cd908d0 | 180 | XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi); |
b5cec4c5 | 181 | |
8e4fba20 CLG |
182 | if (icp->mfrr < CPPR(icp)) { |
183 | icp_check_ipi(icp); | |
cc706a53 | 184 | } |
2cd908d0 CLG |
185 | |
186 | xic->ics_resend(xi); | |
b5cec4c5 DG |
187 | } |
188 | ||
8e4fba20 | 189 | void icp_set_cppr(ICPState *icp, uint8_t cppr) |
b5cec4c5 | 190 | { |
b5cec4c5 DG |
191 | uint8_t old_cppr; |
192 | uint32_t old_xisr; | |
193 | ||
8e4fba20 CLG |
194 | old_cppr = CPPR(icp); |
195 | icp->xirr = (icp->xirr & ~CPPR_MASK) | (cppr << 24); | |
b5cec4c5 DG |
196 | |
197 | if (cppr < old_cppr) { | |
8e4fba20 CLG |
198 | if (XISR(icp) && (cppr <= icp->pending_priority)) { |
199 | old_xisr = XISR(icp); | |
200 | icp->xirr &= ~XISR_MASK; /* Clear XISR */ | |
201 | icp->pending_priority = 0xff; | |
202 | qemu_irq_lower(icp->output); | |
203 | if (icp->xirr_owner) { | |
204 | ics_reject(icp->xirr_owner, old_xisr); | |
205 | icp->xirr_owner = NULL; | |
cc706a53 | 206 | } |
b5cec4c5 DG |
207 | } |
208 | } else { | |
8e4fba20 CLG |
209 | if (!XISR(icp)) { |
210 | icp_resend(icp); | |
b5cec4c5 DG |
211 | } |
212 | } | |
213 | } | |
214 | ||
8e4fba20 | 215 | void icp_set_mfrr(ICPState *icp, uint8_t mfrr) |
b5cec4c5 | 216 | { |
8e4fba20 CLG |
217 | icp->mfrr = mfrr; |
218 | if (mfrr < CPPR(icp)) { | |
219 | icp_check_ipi(icp); | |
b5cec4c5 DG |
220 | } |
221 | } | |
222 | ||
8e4fba20 | 223 | uint32_t icp_accept(ICPState *icp) |
b5cec4c5 | 224 | { |
8e4fba20 | 225 | uint32_t xirr = icp->xirr; |
b5cec4c5 | 226 | |
8e4fba20 CLG |
227 | qemu_irq_lower(icp->output); |
228 | icp->xirr = icp->pending_priority << 24; | |
229 | icp->pending_priority = 0xff; | |
230 | icp->xirr_owner = NULL; | |
500efa23 | 231 | |
8e4fba20 | 232 | trace_xics_icp_accept(xirr, icp->xirr); |
500efa23 | 233 | |
b5cec4c5 DG |
234 | return xirr; |
235 | } | |
236 | ||
8e4fba20 | 237 | uint32_t icp_ipoll(ICPState *icp, uint32_t *mfrr) |
1cbd2220 BH |
238 | { |
239 | if (mfrr) { | |
8e4fba20 | 240 | *mfrr = icp->mfrr; |
1cbd2220 | 241 | } |
8e4fba20 | 242 | return icp->xirr; |
1cbd2220 BH |
243 | } |
244 | ||
8e4fba20 | 245 | void icp_eoi(ICPState *icp, uint32_t xirr) |
b5cec4c5 | 246 | { |
8e4fba20 | 247 | XICSFabric *xi = icp->xics; |
2cd908d0 | 248 | XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi); |
cc706a53 BH |
249 | ICSState *ics; |
250 | uint32_t irq; | |
b5cec4c5 | 251 | |
b5cec4c5 | 252 | /* Send EOI -> ICS */ |
8e4fba20 CLG |
253 | icp->xirr = (icp->xirr & ~CPPR_MASK) | (xirr & CPPR_MASK); |
254 | trace_xics_icp_eoi(icp->cs->cpu_index, xirr, icp->xirr); | |
cc706a53 | 255 | irq = xirr & XISR_MASK; |
2cd908d0 CLG |
256 | |
257 | ics = xic->ics_get(xi, irq); | |
258 | if (ics) { | |
259 | ics_eoi(ics, irq); | |
cc706a53 | 260 | } |
8e4fba20 CLG |
261 | if (!XISR(icp)) { |
262 | icp_resend(icp); | |
b5cec4c5 DG |
263 | } |
264 | } | |
265 | ||
cc706a53 | 266 | static void icp_irq(ICSState *ics, int server, int nr, uint8_t priority) |
b5cec4c5 | 267 | { |
8e4fba20 | 268 | ICPState *icp = xics_icp_get(ics->xics, server); |
b5cec4c5 | 269 | |
500efa23 DG |
270 | trace_xics_icp_irq(server, nr, priority); |
271 | ||
8e4fba20 CLG |
272 | if ((priority >= CPPR(icp)) |
273 | || (XISR(icp) && (icp->pending_priority <= priority))) { | |
cc706a53 | 274 | ics_reject(ics, nr); |
b5cec4c5 | 275 | } else { |
8e4fba20 CLG |
276 | if (XISR(icp) && icp->xirr_owner) { |
277 | ics_reject(icp->xirr_owner, XISR(icp)); | |
278 | icp->xirr_owner = NULL; | |
b5cec4c5 | 279 | } |
8e4fba20 CLG |
280 | icp->xirr = (icp->xirr & ~XISR_MASK) | (nr & XISR_MASK); |
281 | icp->xirr_owner = ics; | |
282 | icp->pending_priority = priority; | |
283 | trace_xics_icp_raise(icp->xirr, icp->pending_priority); | |
284 | qemu_irq_raise(icp->output); | |
b5cec4c5 DG |
285 | } |
286 | } | |
287 | ||
d1b5682d AK |
288 | static void icp_dispatch_pre_save(void *opaque) |
289 | { | |
8e4fba20 CLG |
290 | ICPState *icp = opaque; |
291 | ICPStateClass *info = ICP_GET_CLASS(icp); | |
d1b5682d AK |
292 | |
293 | if (info->pre_save) { | |
8e4fba20 | 294 | info->pre_save(icp); |
d1b5682d AK |
295 | } |
296 | } | |
297 | ||
298 | static int icp_dispatch_post_load(void *opaque, int version_id) | |
299 | { | |
8e4fba20 CLG |
300 | ICPState *icp = opaque; |
301 | ICPStateClass *info = ICP_GET_CLASS(icp); | |
d1b5682d AK |
302 | |
303 | if (info->post_load) { | |
8e4fba20 | 304 | return info->post_load(icp, version_id); |
d1b5682d AK |
305 | } |
306 | ||
307 | return 0; | |
308 | } | |
309 | ||
c04d6cfa AL |
310 | static const VMStateDescription vmstate_icp_server = { |
311 | .name = "icp/server", | |
312 | .version_id = 1, | |
313 | .minimum_version_id = 1, | |
d1b5682d AK |
314 | .pre_save = icp_dispatch_pre_save, |
315 | .post_load = icp_dispatch_post_load, | |
3aff6c2f | 316 | .fields = (VMStateField[]) { |
c04d6cfa AL |
317 | /* Sanity check */ |
318 | VMSTATE_UINT32(xirr, ICPState), | |
319 | VMSTATE_UINT8(pending_priority, ICPState), | |
320 | VMSTATE_UINT8(mfrr, ICPState), | |
321 | VMSTATE_END_OF_LIST() | |
322 | }, | |
b5cec4c5 DG |
323 | }; |
324 | ||
7ea6e067 | 325 | static void icp_reset(void *dev) |
c04d6cfa AL |
326 | { |
327 | ICPState *icp = ICP(dev); | |
328 | ||
329 | icp->xirr = 0; | |
330 | icp->pending_priority = 0xff; | |
331 | icp->mfrr = 0xff; | |
332 | ||
333 | /* Make all outputs are deasserted */ | |
334 | qemu_set_irq(icp->output, 0); | |
335 | } | |
336 | ||
817bb6a4 CLG |
337 | static void icp_realize(DeviceState *dev, Error **errp) |
338 | { | |
339 | ICPState *icp = ICP(dev); | |
439071a9 | 340 | ICPStateClass *icpc = ICP_GET_CLASS(dev); |
817bb6a4 CLG |
341 | Object *obj; |
342 | Error *err = NULL; | |
343 | ||
344 | obj = object_property_get_link(OBJECT(dev), "xics", &err); | |
345 | if (!obj) { | |
346 | error_setg(errp, "%s: required link 'xics' not found: %s", | |
347 | __func__, error_get_pretty(err)); | |
348 | return; | |
349 | } | |
350 | ||
2cd908d0 | 351 | icp->xics = XICS_FABRIC(obj); |
7ea6e067 | 352 | |
439071a9 CLG |
353 | if (icpc->realize) { |
354 | icpc->realize(dev, errp); | |
355 | } | |
356 | ||
7ea6e067 | 357 | qemu_register_reset(icp_reset, dev); |
817bb6a4 CLG |
358 | } |
359 | ||
360 | ||
c04d6cfa AL |
361 | static void icp_class_init(ObjectClass *klass, void *data) |
362 | { | |
363 | DeviceClass *dc = DEVICE_CLASS(klass); | |
364 | ||
c04d6cfa | 365 | dc->vmsd = &vmstate_icp_server; |
817bb6a4 | 366 | dc->realize = icp_realize; |
c04d6cfa AL |
367 | } |
368 | ||
456df19c | 369 | static const TypeInfo icp_info = { |
c04d6cfa AL |
370 | .name = TYPE_ICP, |
371 | .parent = TYPE_DEVICE, | |
372 | .instance_size = sizeof(ICPState), | |
373 | .class_init = icp_class_init, | |
d1b5682d | 374 | .class_size = sizeof(ICPStateClass), |
b5cec4c5 DG |
375 | }; |
376 | ||
c04d6cfa AL |
377 | /* |
378 | * ICS: Source layer | |
379 | */ | |
d4d7a59a | 380 | static void ics_simple_resend_msi(ICSState *ics, int srcno) |
d07fee7e | 381 | { |
c04d6cfa | 382 | ICSIRQState *irq = ics->irqs + srcno; |
d07fee7e DG |
383 | |
384 | /* FIXME: filter by server#? */ | |
98ca8c02 DG |
385 | if (irq->status & XICS_STATUS_REJECTED) { |
386 | irq->status &= ~XICS_STATUS_REJECTED; | |
d07fee7e | 387 | if (irq->priority != 0xff) { |
cc706a53 | 388 | icp_irq(ics, irq->server, srcno + ics->offset, irq->priority); |
d07fee7e DG |
389 | } |
390 | } | |
391 | } | |
392 | ||
d4d7a59a | 393 | static void ics_simple_resend_lsi(ICSState *ics, int srcno) |
d07fee7e | 394 | { |
c04d6cfa | 395 | ICSIRQState *irq = ics->irqs + srcno; |
d07fee7e | 396 | |
98ca8c02 DG |
397 | if ((irq->priority != 0xff) |
398 | && (irq->status & XICS_STATUS_ASSERTED) | |
399 | && !(irq->status & XICS_STATUS_SENT)) { | |
400 | irq->status |= XICS_STATUS_SENT; | |
cc706a53 | 401 | icp_irq(ics, irq->server, srcno + ics->offset, irq->priority); |
d07fee7e DG |
402 | } |
403 | } | |
404 | ||
d4d7a59a | 405 | static void ics_simple_set_irq_msi(ICSState *ics, int srcno, int val) |
b5cec4c5 | 406 | { |
c04d6cfa | 407 | ICSIRQState *irq = ics->irqs + srcno; |
b5cec4c5 | 408 | |
d4d7a59a | 409 | trace_xics_ics_simple_set_irq_msi(srcno, srcno + ics->offset); |
500efa23 | 410 | |
b5cec4c5 DG |
411 | if (val) { |
412 | if (irq->priority == 0xff) { | |
98ca8c02 | 413 | irq->status |= XICS_STATUS_MASKED_PENDING; |
500efa23 | 414 | trace_xics_masked_pending(); |
b5cec4c5 | 415 | } else { |
cc706a53 | 416 | icp_irq(ics, irq->server, srcno + ics->offset, irq->priority); |
b5cec4c5 DG |
417 | } |
418 | } | |
419 | } | |
420 | ||
d4d7a59a | 421 | static void ics_simple_set_irq_lsi(ICSState *ics, int srcno, int val) |
b5cec4c5 | 422 | { |
c04d6cfa | 423 | ICSIRQState *irq = ics->irqs + srcno; |
b5cec4c5 | 424 | |
d4d7a59a | 425 | trace_xics_ics_simple_set_irq_lsi(srcno, srcno + ics->offset); |
98ca8c02 DG |
426 | if (val) { |
427 | irq->status |= XICS_STATUS_ASSERTED; | |
428 | } else { | |
429 | irq->status &= ~XICS_STATUS_ASSERTED; | |
430 | } | |
d4d7a59a | 431 | ics_simple_resend_lsi(ics, srcno); |
b5cec4c5 DG |
432 | } |
433 | ||
d4d7a59a | 434 | static void ics_simple_set_irq(void *opaque, int srcno, int val) |
b5cec4c5 | 435 | { |
c04d6cfa | 436 | ICSState *ics = (ICSState *)opaque; |
b5cec4c5 | 437 | |
4af88944 | 438 | if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) { |
d4d7a59a | 439 | ics_simple_set_irq_lsi(ics, srcno, val); |
d07fee7e | 440 | } else { |
d4d7a59a | 441 | ics_simple_set_irq_msi(ics, srcno, val); |
d07fee7e DG |
442 | } |
443 | } | |
b5cec4c5 | 444 | |
d4d7a59a | 445 | static void ics_simple_write_xive_msi(ICSState *ics, int srcno) |
d07fee7e | 446 | { |
c04d6cfa | 447 | ICSIRQState *irq = ics->irqs + srcno; |
d07fee7e | 448 | |
98ca8c02 DG |
449 | if (!(irq->status & XICS_STATUS_MASKED_PENDING) |
450 | || (irq->priority == 0xff)) { | |
d07fee7e | 451 | return; |
b5cec4c5 | 452 | } |
d07fee7e | 453 | |
98ca8c02 | 454 | irq->status &= ~XICS_STATUS_MASKED_PENDING; |
cc706a53 | 455 | icp_irq(ics, irq->server, srcno + ics->offset, irq->priority); |
b5cec4c5 DG |
456 | } |
457 | ||
d4d7a59a | 458 | static void ics_simple_write_xive_lsi(ICSState *ics, int srcno) |
b5cec4c5 | 459 | { |
d4d7a59a | 460 | ics_simple_resend_lsi(ics, srcno); |
d07fee7e DG |
461 | } |
462 | ||
d4d7a59a BH |
463 | void ics_simple_write_xive(ICSState *ics, int srcno, int server, |
464 | uint8_t priority, uint8_t saved_priority) | |
d07fee7e | 465 | { |
c04d6cfa | 466 | ICSIRQState *irq = ics->irqs + srcno; |
b5cec4c5 DG |
467 | |
468 | irq->server = server; | |
469 | irq->priority = priority; | |
3fe719f4 | 470 | irq->saved_priority = saved_priority; |
b5cec4c5 | 471 | |
d4d7a59a BH |
472 | trace_xics_ics_simple_write_xive(ics->offset + srcno, srcno, server, |
473 | priority); | |
500efa23 | 474 | |
4af88944 | 475 | if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) { |
d4d7a59a | 476 | ics_simple_write_xive_lsi(ics, srcno); |
d07fee7e | 477 | } else { |
d4d7a59a | 478 | ics_simple_write_xive_msi(ics, srcno); |
b5cec4c5 | 479 | } |
b5cec4c5 DG |
480 | } |
481 | ||
d4d7a59a | 482 | static void ics_simple_reject(ICSState *ics, uint32_t nr) |
b5cec4c5 | 483 | { |
c04d6cfa | 484 | ICSIRQState *irq = ics->irqs + nr - ics->offset; |
d07fee7e | 485 | |
d4d7a59a | 486 | trace_xics_ics_simple_reject(nr, nr - ics->offset); |
056b9775 ND |
487 | if (irq->flags & XICS_FLAGS_IRQ_MSI) { |
488 | irq->status |= XICS_STATUS_REJECTED; | |
489 | } else if (irq->flags & XICS_FLAGS_IRQ_LSI) { | |
490 | irq->status &= ~XICS_STATUS_SENT; | |
491 | } | |
b5cec4c5 DG |
492 | } |
493 | ||
d4d7a59a | 494 | static void ics_simple_resend(ICSState *ics) |
b5cec4c5 | 495 | { |
d07fee7e DG |
496 | int i; |
497 | ||
498 | for (i = 0; i < ics->nr_irqs; i++) { | |
d07fee7e | 499 | /* FIXME: filter by server#? */ |
4af88944 | 500 | if (ics->irqs[i].flags & XICS_FLAGS_IRQ_LSI) { |
d4d7a59a | 501 | ics_simple_resend_lsi(ics, i); |
d07fee7e | 502 | } else { |
d4d7a59a | 503 | ics_simple_resend_msi(ics, i); |
d07fee7e DG |
504 | } |
505 | } | |
b5cec4c5 DG |
506 | } |
507 | ||
d4d7a59a | 508 | static void ics_simple_eoi(ICSState *ics, uint32_t nr) |
b5cec4c5 | 509 | { |
d07fee7e | 510 | int srcno = nr - ics->offset; |
c04d6cfa | 511 | ICSIRQState *irq = ics->irqs + srcno; |
d07fee7e | 512 | |
d4d7a59a | 513 | trace_xics_ics_simple_eoi(nr); |
500efa23 | 514 | |
4af88944 | 515 | if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) { |
98ca8c02 | 516 | irq->status &= ~XICS_STATUS_SENT; |
d07fee7e | 517 | } |
b5cec4c5 DG |
518 | } |
519 | ||
7ea6e067 | 520 | static void ics_simple_reset(void *dev) |
c04d6cfa | 521 | { |
d4d7a59a | 522 | ICSState *ics = ICS_SIMPLE(dev); |
c04d6cfa | 523 | int i; |
a7e519a8 AK |
524 | uint8_t flags[ics->nr_irqs]; |
525 | ||
526 | for (i = 0; i < ics->nr_irqs; i++) { | |
527 | flags[i] = ics->irqs[i].flags; | |
528 | } | |
c04d6cfa AL |
529 | |
530 | memset(ics->irqs, 0, sizeof(ICSIRQState) * ics->nr_irqs); | |
a7e519a8 | 531 | |
c04d6cfa AL |
532 | for (i = 0; i < ics->nr_irqs; i++) { |
533 | ics->irqs[i].priority = 0xff; | |
534 | ics->irqs[i].saved_priority = 0xff; | |
a7e519a8 | 535 | ics->irqs[i].flags = flags[i]; |
c04d6cfa AL |
536 | } |
537 | } | |
538 | ||
d4d7a59a | 539 | static void ics_simple_dispatch_pre_save(void *opaque) |
d1b5682d AK |
540 | { |
541 | ICSState *ics = opaque; | |
d4d7a59a | 542 | ICSStateClass *info = ICS_BASE_GET_CLASS(ics); |
d1b5682d AK |
543 | |
544 | if (info->pre_save) { | |
545 | info->pre_save(ics); | |
546 | } | |
547 | } | |
548 | ||
d4d7a59a | 549 | static int ics_simple_dispatch_post_load(void *opaque, int version_id) |
d1b5682d AK |
550 | { |
551 | ICSState *ics = opaque; | |
d4d7a59a | 552 | ICSStateClass *info = ICS_BASE_GET_CLASS(ics); |
d1b5682d AK |
553 | |
554 | if (info->post_load) { | |
555 | return info->post_load(ics, version_id); | |
556 | } | |
557 | ||
558 | return 0; | |
559 | } | |
560 | ||
d4d7a59a | 561 | static const VMStateDescription vmstate_ics_simple_irq = { |
c04d6cfa | 562 | .name = "ics/irq", |
4af88944 | 563 | .version_id = 2, |
c04d6cfa | 564 | .minimum_version_id = 1, |
3aff6c2f | 565 | .fields = (VMStateField[]) { |
c04d6cfa AL |
566 | VMSTATE_UINT32(server, ICSIRQState), |
567 | VMSTATE_UINT8(priority, ICSIRQState), | |
568 | VMSTATE_UINT8(saved_priority, ICSIRQState), | |
569 | VMSTATE_UINT8(status, ICSIRQState), | |
4af88944 | 570 | VMSTATE_UINT8(flags, ICSIRQState), |
c04d6cfa AL |
571 | VMSTATE_END_OF_LIST() |
572 | }, | |
573 | }; | |
574 | ||
d4d7a59a | 575 | static const VMStateDescription vmstate_ics_simple = { |
c04d6cfa AL |
576 | .name = "ics", |
577 | .version_id = 1, | |
578 | .minimum_version_id = 1, | |
d4d7a59a BH |
579 | .pre_save = ics_simple_dispatch_pre_save, |
580 | .post_load = ics_simple_dispatch_post_load, | |
3aff6c2f | 581 | .fields = (VMStateField[]) { |
c04d6cfa AL |
582 | /* Sanity check */ |
583 | VMSTATE_UINT32_EQUAL(nr_irqs, ICSState), | |
584 | ||
585 | VMSTATE_STRUCT_VARRAY_POINTER_UINT32(irqs, ICSState, nr_irqs, | |
d4d7a59a BH |
586 | vmstate_ics_simple_irq, |
587 | ICSIRQState), | |
c04d6cfa AL |
588 | VMSTATE_END_OF_LIST() |
589 | }, | |
590 | }; | |
591 | ||
d4d7a59a | 592 | static void ics_simple_initfn(Object *obj) |
5a3d7b23 | 593 | { |
d4d7a59a | 594 | ICSState *ics = ICS_SIMPLE(obj); |
5a3d7b23 AK |
595 | |
596 | ics->offset = XICS_IRQ_BASE; | |
597 | } | |
598 | ||
d4d7a59a | 599 | static void ics_simple_realize(DeviceState *dev, Error **errp) |
c04d6cfa | 600 | { |
d4d7a59a | 601 | ICSState *ics = ICS_SIMPLE(dev); |
c04d6cfa | 602 | |
b45ff2d9 AK |
603 | if (!ics->nr_irqs) { |
604 | error_setg(errp, "Number of interrupts needs to be greater 0"); | |
605 | return; | |
606 | } | |
c04d6cfa | 607 | ics->irqs = g_malloc0(ics->nr_irqs * sizeof(ICSIRQState)); |
d4d7a59a | 608 | ics->qirqs = qemu_allocate_irqs(ics_simple_set_irq, ics, ics->nr_irqs); |
7ea6e067 CLG |
609 | |
610 | qemu_register_reset(ics_simple_reset, dev); | |
c04d6cfa AL |
611 | } |
612 | ||
4e4169f7 CLG |
613 | static Property ics_simple_properties[] = { |
614 | DEFINE_PROP_UINT32("nr-irqs", ICSState, nr_irqs, 0), | |
615 | DEFINE_PROP_END_OF_LIST(), | |
616 | }; | |
617 | ||
d4d7a59a | 618 | static void ics_simple_class_init(ObjectClass *klass, void *data) |
c04d6cfa AL |
619 | { |
620 | DeviceClass *dc = DEVICE_CLASS(klass); | |
d4d7a59a | 621 | ICSStateClass *isc = ICS_BASE_CLASS(klass); |
c04d6cfa | 622 | |
4e4169f7 CLG |
623 | isc->realize = ics_simple_realize; |
624 | dc->props = ics_simple_properties; | |
d4d7a59a | 625 | dc->vmsd = &vmstate_ics_simple; |
d4d7a59a BH |
626 | isc->reject = ics_simple_reject; |
627 | isc->resend = ics_simple_resend; | |
628 | isc->eoi = ics_simple_eoi; | |
c04d6cfa AL |
629 | } |
630 | ||
d4d7a59a BH |
631 | static const TypeInfo ics_simple_info = { |
632 | .name = TYPE_ICS_SIMPLE, | |
633 | .parent = TYPE_ICS_BASE, | |
634 | .instance_size = sizeof(ICSState), | |
635 | .class_init = ics_simple_class_init, | |
636 | .class_size = sizeof(ICSStateClass), | |
637 | .instance_init = ics_simple_initfn, | |
638 | }; | |
639 | ||
4e4169f7 CLG |
640 | static void ics_base_realize(DeviceState *dev, Error **errp) |
641 | { | |
642 | ICSStateClass *icsc = ICS_BASE_GET_CLASS(dev); | |
643 | ICSState *ics = ICS_BASE(dev); | |
644 | Object *obj; | |
645 | Error *err = NULL; | |
646 | ||
647 | obj = object_property_get_link(OBJECT(dev), "xics", &err); | |
648 | if (!obj) { | |
649 | error_setg(errp, "%s: required link 'xics' not found: %s", | |
650 | __func__, error_get_pretty(err)); | |
651 | return; | |
652 | } | |
b4f27d71 | 653 | ics->xics = XICS_FABRIC(obj); |
4e4169f7 CLG |
654 | |
655 | ||
656 | if (icsc->realize) { | |
657 | icsc->realize(dev, errp); | |
658 | } | |
659 | } | |
660 | ||
661 | static void ics_base_class_init(ObjectClass *klass, void *data) | |
662 | { | |
663 | DeviceClass *dc = DEVICE_CLASS(klass); | |
664 | ||
665 | dc->realize = ics_base_realize; | |
666 | } | |
667 | ||
d4d7a59a BH |
668 | static const TypeInfo ics_base_info = { |
669 | .name = TYPE_ICS_BASE, | |
c04d6cfa | 670 | .parent = TYPE_DEVICE, |
d4d7a59a | 671 | .abstract = true, |
c04d6cfa | 672 | .instance_size = sizeof(ICSState), |
4e4169f7 | 673 | .class_init = ics_base_class_init, |
d1b5682d | 674 | .class_size = sizeof(ICSStateClass), |
c04d6cfa AL |
675 | }; |
676 | ||
51b18005 CLG |
677 | static const TypeInfo xics_fabric_info = { |
678 | .name = TYPE_XICS_FABRIC, | |
679 | .parent = TYPE_INTERFACE, | |
680 | .class_size = sizeof(XICSFabricClass), | |
681 | }; | |
682 | ||
b5cec4c5 DG |
683 | /* |
684 | * Exported functions | |
685 | */ | |
f7759e43 | 686 | qemu_irq xics_get_qirq(XICSFabric *xi, int irq) |
b5cec4c5 | 687 | { |
f7759e43 CLG |
688 | XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi); |
689 | ICSState *ics = xic->ics_get(xi, irq); | |
641c3493 | 690 | |
cc706a53 | 691 | if (ics) { |
641c3493 | 692 | return ics->qirqs[irq - ics->offset]; |
b5cec4c5 DG |
693 | } |
694 | ||
641c3493 | 695 | return NULL; |
a307d594 AK |
696 | } |
697 | ||
b4f27d71 CLG |
698 | ICPState *xics_icp_get(XICSFabric *xi, int server) |
699 | { | |
700 | XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi); | |
701 | ||
702 | return xic->icp_get(xi, server); | |
703 | } | |
704 | ||
9c7027ba | 705 | void ics_set_irq_type(ICSState *ics, int srcno, bool lsi) |
4af88944 AK |
706 | { |
707 | assert(!(ics->irqs[srcno].flags & XICS_FLAGS_IRQ_MASK)); | |
708 | ||
709 | ics->irqs[srcno].flags |= | |
710 | lsi ? XICS_FLAGS_IRQ_LSI : XICS_FLAGS_IRQ_MSI; | |
711 | } | |
712 | ||
c04d6cfa AL |
713 | static void xics_register_types(void) |
714 | { | |
d4d7a59a BH |
715 | type_register_static(&ics_simple_info); |
716 | type_register_static(&ics_base_info); | |
c04d6cfa | 717 | type_register_static(&icp_info); |
51b18005 | 718 | type_register_static(&xics_fabric_info); |
b5cec4c5 | 719 | } |
c04d6cfa AL |
720 | |
721 | type_init(xics_register_types) |