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Commit | Line | Data |
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b5cec4c5 DG |
1 | /* |
2 | * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator | |
3 | * | |
4 | * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics | |
5 | * | |
6 | * Copyright (c) 2010,2011 David Gibson, IBM Corporation. | |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
9 | * of this software and associated documentation files (the "Software"), to deal | |
10 | * in the Software without restriction, including without limitation the rights | |
11 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
12 | * copies of the Software, and to permit persons to whom the Software is | |
13 | * furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice shall be included in | |
16 | * all copies or substantial portions of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
22 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
23 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
24 | * THE SOFTWARE. | |
25 | * | |
26 | */ | |
27 | ||
0d75590d | 28 | #include "qemu/osdep.h" |
da34e65c | 29 | #include "qapi/error.h" |
4771d756 | 30 | #include "cpu.h" |
500efa23 | 31 | #include "trace.h" |
5d87e4b7 | 32 | #include "qemu/timer.h" |
0d09e41a | 33 | #include "hw/ppc/xics.h" |
a27bd6c7 | 34 | #include "hw/qdev-properties.h" |
9ccff2a4 | 35 | #include "qemu/error-report.h" |
0b8fa32f | 36 | #include "qemu/module.h" |
5a3d7b23 | 37 | #include "qapi/visitor.h" |
d6454270 | 38 | #include "migration/vmstate.h" |
b1fc72f0 BH |
39 | #include "monitor/monitor.h" |
40 | #include "hw/intc/intc.h" | |
64552b6b | 41 | #include "hw/irq.h" |
0e5c7fad | 42 | #include "sysemu/kvm.h" |
71e8a915 | 43 | #include "sysemu/reset.h" |
b5cec4c5 | 44 | |
6449da45 | 45 | void icp_pic_print_info(ICPState *icp, Monitor *mon) |
b1fc72f0 | 46 | { |
0a83b470 GK |
47 | int cpu_index; |
48 | ||
49 | /* Skip partially initialized vCPUs. This can happen on sPAPR when vCPUs | |
50 | * are hot plugged or unplugged. | |
51 | */ | |
52 | if (!icp) { | |
53 | return; | |
54 | } | |
55 | ||
56 | cpu_index = icp->cs ? icp->cs->cpu_index : -1; | |
b9038e78 CLG |
57 | |
58 | if (!icp->output) { | |
59 | return; | |
60 | } | |
dcb556fc | 61 | |
0e5c7fad GK |
62 | if (kvm_irqchip_in_kernel()) { |
63 | icp_synchronize_state(icp); | |
dcb556fc GK |
64 | } |
65 | ||
b9038e78 CLG |
66 | monitor_printf(mon, "CPU %d XIRR=%08x (%p) PP=%02x MFRR=%02x\n", |
67 | cpu_index, icp->xirr, icp->xirr_owner, | |
68 | icp->pending_priority, icp->mfrr); | |
69 | } | |
70 | ||
6449da45 | 71 | void ics_pic_print_info(ICSState *ics, Monitor *mon) |
b9038e78 | 72 | { |
b1fc72f0 BH |
73 | uint32_t i; |
74 | ||
b9038e78 CLG |
75 | monitor_printf(mon, "ICS %4x..%4x %p\n", |
76 | ics->offset, ics->offset + ics->nr_irqs - 1, ics); | |
b1fc72f0 | 77 | |
b9038e78 CLG |
78 | if (!ics->irqs) { |
79 | return; | |
b1fc72f0 BH |
80 | } |
81 | ||
d80b2ccf GK |
82 | if (kvm_irqchip_in_kernel()) { |
83 | ics_synchronize_state(ics); | |
dcb556fc GK |
84 | } |
85 | ||
b9038e78 CLG |
86 | for (i = 0; i < ics->nr_irqs; i++) { |
87 | ICSIRQState *irq = ics->irqs + i; | |
b1fc72f0 | 88 | |
b9038e78 | 89 | if (!(irq->flags & XICS_FLAGS_IRQ_MASK)) { |
b1fc72f0 BH |
90 | continue; |
91 | } | |
b9038e78 CLG |
92 | monitor_printf(mon, " %4x %s %02x %02x\n", |
93 | ics->offset + i, | |
94 | (irq->flags & XICS_FLAGS_IRQ_LSI) ? | |
95 | "LSI" : "MSI", | |
96 | irq->priority, irq->status); | |
b1fc72f0 BH |
97 | } |
98 | } | |
99 | ||
b5cec4c5 DG |
100 | /* |
101 | * ICP: Presentation layer | |
102 | */ | |
103 | ||
b5cec4c5 DG |
104 | #define XISR_MASK 0x00ffffff |
105 | #define CPPR_MASK 0xff000000 | |
106 | ||
8e4fba20 CLG |
107 | #define XISR(icp) (((icp)->xirr) & XISR_MASK) |
108 | #define CPPR(icp) (((icp)->xirr) >> 24) | |
b5cec4c5 | 109 | |
d5803c73 DG |
110 | static void ics_reject(ICSState *ics, uint32_t nr); |
111 | static void ics_eoi(ICSState *ics, uint32_t nr); | |
b5cec4c5 | 112 | |
8e4fba20 | 113 | static void icp_check_ipi(ICPState *icp) |
b5cec4c5 | 114 | { |
8e4fba20 | 115 | if (XISR(icp) && (icp->pending_priority <= icp->mfrr)) { |
b5cec4c5 DG |
116 | return; |
117 | } | |
118 | ||
8e4fba20 | 119 | trace_xics_icp_check_ipi(icp->cs->cpu_index, icp->mfrr); |
500efa23 | 120 | |
8e4fba20 CLG |
121 | if (XISR(icp) && icp->xirr_owner) { |
122 | ics_reject(icp->xirr_owner, XISR(icp)); | |
b5cec4c5 DG |
123 | } |
124 | ||
8e4fba20 CLG |
125 | icp->xirr = (icp->xirr & ~XISR_MASK) | XICS_IPI; |
126 | icp->pending_priority = icp->mfrr; | |
127 | icp->xirr_owner = NULL; | |
128 | qemu_irq_raise(icp->output); | |
b5cec4c5 DG |
129 | } |
130 | ||
8e4fba20 | 131 | void icp_resend(ICPState *icp) |
b5cec4c5 | 132 | { |
8e4fba20 | 133 | XICSFabric *xi = icp->xics; |
2cd908d0 | 134 | XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi); |
b5cec4c5 | 135 | |
8e4fba20 CLG |
136 | if (icp->mfrr < CPPR(icp)) { |
137 | icp_check_ipi(icp); | |
cc706a53 | 138 | } |
2cd908d0 CLG |
139 | |
140 | xic->ics_resend(xi); | |
b5cec4c5 DG |
141 | } |
142 | ||
8e4fba20 | 143 | void icp_set_cppr(ICPState *icp, uint8_t cppr) |
b5cec4c5 | 144 | { |
b5cec4c5 DG |
145 | uint8_t old_cppr; |
146 | uint32_t old_xisr; | |
147 | ||
8e4fba20 CLG |
148 | old_cppr = CPPR(icp); |
149 | icp->xirr = (icp->xirr & ~CPPR_MASK) | (cppr << 24); | |
b5cec4c5 DG |
150 | |
151 | if (cppr < old_cppr) { | |
8e4fba20 CLG |
152 | if (XISR(icp) && (cppr <= icp->pending_priority)) { |
153 | old_xisr = XISR(icp); | |
154 | icp->xirr &= ~XISR_MASK; /* Clear XISR */ | |
155 | icp->pending_priority = 0xff; | |
156 | qemu_irq_lower(icp->output); | |
157 | if (icp->xirr_owner) { | |
158 | ics_reject(icp->xirr_owner, old_xisr); | |
159 | icp->xirr_owner = NULL; | |
cc706a53 | 160 | } |
b5cec4c5 DG |
161 | } |
162 | } else { | |
8e4fba20 CLG |
163 | if (!XISR(icp)) { |
164 | icp_resend(icp); | |
b5cec4c5 DG |
165 | } |
166 | } | |
167 | } | |
168 | ||
8e4fba20 | 169 | void icp_set_mfrr(ICPState *icp, uint8_t mfrr) |
b5cec4c5 | 170 | { |
8e4fba20 CLG |
171 | icp->mfrr = mfrr; |
172 | if (mfrr < CPPR(icp)) { | |
173 | icp_check_ipi(icp); | |
b5cec4c5 DG |
174 | } |
175 | } | |
176 | ||
8e4fba20 | 177 | uint32_t icp_accept(ICPState *icp) |
b5cec4c5 | 178 | { |
8e4fba20 | 179 | uint32_t xirr = icp->xirr; |
b5cec4c5 | 180 | |
8e4fba20 CLG |
181 | qemu_irq_lower(icp->output); |
182 | icp->xirr = icp->pending_priority << 24; | |
183 | icp->pending_priority = 0xff; | |
184 | icp->xirr_owner = NULL; | |
500efa23 | 185 | |
8e4fba20 | 186 | trace_xics_icp_accept(xirr, icp->xirr); |
500efa23 | 187 | |
b5cec4c5 DG |
188 | return xirr; |
189 | } | |
190 | ||
8e4fba20 | 191 | uint32_t icp_ipoll(ICPState *icp, uint32_t *mfrr) |
1cbd2220 BH |
192 | { |
193 | if (mfrr) { | |
8e4fba20 | 194 | *mfrr = icp->mfrr; |
1cbd2220 | 195 | } |
8e4fba20 | 196 | return icp->xirr; |
1cbd2220 BH |
197 | } |
198 | ||
8e4fba20 | 199 | void icp_eoi(ICPState *icp, uint32_t xirr) |
b5cec4c5 | 200 | { |
8e4fba20 | 201 | XICSFabric *xi = icp->xics; |
2cd908d0 | 202 | XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi); |
cc706a53 BH |
203 | ICSState *ics; |
204 | uint32_t irq; | |
b5cec4c5 | 205 | |
b5cec4c5 | 206 | /* Send EOI -> ICS */ |
8e4fba20 CLG |
207 | icp->xirr = (icp->xirr & ~CPPR_MASK) | (xirr & CPPR_MASK); |
208 | trace_xics_icp_eoi(icp->cs->cpu_index, xirr, icp->xirr); | |
cc706a53 | 209 | irq = xirr & XISR_MASK; |
2cd908d0 CLG |
210 | |
211 | ics = xic->ics_get(xi, irq); | |
212 | if (ics) { | |
213 | ics_eoi(ics, irq); | |
cc706a53 | 214 | } |
8e4fba20 CLG |
215 | if (!XISR(icp)) { |
216 | icp_resend(icp); | |
b5cec4c5 DG |
217 | } |
218 | } | |
219 | ||
9ae1329e | 220 | void icp_irq(ICSState *ics, int server, int nr, uint8_t priority) |
b5cec4c5 | 221 | { |
8e4fba20 | 222 | ICPState *icp = xics_icp_get(ics->xics, server); |
b5cec4c5 | 223 | |
500efa23 DG |
224 | trace_xics_icp_irq(server, nr, priority); |
225 | ||
8e4fba20 CLG |
226 | if ((priority >= CPPR(icp)) |
227 | || (XISR(icp) && (icp->pending_priority <= priority))) { | |
cc706a53 | 228 | ics_reject(ics, nr); |
b5cec4c5 | 229 | } else { |
8e4fba20 CLG |
230 | if (XISR(icp) && icp->xirr_owner) { |
231 | ics_reject(icp->xirr_owner, XISR(icp)); | |
232 | icp->xirr_owner = NULL; | |
b5cec4c5 | 233 | } |
8e4fba20 CLG |
234 | icp->xirr = (icp->xirr & ~XISR_MASK) | (nr & XISR_MASK); |
235 | icp->xirr_owner = ics; | |
236 | icp->pending_priority = priority; | |
237 | trace_xics_icp_raise(icp->xirr, icp->pending_priority); | |
238 | qemu_irq_raise(icp->output); | |
b5cec4c5 DG |
239 | } |
240 | } | |
241 | ||
0e5c7fad | 242 | static int icp_pre_save(void *opaque) |
d1b5682d | 243 | { |
8e4fba20 | 244 | ICPState *icp = opaque; |
d1b5682d | 245 | |
0e5c7fad GK |
246 | if (kvm_irqchip_in_kernel()) { |
247 | icp_get_kvm_state(icp); | |
d1b5682d | 248 | } |
44b1ff31 DDAG |
249 | |
250 | return 0; | |
d1b5682d AK |
251 | } |
252 | ||
0e5c7fad | 253 | static int icp_post_load(void *opaque, int version_id) |
d1b5682d | 254 | { |
8e4fba20 | 255 | ICPState *icp = opaque; |
d1b5682d | 256 | |
0e5c7fad | 257 | if (kvm_irqchip_in_kernel()) { |
330a21e3 GK |
258 | Error *local_err = NULL; |
259 | int ret; | |
260 | ||
261 | ret = icp_set_kvm_state(icp, &local_err); | |
262 | if (ret < 0) { | |
263 | error_report_err(local_err); | |
264 | return ret; | |
265 | } | |
d1b5682d AK |
266 | } |
267 | ||
268 | return 0; | |
269 | } | |
270 | ||
c04d6cfa AL |
271 | static const VMStateDescription vmstate_icp_server = { |
272 | .name = "icp/server", | |
273 | .version_id = 1, | |
274 | .minimum_version_id = 1, | |
0e5c7fad GK |
275 | .pre_save = icp_pre_save, |
276 | .post_load = icp_post_load, | |
3aff6c2f | 277 | .fields = (VMStateField[]) { |
c04d6cfa AL |
278 | /* Sanity check */ |
279 | VMSTATE_UINT32(xirr, ICPState), | |
280 | VMSTATE_UINT8(pending_priority, ICPState), | |
281 | VMSTATE_UINT8(mfrr, ICPState), | |
282 | VMSTATE_END_OF_LIST() | |
283 | }, | |
b5cec4c5 DG |
284 | }; |
285 | ||
d49e8a9b | 286 | void icp_reset(ICPState *icp) |
c04d6cfa | 287 | { |
c04d6cfa AL |
288 | icp->xirr = 0; |
289 | icp->pending_priority = 0xff; | |
290 | icp->mfrr = 0xff; | |
291 | ||
d82f3971 | 292 | if (kvm_irqchip_in_kernel()) { |
330a21e3 GK |
293 | Error *local_err = NULL; |
294 | ||
d49e8a9b | 295 | icp_set_kvm_state(icp, &local_err); |
330a21e3 GK |
296 | if (local_err) { |
297 | error_report_err(local_err); | |
298 | } | |
d82f3971 | 299 | } |
b585395b GK |
300 | } |
301 | ||
817bb6a4 CLG |
302 | static void icp_realize(DeviceState *dev, Error **errp) |
303 | { | |
304 | ICPState *icp = ICP(dev); | |
9ed65663 | 305 | CPUPPCState *env; |
817bb6a4 CLG |
306 | Error *err = NULL; |
307 | ||
b4a378a7 | 308 | assert(icp->xics); |
e388d66b | 309 | assert(icp->cs); |
7ea6e067 | 310 | |
e388d66b | 311 | env = &POWERPC_CPU(icp->cs)->env; |
9ed65663 GK |
312 | switch (PPC_INPUT(env)) { |
313 | case PPC_FLAGS_INPUT_POWER7: | |
314 | icp->output = env->irq_inputs[POWER7_INPUT_INT]; | |
315 | break; | |
67afe775 BH |
316 | case PPC_FLAGS_INPUT_POWER9: /* For SPAPR xics emulation */ |
317 | icp->output = env->irq_inputs[POWER9_INPUT_INT]; | |
318 | break; | |
9ed65663 GK |
319 | |
320 | case PPC_FLAGS_INPUT_970: | |
321 | icp->output = env->irq_inputs[PPC970_INPUT_INT]; | |
322 | break; | |
323 | ||
324 | default: | |
325 | error_setg(errp, "XICS interrupt controller does not support this CPU bus model"); | |
326 | return; | |
327 | } | |
328 | ||
d9b9e6f6 | 329 | /* Connect the presenter to the VCPU (required for CPU hotplug) */ |
8e6e6efe GK |
330 | if (kvm_irqchip_in_kernel()) { |
331 | icp_kvm_realize(dev, &err); | |
332 | if (err) { | |
333 | error_propagate(errp, err); | |
334 | return; | |
335 | } | |
336 | } | |
337 | ||
c95f6161 | 338 | vmstate_register(NULL, icp->cs->cpu_index, &vmstate_icp_server, icp); |
817bb6a4 CLG |
339 | } |
340 | ||
b69c3c21 | 341 | static void icp_unrealize(DeviceState *dev) |
62f94fc9 | 342 | { |
c95f6161 GK |
343 | ICPState *icp = ICP(dev); |
344 | ||
345 | vmstate_unregister(NULL, &vmstate_icp_server, icp); | |
62f94fc9 | 346 | } |
817bb6a4 | 347 | |
b4a378a7 GK |
348 | static Property icp_properties[] = { |
349 | DEFINE_PROP_LINK(ICP_PROP_XICS, ICPState, xics, TYPE_XICS_FABRIC, | |
350 | XICSFabric *), | |
e388d66b | 351 | DEFINE_PROP_LINK(ICP_PROP_CPU, ICPState, cs, TYPE_CPU, CPUState *), |
b4a378a7 GK |
352 | DEFINE_PROP_END_OF_LIST(), |
353 | }; | |
354 | ||
c04d6cfa AL |
355 | static void icp_class_init(ObjectClass *klass, void *data) |
356 | { | |
357 | DeviceClass *dc = DEVICE_CLASS(klass); | |
358 | ||
817bb6a4 | 359 | dc->realize = icp_realize; |
62f94fc9 | 360 | dc->unrealize = icp_unrealize; |
4f67d30b | 361 | device_class_set_props(dc, icp_properties); |
e6144bf9 GK |
362 | /* |
363 | * Reason: part of XICS interrupt controller, needs to be wired up | |
364 | * by icp_create(). | |
365 | */ | |
366 | dc->user_creatable = false; | |
c04d6cfa AL |
367 | } |
368 | ||
456df19c | 369 | static const TypeInfo icp_info = { |
c04d6cfa AL |
370 | .name = TYPE_ICP, |
371 | .parent = TYPE_DEVICE, | |
372 | .instance_size = sizeof(ICPState), | |
373 | .class_init = icp_class_init, | |
d1b5682d | 374 | .class_size = sizeof(ICPStateClass), |
b5cec4c5 DG |
375 | }; |
376 | ||
4f7a47be CLG |
377 | Object *icp_create(Object *cpu, const char *type, XICSFabric *xi, Error **errp) |
378 | { | |
379 | Error *local_err = NULL; | |
380 | Object *obj; | |
381 | ||
382 | obj = object_new(type); | |
d2623129 | 383 | object_property_add_child(cpu, type, obj); |
4f7a47be | 384 | object_unref(obj); |
b4a378a7 | 385 | object_property_set_link(obj, OBJECT(xi), ICP_PROP_XICS, &error_abort); |
e388d66b | 386 | object_property_set_link(obj, cpu, ICP_PROP_CPU, &error_abort); |
ce189ab2 | 387 | qdev_realize(DEVICE(obj), NULL, &local_err); |
4f7a47be CLG |
388 | if (local_err) { |
389 | object_unparent(obj); | |
390 | error_propagate(errp, local_err); | |
391 | obj = NULL; | |
392 | } | |
393 | ||
394 | return obj; | |
395 | } | |
396 | ||
0990ce6a GK |
397 | void icp_destroy(ICPState *icp) |
398 | { | |
35886de1 GK |
399 | Object *obj = OBJECT(icp); |
400 | ||
35886de1 | 401 | object_unparent(obj); |
0990ce6a GK |
402 | } |
403 | ||
c04d6cfa AL |
404 | /* |
405 | * ICS: Source layer | |
406 | */ | |
d5803c73 | 407 | static void ics_resend_msi(ICSState *ics, int srcno) |
d07fee7e | 408 | { |
c04d6cfa | 409 | ICSIRQState *irq = ics->irqs + srcno; |
d07fee7e DG |
410 | |
411 | /* FIXME: filter by server#? */ | |
98ca8c02 DG |
412 | if (irq->status & XICS_STATUS_REJECTED) { |
413 | irq->status &= ~XICS_STATUS_REJECTED; | |
d07fee7e | 414 | if (irq->priority != 0xff) { |
cc706a53 | 415 | icp_irq(ics, irq->server, srcno + ics->offset, irq->priority); |
d07fee7e DG |
416 | } |
417 | } | |
418 | } | |
419 | ||
d5803c73 | 420 | static void ics_resend_lsi(ICSState *ics, int srcno) |
d07fee7e | 421 | { |
c04d6cfa | 422 | ICSIRQState *irq = ics->irqs + srcno; |
d07fee7e | 423 | |
98ca8c02 DG |
424 | if ((irq->priority != 0xff) |
425 | && (irq->status & XICS_STATUS_ASSERTED) | |
426 | && !(irq->status & XICS_STATUS_SENT)) { | |
427 | irq->status |= XICS_STATUS_SENT; | |
cc706a53 | 428 | icp_irq(ics, irq->server, srcno + ics->offset, irq->priority); |
d07fee7e DG |
429 | } |
430 | } | |
431 | ||
28976c99 | 432 | static void ics_set_irq_msi(ICSState *ics, int srcno, int val) |
b5cec4c5 | 433 | { |
c04d6cfa | 434 | ICSIRQState *irq = ics->irqs + srcno; |
b5cec4c5 | 435 | |
28976c99 | 436 | trace_xics_ics_set_irq_msi(srcno, srcno + ics->offset); |
500efa23 | 437 | |
b5cec4c5 DG |
438 | if (val) { |
439 | if (irq->priority == 0xff) { | |
98ca8c02 | 440 | irq->status |= XICS_STATUS_MASKED_PENDING; |
500efa23 | 441 | trace_xics_masked_pending(); |
b5cec4c5 | 442 | } else { |
cc706a53 | 443 | icp_irq(ics, irq->server, srcno + ics->offset, irq->priority); |
b5cec4c5 DG |
444 | } |
445 | } | |
446 | } | |
447 | ||
28976c99 | 448 | static void ics_set_irq_lsi(ICSState *ics, int srcno, int val) |
b5cec4c5 | 449 | { |
c04d6cfa | 450 | ICSIRQState *irq = ics->irqs + srcno; |
b5cec4c5 | 451 | |
28976c99 | 452 | trace_xics_ics_set_irq_lsi(srcno, srcno + ics->offset); |
98ca8c02 DG |
453 | if (val) { |
454 | irq->status |= XICS_STATUS_ASSERTED; | |
455 | } else { | |
456 | irq->status &= ~XICS_STATUS_ASSERTED; | |
457 | } | |
d5803c73 | 458 | ics_resend_lsi(ics, srcno); |
b5cec4c5 DG |
459 | } |
460 | ||
28976c99 | 461 | void ics_set_irq(void *opaque, int srcno, int val) |
b5cec4c5 | 462 | { |
c04d6cfa | 463 | ICSState *ics = (ICSState *)opaque; |
b5cec4c5 | 464 | |
557b4567 GK |
465 | if (kvm_irqchip_in_kernel()) { |
466 | ics_kvm_set_irq(ics, srcno, val); | |
467 | return; | |
468 | } | |
469 | ||
4af88944 | 470 | if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) { |
28976c99 | 471 | ics_set_irq_lsi(ics, srcno, val); |
d07fee7e | 472 | } else { |
28976c99 | 473 | ics_set_irq_msi(ics, srcno, val); |
d07fee7e DG |
474 | } |
475 | } | |
b5cec4c5 | 476 | |
28976c99 | 477 | static void ics_write_xive_msi(ICSState *ics, int srcno) |
d07fee7e | 478 | { |
c04d6cfa | 479 | ICSIRQState *irq = ics->irqs + srcno; |
d07fee7e | 480 | |
98ca8c02 DG |
481 | if (!(irq->status & XICS_STATUS_MASKED_PENDING) |
482 | || (irq->priority == 0xff)) { | |
d07fee7e | 483 | return; |
b5cec4c5 | 484 | } |
d07fee7e | 485 | |
98ca8c02 | 486 | irq->status &= ~XICS_STATUS_MASKED_PENDING; |
cc706a53 | 487 | icp_irq(ics, irq->server, srcno + ics->offset, irq->priority); |
b5cec4c5 DG |
488 | } |
489 | ||
28976c99 | 490 | static void ics_write_xive_lsi(ICSState *ics, int srcno) |
b5cec4c5 | 491 | { |
d5803c73 | 492 | ics_resend_lsi(ics, srcno); |
d07fee7e DG |
493 | } |
494 | ||
28976c99 DG |
495 | void ics_write_xive(ICSState *ics, int srcno, int server, |
496 | uint8_t priority, uint8_t saved_priority) | |
d07fee7e | 497 | { |
c04d6cfa | 498 | ICSIRQState *irq = ics->irqs + srcno; |
b5cec4c5 DG |
499 | |
500 | irq->server = server; | |
501 | irq->priority = priority; | |
3fe719f4 | 502 | irq->saved_priority = saved_priority; |
b5cec4c5 | 503 | |
28976c99 | 504 | trace_xics_ics_write_xive(ics->offset + srcno, srcno, server, priority); |
500efa23 | 505 | |
4af88944 | 506 | if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) { |
28976c99 | 507 | ics_write_xive_lsi(ics, srcno); |
d07fee7e | 508 | } else { |
28976c99 | 509 | ics_write_xive_msi(ics, srcno); |
b5cec4c5 | 510 | } |
b5cec4c5 DG |
511 | } |
512 | ||
d5803c73 | 513 | static void ics_reject(ICSState *ics, uint32_t nr) |
b5cec4c5 | 514 | { |
9ae1329e | 515 | ICSStateClass *isc = ICS_GET_CLASS(ics); |
c04d6cfa | 516 | ICSIRQState *irq = ics->irqs + nr - ics->offset; |
d07fee7e | 517 | |
9ae1329e CLG |
518 | if (isc->reject) { |
519 | isc->reject(ics, nr); | |
520 | return; | |
521 | } | |
522 | ||
d5803c73 | 523 | trace_xics_ics_reject(nr, nr - ics->offset); |
056b9775 ND |
524 | if (irq->flags & XICS_FLAGS_IRQ_MSI) { |
525 | irq->status |= XICS_STATUS_REJECTED; | |
526 | } else if (irq->flags & XICS_FLAGS_IRQ_LSI) { | |
527 | irq->status &= ~XICS_STATUS_SENT; | |
528 | } | |
b5cec4c5 DG |
529 | } |
530 | ||
d5803c73 | 531 | void ics_resend(ICSState *ics) |
b5cec4c5 | 532 | { |
9ae1329e | 533 | ICSStateClass *isc = ICS_GET_CLASS(ics); |
d07fee7e DG |
534 | int i; |
535 | ||
9ae1329e CLG |
536 | if (isc->resend) { |
537 | isc->resend(ics); | |
538 | return; | |
539 | } | |
540 | ||
d07fee7e | 541 | for (i = 0; i < ics->nr_irqs; i++) { |
d07fee7e | 542 | /* FIXME: filter by server#? */ |
4af88944 | 543 | if (ics->irqs[i].flags & XICS_FLAGS_IRQ_LSI) { |
d5803c73 | 544 | ics_resend_lsi(ics, i); |
d07fee7e | 545 | } else { |
d5803c73 | 546 | ics_resend_msi(ics, i); |
d07fee7e DG |
547 | } |
548 | } | |
b5cec4c5 DG |
549 | } |
550 | ||
d5803c73 | 551 | static void ics_eoi(ICSState *ics, uint32_t nr) |
b5cec4c5 | 552 | { |
d07fee7e | 553 | int srcno = nr - ics->offset; |
c04d6cfa | 554 | ICSIRQState *irq = ics->irqs + srcno; |
d07fee7e | 555 | |
d5803c73 | 556 | trace_xics_ics_eoi(nr); |
500efa23 | 557 | |
4af88944 | 558 | if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) { |
98ca8c02 | 559 | irq->status &= ~XICS_STATUS_SENT; |
d07fee7e | 560 | } |
b5cec4c5 DG |
561 | } |
562 | ||
da2ef5b2 | 563 | static void ics_reset_irq(ICSIRQState *irq) |
c04d6cfa | 564 | { |
da2ef5b2 DG |
565 | irq->priority = 0xff; |
566 | irq->saved_priority = 0xff; | |
567 | } | |
a7e519a8 | 568 | |
da2ef5b2 DG |
569 | static void ics_reset(DeviceState *dev) |
570 | { | |
642e9271 | 571 | ICSState *ics = ICS(dev); |
da2ef5b2 DG |
572 | int i; |
573 | uint8_t flags[ics->nr_irqs]; | |
574 | ||
575 | for (i = 0; i < ics->nr_irqs; i++) { | |
576 | flags[i] = ics->irqs[i].flags; | |
577 | } | |
578 | ||
579 | memset(ics->irqs, 0, sizeof(ICSIRQState) * ics->nr_irqs); | |
580 | ||
581 | for (i = 0; i < ics->nr_irqs; i++) { | |
582 | ics_reset_irq(ics->irqs + i); | |
583 | ics->irqs[i].flags = flags[i]; | |
584 | } | |
f1f5b701 GK |
585 | |
586 | if (kvm_irqchip_in_kernel()) { | |
330a21e3 GK |
587 | Error *local_err = NULL; |
588 | ||
642e9271 | 589 | ics_set_kvm_state(ICS(dev), &local_err); |
330a21e3 GK |
590 | if (local_err) { |
591 | error_report_err(local_err); | |
592 | } | |
f1f5b701 | 593 | } |
eeefd43b | 594 | } |
a7e519a8 | 595 | |
da2ef5b2 | 596 | static void ics_reset_handler(void *dev) |
eeefd43b | 597 | { |
da2ef5b2 | 598 | ics_reset(dev); |
c04d6cfa AL |
599 | } |
600 | ||
642e9271 | 601 | static void ics_realize(DeviceState *dev, Error **errp) |
c04d6cfa | 602 | { |
642e9271 | 603 | ICSState *ics = ICS(dev); |
4e4169f7 | 604 | |
b015a980 | 605 | assert(ics->xics); |
4e4169f7 | 606 | |
0a647b76 CLG |
607 | if (!ics->nr_irqs) { |
608 | error_setg(errp, "Number of interrupts needs to be greater 0"); | |
609 | return; | |
4e4169f7 | 610 | } |
0a647b76 | 611 | ics->irqs = g_malloc0(ics->nr_irqs * sizeof(ICSIRQState)); |
642e9271 DG |
612 | |
613 | qemu_register_reset(ics_reset_handler, ics); | |
4e4169f7 CLG |
614 | } |
615 | ||
642e9271 | 616 | static void ics_instance_init(Object *obj) |
815049a0 | 617 | { |
642e9271 | 618 | ICSState *ics = ICS(obj); |
815049a0 CLG |
619 | |
620 | ics->offset = XICS_IRQ_BASE; | |
621 | } | |
622 | ||
642e9271 | 623 | static int ics_pre_save(void *opaque) |
c8b1846f CLG |
624 | { |
625 | ICSState *ics = opaque; | |
c8b1846f | 626 | |
d80b2ccf GK |
627 | if (kvm_irqchip_in_kernel()) { |
628 | ics_get_kvm_state(ics); | |
c8b1846f CLG |
629 | } |
630 | ||
631 | return 0; | |
632 | } | |
633 | ||
642e9271 | 634 | static int ics_post_load(void *opaque, int version_id) |
c8b1846f CLG |
635 | { |
636 | ICSState *ics = opaque; | |
c8b1846f | 637 | |
d80b2ccf | 638 | if (kvm_irqchip_in_kernel()) { |
330a21e3 GK |
639 | Error *local_err = NULL; |
640 | int ret; | |
641 | ||
642 | ret = ics_set_kvm_state(ics, &local_err); | |
643 | if (ret < 0) { | |
644 | error_report_err(local_err); | |
645 | return ret; | |
646 | } | |
c8b1846f CLG |
647 | } |
648 | ||
649 | return 0; | |
650 | } | |
651 | ||
642e9271 | 652 | static const VMStateDescription vmstate_ics_irq = { |
c8b1846f CLG |
653 | .name = "ics/irq", |
654 | .version_id = 2, | |
655 | .minimum_version_id = 1, | |
656 | .fields = (VMStateField[]) { | |
657 | VMSTATE_UINT32(server, ICSIRQState), | |
658 | VMSTATE_UINT8(priority, ICSIRQState), | |
659 | VMSTATE_UINT8(saved_priority, ICSIRQState), | |
660 | VMSTATE_UINT8(status, ICSIRQState), | |
661 | VMSTATE_UINT8(flags, ICSIRQState), | |
662 | VMSTATE_END_OF_LIST() | |
663 | }, | |
664 | }; | |
665 | ||
642e9271 | 666 | static const VMStateDescription vmstate_ics = { |
c8b1846f CLG |
667 | .name = "ics", |
668 | .version_id = 1, | |
669 | .minimum_version_id = 1, | |
642e9271 DG |
670 | .pre_save = ics_pre_save, |
671 | .post_load = ics_post_load, | |
c8b1846f CLG |
672 | .fields = (VMStateField[]) { |
673 | /* Sanity check */ | |
674 | VMSTATE_UINT32_EQUAL(nr_irqs, ICSState, NULL), | |
675 | ||
676 | VMSTATE_STRUCT_VARRAY_POINTER_UINT32(irqs, ICSState, nr_irqs, | |
642e9271 | 677 | vmstate_ics_irq, |
c8b1846f CLG |
678 | ICSIRQState), |
679 | VMSTATE_END_OF_LIST() | |
680 | }, | |
681 | }; | |
682 | ||
642e9271 | 683 | static Property ics_properties[] = { |
0a647b76 | 684 | DEFINE_PROP_UINT32("nr-irqs", ICSState, nr_irqs, 0), |
b015a980 GK |
685 | DEFINE_PROP_LINK(ICS_PROP_XICS, ICSState, xics, TYPE_XICS_FABRIC, |
686 | XICSFabric *), | |
0a647b76 CLG |
687 | DEFINE_PROP_END_OF_LIST(), |
688 | }; | |
689 | ||
642e9271 | 690 | static void ics_class_init(ObjectClass *klass, void *data) |
4e4169f7 CLG |
691 | { |
692 | DeviceClass *dc = DEVICE_CLASS(klass); | |
693 | ||
642e9271 | 694 | dc->realize = ics_realize; |
4f67d30b | 695 | device_class_set_props(dc, ics_properties); |
da2ef5b2 | 696 | dc->reset = ics_reset; |
642e9271 | 697 | dc->vmsd = &vmstate_ics; |
e6144bf9 GK |
698 | /* |
699 | * Reason: part of XICS interrupt controller, needs to be wired up, | |
700 | * e.g. by spapr_irq_init(). | |
701 | */ | |
702 | dc->user_creatable = false; | |
4e4169f7 CLG |
703 | } |
704 | ||
642e9271 DG |
705 | static const TypeInfo ics_info = { |
706 | .name = TYPE_ICS, | |
c04d6cfa AL |
707 | .parent = TYPE_DEVICE, |
708 | .instance_size = sizeof(ICSState), | |
642e9271 DG |
709 | .instance_init = ics_instance_init, |
710 | .class_init = ics_class_init, | |
d1b5682d | 711 | .class_size = sizeof(ICSStateClass), |
c04d6cfa AL |
712 | }; |
713 | ||
51b18005 CLG |
714 | static const TypeInfo xics_fabric_info = { |
715 | .name = TYPE_XICS_FABRIC, | |
716 | .parent = TYPE_INTERFACE, | |
717 | .class_size = sizeof(XICSFabricClass), | |
718 | }; | |
719 | ||
b5cec4c5 DG |
720 | /* |
721 | * Exported functions | |
722 | */ | |
b4f27d71 CLG |
723 | ICPState *xics_icp_get(XICSFabric *xi, int server) |
724 | { | |
725 | XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi); | |
726 | ||
727 | return xic->icp_get(xi, server); | |
728 | } | |
729 | ||
9c7027ba | 730 | void ics_set_irq_type(ICSState *ics, int srcno, bool lsi) |
4af88944 AK |
731 | { |
732 | assert(!(ics->irqs[srcno].flags & XICS_FLAGS_IRQ_MASK)); | |
733 | ||
734 | ics->irqs[srcno].flags |= | |
735 | lsi ? XICS_FLAGS_IRQ_LSI : XICS_FLAGS_IRQ_MSI; | |
6cead90c GK |
736 | |
737 | if (kvm_irqchip_in_kernel()) { | |
330a21e3 GK |
738 | Error *local_err = NULL; |
739 | ||
83629419 | 740 | ics_reset_irq(ics->irqs + srcno); |
330a21e3 GK |
741 | ics_set_kvm_state_one(ics, srcno, &local_err); |
742 | if (local_err) { | |
743 | error_report_err(local_err); | |
744 | } | |
6cead90c | 745 | } |
4af88944 AK |
746 | } |
747 | ||
c04d6cfa AL |
748 | static void xics_register_types(void) |
749 | { | |
642e9271 | 750 | type_register_static(&ics_info); |
c04d6cfa | 751 | type_register_static(&icp_info); |
51b18005 | 752 | type_register_static(&xics_fabric_info); |
b5cec4c5 | 753 | } |
c04d6cfa AL |
754 | |
755 | type_init(xics_register_types) |