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CommitLineData
b5cec4c5
DG
1/*
2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
3 *
4 * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
5 *
6 * Copyright (c) 2010,2011 David Gibson, IBM Corporation.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 *
26 */
27
0d75590d 28#include "qemu/osdep.h"
da34e65c 29#include "qapi/error.h"
4771d756 30#include "cpu.h"
500efa23 31#include "trace.h"
5d87e4b7 32#include "qemu/timer.h"
0d09e41a 33#include "hw/ppc/xics.h"
a27bd6c7 34#include "hw/qdev-properties.h"
9ccff2a4 35#include "qemu/error-report.h"
0b8fa32f 36#include "qemu/module.h"
5a3d7b23 37#include "qapi/visitor.h"
d6454270 38#include "migration/vmstate.h"
b1fc72f0
BH
39#include "monitor/monitor.h"
40#include "hw/intc/intc.h"
64552b6b 41#include "hw/irq.h"
0e5c7fad 42#include "sysemu/kvm.h"
71e8a915 43#include "sysemu/reset.h"
b5cec4c5 44
6449da45 45void icp_pic_print_info(ICPState *icp, Monitor *mon)
b1fc72f0 46{
b9038e78
CLG
47 int cpu_index = icp->cs ? icp->cs->cpu_index : -1;
48
49 if (!icp->output) {
50 return;
51 }
dcb556fc 52
0e5c7fad
GK
53 if (kvm_irqchip_in_kernel()) {
54 icp_synchronize_state(icp);
dcb556fc
GK
55 }
56
b9038e78
CLG
57 monitor_printf(mon, "CPU %d XIRR=%08x (%p) PP=%02x MFRR=%02x\n",
58 cpu_index, icp->xirr, icp->xirr_owner,
59 icp->pending_priority, icp->mfrr);
60}
61
6449da45 62void ics_pic_print_info(ICSState *ics, Monitor *mon)
b9038e78 63{
b1fc72f0
BH
64 uint32_t i;
65
b9038e78
CLG
66 monitor_printf(mon, "ICS %4x..%4x %p\n",
67 ics->offset, ics->offset + ics->nr_irqs - 1, ics);
b1fc72f0 68
b9038e78
CLG
69 if (!ics->irqs) {
70 return;
b1fc72f0
BH
71 }
72
d80b2ccf
GK
73 if (kvm_irqchip_in_kernel()) {
74 ics_synchronize_state(ics);
dcb556fc
GK
75 }
76
b9038e78
CLG
77 for (i = 0; i < ics->nr_irqs; i++) {
78 ICSIRQState *irq = ics->irqs + i;
b1fc72f0 79
b9038e78 80 if (!(irq->flags & XICS_FLAGS_IRQ_MASK)) {
b1fc72f0
BH
81 continue;
82 }
b9038e78
CLG
83 monitor_printf(mon, " %4x %s %02x %02x\n",
84 ics->offset + i,
85 (irq->flags & XICS_FLAGS_IRQ_LSI) ?
86 "LSI" : "MSI",
87 irq->priority, irq->status);
b1fc72f0
BH
88 }
89}
90
b5cec4c5
DG
91/*
92 * ICP: Presentation layer
93 */
94
b5cec4c5
DG
95#define XISR_MASK 0x00ffffff
96#define CPPR_MASK 0xff000000
97
8e4fba20
CLG
98#define XISR(icp) (((icp)->xirr) & XISR_MASK)
99#define CPPR(icp) (((icp)->xirr) >> 24)
b5cec4c5 100
d5803c73
DG
101static void ics_reject(ICSState *ics, uint32_t nr);
102static void ics_eoi(ICSState *ics, uint32_t nr);
b5cec4c5 103
8e4fba20 104static void icp_check_ipi(ICPState *icp)
b5cec4c5 105{
8e4fba20 106 if (XISR(icp) && (icp->pending_priority <= icp->mfrr)) {
b5cec4c5
DG
107 return;
108 }
109
8e4fba20 110 trace_xics_icp_check_ipi(icp->cs->cpu_index, icp->mfrr);
500efa23 111
8e4fba20
CLG
112 if (XISR(icp) && icp->xirr_owner) {
113 ics_reject(icp->xirr_owner, XISR(icp));
b5cec4c5
DG
114 }
115
8e4fba20
CLG
116 icp->xirr = (icp->xirr & ~XISR_MASK) | XICS_IPI;
117 icp->pending_priority = icp->mfrr;
118 icp->xirr_owner = NULL;
119 qemu_irq_raise(icp->output);
b5cec4c5
DG
120}
121
8e4fba20 122void icp_resend(ICPState *icp)
b5cec4c5 123{
8e4fba20 124 XICSFabric *xi = icp->xics;
2cd908d0 125 XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
b5cec4c5 126
8e4fba20
CLG
127 if (icp->mfrr < CPPR(icp)) {
128 icp_check_ipi(icp);
cc706a53 129 }
2cd908d0
CLG
130
131 xic->ics_resend(xi);
b5cec4c5
DG
132}
133
8e4fba20 134void icp_set_cppr(ICPState *icp, uint8_t cppr)
b5cec4c5 135{
b5cec4c5
DG
136 uint8_t old_cppr;
137 uint32_t old_xisr;
138
8e4fba20
CLG
139 old_cppr = CPPR(icp);
140 icp->xirr = (icp->xirr & ~CPPR_MASK) | (cppr << 24);
b5cec4c5
DG
141
142 if (cppr < old_cppr) {
8e4fba20
CLG
143 if (XISR(icp) && (cppr <= icp->pending_priority)) {
144 old_xisr = XISR(icp);
145 icp->xirr &= ~XISR_MASK; /* Clear XISR */
146 icp->pending_priority = 0xff;
147 qemu_irq_lower(icp->output);
148 if (icp->xirr_owner) {
149 ics_reject(icp->xirr_owner, old_xisr);
150 icp->xirr_owner = NULL;
cc706a53 151 }
b5cec4c5
DG
152 }
153 } else {
8e4fba20
CLG
154 if (!XISR(icp)) {
155 icp_resend(icp);
b5cec4c5
DG
156 }
157 }
158}
159
8e4fba20 160void icp_set_mfrr(ICPState *icp, uint8_t mfrr)
b5cec4c5 161{
8e4fba20
CLG
162 icp->mfrr = mfrr;
163 if (mfrr < CPPR(icp)) {
164 icp_check_ipi(icp);
b5cec4c5
DG
165 }
166}
167
8e4fba20 168uint32_t icp_accept(ICPState *icp)
b5cec4c5 169{
8e4fba20 170 uint32_t xirr = icp->xirr;
b5cec4c5 171
8e4fba20
CLG
172 qemu_irq_lower(icp->output);
173 icp->xirr = icp->pending_priority << 24;
174 icp->pending_priority = 0xff;
175 icp->xirr_owner = NULL;
500efa23 176
8e4fba20 177 trace_xics_icp_accept(xirr, icp->xirr);
500efa23 178
b5cec4c5
DG
179 return xirr;
180}
181
8e4fba20 182uint32_t icp_ipoll(ICPState *icp, uint32_t *mfrr)
1cbd2220
BH
183{
184 if (mfrr) {
8e4fba20 185 *mfrr = icp->mfrr;
1cbd2220 186 }
8e4fba20 187 return icp->xirr;
1cbd2220
BH
188}
189
8e4fba20 190void icp_eoi(ICPState *icp, uint32_t xirr)
b5cec4c5 191{
8e4fba20 192 XICSFabric *xi = icp->xics;
2cd908d0 193 XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
cc706a53
BH
194 ICSState *ics;
195 uint32_t irq;
b5cec4c5 196
b5cec4c5 197 /* Send EOI -> ICS */
8e4fba20
CLG
198 icp->xirr = (icp->xirr & ~CPPR_MASK) | (xirr & CPPR_MASK);
199 trace_xics_icp_eoi(icp->cs->cpu_index, xirr, icp->xirr);
cc706a53 200 irq = xirr & XISR_MASK;
2cd908d0
CLG
201
202 ics = xic->ics_get(xi, irq);
203 if (ics) {
204 ics_eoi(ics, irq);
cc706a53 205 }
8e4fba20
CLG
206 if (!XISR(icp)) {
207 icp_resend(icp);
b5cec4c5
DG
208 }
209}
210
cc706a53 211static void icp_irq(ICSState *ics, int server, int nr, uint8_t priority)
b5cec4c5 212{
8e4fba20 213 ICPState *icp = xics_icp_get(ics->xics, server);
b5cec4c5 214
500efa23
DG
215 trace_xics_icp_irq(server, nr, priority);
216
8e4fba20
CLG
217 if ((priority >= CPPR(icp))
218 || (XISR(icp) && (icp->pending_priority <= priority))) {
cc706a53 219 ics_reject(ics, nr);
b5cec4c5 220 } else {
8e4fba20
CLG
221 if (XISR(icp) && icp->xirr_owner) {
222 ics_reject(icp->xirr_owner, XISR(icp));
223 icp->xirr_owner = NULL;
b5cec4c5 224 }
8e4fba20
CLG
225 icp->xirr = (icp->xirr & ~XISR_MASK) | (nr & XISR_MASK);
226 icp->xirr_owner = ics;
227 icp->pending_priority = priority;
228 trace_xics_icp_raise(icp->xirr, icp->pending_priority);
229 qemu_irq_raise(icp->output);
b5cec4c5
DG
230 }
231}
232
0e5c7fad 233static int icp_pre_save(void *opaque)
d1b5682d 234{
8e4fba20 235 ICPState *icp = opaque;
d1b5682d 236
0e5c7fad
GK
237 if (kvm_irqchip_in_kernel()) {
238 icp_get_kvm_state(icp);
d1b5682d 239 }
44b1ff31
DDAG
240
241 return 0;
d1b5682d
AK
242}
243
0e5c7fad 244static int icp_post_load(void *opaque, int version_id)
d1b5682d 245{
8e4fba20 246 ICPState *icp = opaque;
d1b5682d 247
0e5c7fad 248 if (kvm_irqchip_in_kernel()) {
330a21e3
GK
249 Error *local_err = NULL;
250 int ret;
251
252 ret = icp_set_kvm_state(icp, &local_err);
253 if (ret < 0) {
254 error_report_err(local_err);
255 return ret;
256 }
d1b5682d
AK
257 }
258
259 return 0;
260}
261
c04d6cfa
AL
262static const VMStateDescription vmstate_icp_server = {
263 .name = "icp/server",
264 .version_id = 1,
265 .minimum_version_id = 1,
0e5c7fad
GK
266 .pre_save = icp_pre_save,
267 .post_load = icp_post_load,
3aff6c2f 268 .fields = (VMStateField[]) {
c04d6cfa
AL
269 /* Sanity check */
270 VMSTATE_UINT32(xirr, ICPState),
271 VMSTATE_UINT8(pending_priority, ICPState),
272 VMSTATE_UINT8(mfrr, ICPState),
273 VMSTATE_END_OF_LIST()
274 },
b5cec4c5
DG
275};
276
d82f3971 277static void icp_reset_handler(void *dev)
c04d6cfa
AL
278{
279 ICPState *icp = ICP(dev);
280
281 icp->xirr = 0;
282 icp->pending_priority = 0xff;
283 icp->mfrr = 0xff;
284
285 /* Make all outputs are deasserted */
286 qemu_set_irq(icp->output, 0);
c04d6cfa 287
d82f3971 288 if (kvm_irqchip_in_kernel()) {
330a21e3
GK
289 Error *local_err = NULL;
290
291 icp_set_kvm_state(ICP(dev), &local_err);
292 if (local_err) {
293 error_report_err(local_err);
294 }
d82f3971 295 }
b585395b
GK
296}
297
817bb6a4
CLG
298static void icp_realize(DeviceState *dev, Error **errp)
299{
300 ICPState *icp = ICP(dev);
9ed65663
GK
301 PowerPCCPU *cpu;
302 CPUPPCState *env;
817bb6a4
CLG
303 Object *obj;
304 Error *err = NULL;
305
ad265631 306 obj = object_property_get_link(OBJECT(dev), ICP_PROP_XICS, &err);
817bb6a4 307 if (!obj) {
4b576648
MA
308 error_propagate_prepend(errp, err,
309 "required link '" ICP_PROP_XICS
310 "' not found: ");
817bb6a4
CLG
311 return;
312 }
313
2cd908d0 314 icp->xics = XICS_FABRIC(obj);
7ea6e067 315
9ed65663
GK
316 obj = object_property_get_link(OBJECT(dev), ICP_PROP_CPU, &err);
317 if (!obj) {
4b576648
MA
318 error_propagate_prepend(errp, err,
319 "required link '" ICP_PROP_CPU
320 "' not found: ");
9ed65663
GK
321 return;
322 }
323
324 cpu = POWERPC_CPU(obj);
9ed65663
GK
325 icp->cs = CPU(obj);
326
9ed65663
GK
327 env = &cpu->env;
328 switch (PPC_INPUT(env)) {
329 case PPC_FLAGS_INPUT_POWER7:
330 icp->output = env->irq_inputs[POWER7_INPUT_INT];
331 break;
67afe775
BH
332 case PPC_FLAGS_INPUT_POWER9: /* For SPAPR xics emulation */
333 icp->output = env->irq_inputs[POWER9_INPUT_INT];
334 break;
9ed65663
GK
335
336 case PPC_FLAGS_INPUT_970:
337 icp->output = env->irq_inputs[PPC970_INPUT_INT];
338 break;
339
340 default:
341 error_setg(errp, "XICS interrupt controller does not support this CPU bus model");
342 return;
343 }
344
d9b9e6f6 345 /* Connect the presenter to the VCPU (required for CPU hotplug) */
8e6e6efe
GK
346 if (kvm_irqchip_in_kernel()) {
347 icp_kvm_realize(dev, &err);
348 if (err) {
349 error_propagate(errp, err);
350 return;
351 }
352 }
353
b585395b 354 qemu_register_reset(icp_reset_handler, dev);
c95f6161 355 vmstate_register(NULL, icp->cs->cpu_index, &vmstate_icp_server, icp);
817bb6a4
CLG
356}
357
62f94fc9
GK
358static void icp_unrealize(DeviceState *dev, Error **errp)
359{
c95f6161
GK
360 ICPState *icp = ICP(dev);
361
362 vmstate_unregister(NULL, &vmstate_icp_server, icp);
b585395b 363 qemu_unregister_reset(icp_reset_handler, dev);
62f94fc9 364}
817bb6a4 365
c04d6cfa
AL
366static void icp_class_init(ObjectClass *klass, void *data)
367{
368 DeviceClass *dc = DEVICE_CLASS(klass);
369
817bb6a4 370 dc->realize = icp_realize;
62f94fc9 371 dc->unrealize = icp_unrealize;
c04d6cfa
AL
372}
373
456df19c 374static const TypeInfo icp_info = {
c04d6cfa
AL
375 .name = TYPE_ICP,
376 .parent = TYPE_DEVICE,
377 .instance_size = sizeof(ICPState),
378 .class_init = icp_class_init,
d1b5682d 379 .class_size = sizeof(ICPStateClass),
b5cec4c5
DG
380};
381
4f7a47be
CLG
382Object *icp_create(Object *cpu, const char *type, XICSFabric *xi, Error **errp)
383{
384 Error *local_err = NULL;
385 Object *obj;
386
387 obj = object_new(type);
388 object_property_add_child(cpu, type, obj, &error_abort);
389 object_unref(obj);
390 object_property_add_const_link(obj, ICP_PROP_XICS, OBJECT(xi),
391 &error_abort);
392 object_property_add_const_link(obj, ICP_PROP_CPU, cpu, &error_abort);
393 object_property_set_bool(obj, true, "realized", &local_err);
394 if (local_err) {
395 object_unparent(obj);
396 error_propagate(errp, local_err);
397 obj = NULL;
398 }
399
400 return obj;
401}
402
c04d6cfa
AL
403/*
404 * ICS: Source layer
405 */
d5803c73 406static void ics_resend_msi(ICSState *ics, int srcno)
d07fee7e 407{
c04d6cfa 408 ICSIRQState *irq = ics->irqs + srcno;
d07fee7e
DG
409
410 /* FIXME: filter by server#? */
98ca8c02
DG
411 if (irq->status & XICS_STATUS_REJECTED) {
412 irq->status &= ~XICS_STATUS_REJECTED;
d07fee7e 413 if (irq->priority != 0xff) {
cc706a53 414 icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
d07fee7e
DG
415 }
416 }
417}
418
d5803c73 419static void ics_resend_lsi(ICSState *ics, int srcno)
d07fee7e 420{
c04d6cfa 421 ICSIRQState *irq = ics->irqs + srcno;
d07fee7e 422
98ca8c02
DG
423 if ((irq->priority != 0xff)
424 && (irq->status & XICS_STATUS_ASSERTED)
425 && !(irq->status & XICS_STATUS_SENT)) {
426 irq->status |= XICS_STATUS_SENT;
cc706a53 427 icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
d07fee7e
DG
428 }
429}
430
28976c99 431static void ics_set_irq_msi(ICSState *ics, int srcno, int val)
b5cec4c5 432{
c04d6cfa 433 ICSIRQState *irq = ics->irqs + srcno;
b5cec4c5 434
28976c99 435 trace_xics_ics_set_irq_msi(srcno, srcno + ics->offset);
500efa23 436
b5cec4c5
DG
437 if (val) {
438 if (irq->priority == 0xff) {
98ca8c02 439 irq->status |= XICS_STATUS_MASKED_PENDING;
500efa23 440 trace_xics_masked_pending();
b5cec4c5 441 } else {
cc706a53 442 icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
b5cec4c5
DG
443 }
444 }
445}
446
28976c99 447static void ics_set_irq_lsi(ICSState *ics, int srcno, int val)
b5cec4c5 448{
c04d6cfa 449 ICSIRQState *irq = ics->irqs + srcno;
b5cec4c5 450
28976c99 451 trace_xics_ics_set_irq_lsi(srcno, srcno + ics->offset);
98ca8c02
DG
452 if (val) {
453 irq->status |= XICS_STATUS_ASSERTED;
454 } else {
455 irq->status &= ~XICS_STATUS_ASSERTED;
456 }
d5803c73 457 ics_resend_lsi(ics, srcno);
b5cec4c5
DG
458}
459
28976c99 460void ics_set_irq(void *opaque, int srcno, int val)
b5cec4c5 461{
c04d6cfa 462 ICSState *ics = (ICSState *)opaque;
b5cec4c5 463
557b4567
GK
464 if (kvm_irqchip_in_kernel()) {
465 ics_kvm_set_irq(ics, srcno, val);
466 return;
467 }
468
4af88944 469 if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
28976c99 470 ics_set_irq_lsi(ics, srcno, val);
d07fee7e 471 } else {
28976c99 472 ics_set_irq_msi(ics, srcno, val);
d07fee7e
DG
473 }
474}
b5cec4c5 475
28976c99 476static void ics_write_xive_msi(ICSState *ics, int srcno)
d07fee7e 477{
c04d6cfa 478 ICSIRQState *irq = ics->irqs + srcno;
d07fee7e 479
98ca8c02
DG
480 if (!(irq->status & XICS_STATUS_MASKED_PENDING)
481 || (irq->priority == 0xff)) {
d07fee7e 482 return;
b5cec4c5 483 }
d07fee7e 484
98ca8c02 485 irq->status &= ~XICS_STATUS_MASKED_PENDING;
cc706a53 486 icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
b5cec4c5
DG
487}
488
28976c99 489static void ics_write_xive_lsi(ICSState *ics, int srcno)
b5cec4c5 490{
d5803c73 491 ics_resend_lsi(ics, srcno);
d07fee7e
DG
492}
493
28976c99
DG
494void ics_write_xive(ICSState *ics, int srcno, int server,
495 uint8_t priority, uint8_t saved_priority)
d07fee7e 496{
c04d6cfa 497 ICSIRQState *irq = ics->irqs + srcno;
b5cec4c5
DG
498
499 irq->server = server;
500 irq->priority = priority;
3fe719f4 501 irq->saved_priority = saved_priority;
b5cec4c5 502
28976c99 503 trace_xics_ics_write_xive(ics->offset + srcno, srcno, server, priority);
500efa23 504
4af88944 505 if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
28976c99 506 ics_write_xive_lsi(ics, srcno);
d07fee7e 507 } else {
28976c99 508 ics_write_xive_msi(ics, srcno);
b5cec4c5 509 }
b5cec4c5
DG
510}
511
d5803c73 512static void ics_reject(ICSState *ics, uint32_t nr)
b5cec4c5 513{
c04d6cfa 514 ICSIRQState *irq = ics->irqs + nr - ics->offset;
d07fee7e 515
d5803c73 516 trace_xics_ics_reject(nr, nr - ics->offset);
056b9775
ND
517 if (irq->flags & XICS_FLAGS_IRQ_MSI) {
518 irq->status |= XICS_STATUS_REJECTED;
519 } else if (irq->flags & XICS_FLAGS_IRQ_LSI) {
520 irq->status &= ~XICS_STATUS_SENT;
521 }
b5cec4c5
DG
522}
523
d5803c73 524void ics_resend(ICSState *ics)
b5cec4c5 525{
d07fee7e
DG
526 int i;
527
528 for (i = 0; i < ics->nr_irqs; i++) {
d07fee7e 529 /* FIXME: filter by server#? */
4af88944 530 if (ics->irqs[i].flags & XICS_FLAGS_IRQ_LSI) {
d5803c73 531 ics_resend_lsi(ics, i);
d07fee7e 532 } else {
d5803c73 533 ics_resend_msi(ics, i);
d07fee7e
DG
534 }
535 }
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DG
536}
537
d5803c73 538static void ics_eoi(ICSState *ics, uint32_t nr)
b5cec4c5 539{
d07fee7e 540 int srcno = nr - ics->offset;
c04d6cfa 541 ICSIRQState *irq = ics->irqs + srcno;
d07fee7e 542
d5803c73 543 trace_xics_ics_eoi(nr);
500efa23 544
4af88944 545 if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
98ca8c02 546 irq->status &= ~XICS_STATUS_SENT;
d07fee7e 547 }
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DG
548}
549
da2ef5b2 550static void ics_reset_irq(ICSIRQState *irq)
c04d6cfa 551{
da2ef5b2
DG
552 irq->priority = 0xff;
553 irq->saved_priority = 0xff;
554}
a7e519a8 555
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DG
556static void ics_reset(DeviceState *dev)
557{
642e9271 558 ICSState *ics = ICS(dev);
da2ef5b2
DG
559 int i;
560 uint8_t flags[ics->nr_irqs];
561
562 for (i = 0; i < ics->nr_irqs; i++) {
563 flags[i] = ics->irqs[i].flags;
564 }
565
566 memset(ics->irqs, 0, sizeof(ICSIRQState) * ics->nr_irqs);
567
568 for (i = 0; i < ics->nr_irqs; i++) {
569 ics_reset_irq(ics->irqs + i);
570 ics->irqs[i].flags = flags[i];
571 }
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572
573 if (kvm_irqchip_in_kernel()) {
330a21e3
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574 Error *local_err = NULL;
575
642e9271 576 ics_set_kvm_state(ICS(dev), &local_err);
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577 if (local_err) {
578 error_report_err(local_err);
579 }
f1f5b701 580 }
eeefd43b 581}
a7e519a8 582
da2ef5b2 583static void ics_reset_handler(void *dev)
eeefd43b 584{
da2ef5b2 585 ics_reset(dev);
c04d6cfa
AL
586}
587
642e9271 588static void ics_realize(DeviceState *dev, Error **errp)
c04d6cfa 589{
642e9271 590 ICSState *ics = ICS(dev);
0a647b76 591 Error *local_err = NULL;
4e4169f7 592 Object *obj;
4e4169f7 593
642e9271 594 obj = object_property_get_link(OBJECT(dev), ICS_PROP_XICS, &local_err);
4e4169f7 595 if (!obj) {
642e9271 596 error_propagate_prepend(errp, local_err,
4b576648
MA
597 "required link '" ICS_PROP_XICS
598 "' not found: ");
4e4169f7
CLG
599 return;
600 }
b4f27d71 601 ics->xics = XICS_FABRIC(obj);
4e4169f7 602
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603 if (!ics->nr_irqs) {
604 error_setg(errp, "Number of interrupts needs to be greater 0");
605 return;
4e4169f7 606 }
0a647b76 607 ics->irqs = g_malloc0(ics->nr_irqs * sizeof(ICSIRQState));
642e9271
DG
608
609 qemu_register_reset(ics_reset_handler, ics);
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610}
611
642e9271 612static void ics_instance_init(Object *obj)
815049a0 613{
642e9271 614 ICSState *ics = ICS(obj);
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615
616 ics->offset = XICS_IRQ_BASE;
617}
618
642e9271 619static int ics_pre_save(void *opaque)
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620{
621 ICSState *ics = opaque;
c8b1846f 622
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623 if (kvm_irqchip_in_kernel()) {
624 ics_get_kvm_state(ics);
c8b1846f
CLG
625 }
626
627 return 0;
628}
629
642e9271 630static int ics_post_load(void *opaque, int version_id)
c8b1846f
CLG
631{
632 ICSState *ics = opaque;
c8b1846f 633
d80b2ccf 634 if (kvm_irqchip_in_kernel()) {
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635 Error *local_err = NULL;
636 int ret;
637
638 ret = ics_set_kvm_state(ics, &local_err);
639 if (ret < 0) {
640 error_report_err(local_err);
641 return ret;
642 }
c8b1846f
CLG
643 }
644
645 return 0;
646}
647
642e9271 648static const VMStateDescription vmstate_ics_irq = {
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649 .name = "ics/irq",
650 .version_id = 2,
651 .minimum_version_id = 1,
652 .fields = (VMStateField[]) {
653 VMSTATE_UINT32(server, ICSIRQState),
654 VMSTATE_UINT8(priority, ICSIRQState),
655 VMSTATE_UINT8(saved_priority, ICSIRQState),
656 VMSTATE_UINT8(status, ICSIRQState),
657 VMSTATE_UINT8(flags, ICSIRQState),
658 VMSTATE_END_OF_LIST()
659 },
660};
661
642e9271 662static const VMStateDescription vmstate_ics = {
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663 .name = "ics",
664 .version_id = 1,
665 .minimum_version_id = 1,
642e9271
DG
666 .pre_save = ics_pre_save,
667 .post_load = ics_post_load,
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668 .fields = (VMStateField[]) {
669 /* Sanity check */
670 VMSTATE_UINT32_EQUAL(nr_irqs, ICSState, NULL),
671
672 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(irqs, ICSState, nr_irqs,
642e9271 673 vmstate_ics_irq,
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CLG
674 ICSIRQState),
675 VMSTATE_END_OF_LIST()
676 },
677};
678
642e9271 679static Property ics_properties[] = {
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680 DEFINE_PROP_UINT32("nr-irqs", ICSState, nr_irqs, 0),
681 DEFINE_PROP_END_OF_LIST(),
682};
683
642e9271 684static void ics_class_init(ObjectClass *klass, void *data)
4e4169f7
CLG
685{
686 DeviceClass *dc = DEVICE_CLASS(klass);
687
642e9271
DG
688 dc->realize = ics_realize;
689 dc->props = ics_properties;
da2ef5b2 690 dc->reset = ics_reset;
642e9271 691 dc->vmsd = &vmstate_ics;
4e4169f7
CLG
692}
693
642e9271
DG
694static const TypeInfo ics_info = {
695 .name = TYPE_ICS,
c04d6cfa
AL
696 .parent = TYPE_DEVICE,
697 .instance_size = sizeof(ICSState),
642e9271
DG
698 .instance_init = ics_instance_init,
699 .class_init = ics_class_init,
d1b5682d 700 .class_size = sizeof(ICSStateClass),
c04d6cfa
AL
701};
702
51b18005
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703static const TypeInfo xics_fabric_info = {
704 .name = TYPE_XICS_FABRIC,
705 .parent = TYPE_INTERFACE,
706 .class_size = sizeof(XICSFabricClass),
707};
708
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709/*
710 * Exported functions
711 */
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712ICPState *xics_icp_get(XICSFabric *xi, int server)
713{
714 XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
715
716 return xic->icp_get(xi, server);
717}
718
9c7027ba 719void ics_set_irq_type(ICSState *ics, int srcno, bool lsi)
4af88944
AK
720{
721 assert(!(ics->irqs[srcno].flags & XICS_FLAGS_IRQ_MASK));
722
723 ics->irqs[srcno].flags |=
724 lsi ? XICS_FLAGS_IRQ_LSI : XICS_FLAGS_IRQ_MSI;
6cead90c
GK
725
726 if (kvm_irqchip_in_kernel()) {
330a21e3
GK
727 Error *local_err = NULL;
728
83629419 729 ics_reset_irq(ics->irqs + srcno);
330a21e3
GK
730 ics_set_kvm_state_one(ics, srcno, &local_err);
731 if (local_err) {
732 error_report_err(local_err);
733 }
6cead90c 734 }
4af88944
AK
735}
736
c04d6cfa
AL
737static void xics_register_types(void)
738{
642e9271 739 type_register_static(&ics_info);
c04d6cfa 740 type_register_static(&icp_info);
51b18005 741 type_register_static(&xics_fabric_info);
b5cec4c5 742}
c04d6cfa
AL
743
744type_init(xics_register_types)