[mirror_qemu.git] / hw / intc / xics_spapr.c

/*
 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
 *
 * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
 *
 * Copyright (c) 2010,2011 David Gibson, IBM Corporation.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 *
 */

#include "qemu/osdep.h"
#include "cpu.h"
#include "hw/hw.h"
#include "trace.h"
#include "qemu/timer.h"
#include "hw/ppc/spapr.h"
#include "hw/ppc/spapr_cpu_core.h"
#include "hw/ppc/xics.h"
#include "hw/ppc/xics_spapr.h"
#include "hw/ppc/fdt.h"
#include "qapi/visitor.h"

/*
 * Guest interfaces
 */

static bool check_emulated_xics(SpaprMachineState *spapr, const char *func)
{
    if (spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT) ||
        kvm_irqchip_in_kernel()) {
        error_report("pseries: %s must only be called for emulated XICS",
                     func);
        return false;
    }

    return true;
}

#define CHECK_EMULATED_XICS_HCALL(spapr)               \
    do {                                               \
        if (!check_emulated_xics((spapr), __func__)) { \
            return H_HARDWARE;                         \
        }                                              \
    } while (0)

static target_ulong h_cppr(PowerPCCPU *cpu, SpaprMachineState *spapr,
                           target_ulong opcode, target_ulong *args)
{
    target_ulong cppr = args[0];

    CHECK_EMULATED_XICS_HCALL(spapr);

    icp_set_cppr(spapr_cpu_state(cpu)->icp, cppr);
    return H_SUCCESS;
}

static target_ulong h_ipi(PowerPCCPU *cpu, SpaprMachineState *spapr,
                          target_ulong opcode, target_ulong *args)
{
    target_ulong mfrr = args[1];
    ICPState *icp = xics_icp_get(XICS_FABRIC(spapr), args[0]);

    CHECK_EMULATED_XICS_HCALL(spapr);

    if (!icp) {
        return H_PARAMETER;
    }

    icp_set_mfrr(icp, mfrr);
    return H_SUCCESS;
}

static target_ulong h_xirr(PowerPCCPU *cpu, SpaprMachineState *spapr,
                           target_ulong opcode, target_ulong *args)
{
    uint32_t xirr = icp_accept(spapr_cpu_state(cpu)->icp);

    CHECK_EMULATED_XICS_HCALL(spapr);

    args[0] = xirr;
    return H_SUCCESS;
}

static target_ulong h_xirr_x(PowerPCCPU *cpu, SpaprMachineState *spapr,
                             target_ulong opcode, target_ulong *args)
{
    uint32_t xirr = icp_accept(spapr_cpu_state(cpu)->icp);

    CHECK_EMULATED_XICS_HCALL(spapr);

    args[0] = xirr;
    args[1] = cpu_get_host_ticks();
    return H_SUCCESS;
}

static target_ulong h_eoi(PowerPCCPU *cpu, SpaprMachineState *spapr,
                          target_ulong opcode, target_ulong *args)
{
    target_ulong xirr = args[0];

    CHECK_EMULATED_XICS_HCALL(spapr);

    icp_eoi(spapr_cpu_state(cpu)->icp, xirr);
    return H_SUCCESS;
}

static target_ulong h_ipoll(PowerPCCPU *cpu, SpaprMachineState *spapr,
                            target_ulong opcode, target_ulong *args)
{
    ICPState *icp = xics_icp_get(XICS_FABRIC(spapr), args[0]);
    uint32_t mfrr;
    uint32_t xirr;

    CHECK_EMULATED_XICS_HCALL(spapr);

    if (!icp) {
        return H_PARAMETER;
    }

    xirr = icp_ipoll(icp, &mfrr);

    args[0] = xirr;
    args[1] = mfrr;

    return H_SUCCESS;
}

#define CHECK_EMULATED_XICS_RTAS(spapr, rets)          \
    do {                                               \
        if (!check_emulated_xics((spapr), __func__)) { \
            rtas_st((rets), 0, RTAS_OUT_HW_ERROR);     \
            return;                                    \
        }                                              \
    } while (0)

static void rtas_set_xive(PowerPCCPU *cpu, SpaprMachineState *spapr,
                          uint32_t token,
                          uint32_t nargs, target_ulong args,
                          uint32_t nret, target_ulong rets)
{
    ICSState *ics = spapr->ics;
    uint32_t nr, srcno, server, priority;

    CHECK_EMULATED_XICS_RTAS(spapr, rets);

    if ((nargs != 3) || (nret != 1)) {
        rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
        return;
    }
    if (!ics) {
        rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
        return;
    }

    nr = rtas_ld(args, 0);
    server = rtas_ld(args, 1);
    priority = rtas_ld(args, 2);

    if (!ics_valid_irq(ics, nr) || !xics_icp_get(XICS_FABRIC(spapr), server)
        || (priority > 0xff)) {
        rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
        return;
    }

    srcno = nr - ics->offset;
    ics_simple_write_xive(ics, srcno, server, priority, priority);

    rtas_st(rets, 0, RTAS_OUT_SUCCESS);
}

static void rtas_get_xive(PowerPCCPU *cpu, SpaprMachineState *spapr,
                          uint32_t token,
                          uint32_t nargs, target_ulong args,
                          uint32_t nret, target_ulong rets)
{
    ICSState *ics = spapr->ics;
    uint32_t nr, srcno;

    CHECK_EMULATED_XICS_RTAS(spapr, rets);

    if ((nargs != 1) || (nret != 3)) {
        rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
        return;
    }
    if (!ics) {
        rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
        return;
    }

    nr = rtas_ld(args, 0);

    if (!ics_valid_irq(ics, nr)) {
        rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
        return;
    }

    rtas_st(rets, 0, RTAS_OUT_SUCCESS);
    srcno = nr - ics->offset;
    rtas_st(rets, 1, ics->irqs[srcno].server);
    rtas_st(rets, 2, ics->irqs[srcno].priority);
}

static void rtas_int_off(PowerPCCPU *cpu, SpaprMachineState *spapr,
                         uint32_t token,
                         uint32_t nargs, target_ulong args,
                         uint32_t nret, target_ulong rets)
{
    ICSState *ics = spapr->ics;
    uint32_t nr, srcno;

    CHECK_EMULATED_XICS_RTAS(spapr, rets);

    if ((nargs != 1) || (nret != 1)) {
        rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
        return;
    }
    if (!ics) {
        rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
        return;
    }

    nr = rtas_ld(args, 0);

    if (!ics_valid_irq(ics, nr)) {
        rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
        return;
    }

    srcno = nr - ics->offset;
    ics_simple_write_xive(ics, srcno, ics->irqs[srcno].server, 0xff,
                          ics->irqs[srcno].priority);

    rtas_st(rets, 0, RTAS_OUT_SUCCESS);
}

static void rtas_int_on(PowerPCCPU *cpu, SpaprMachineState *spapr,
                        uint32_t token,
                        uint32_t nargs, target_ulong args,
                        uint32_t nret, target_ulong rets)
{
    ICSState *ics = spapr->ics;
    uint32_t nr, srcno;

    CHECK_EMULATED_XICS_RTAS(spapr, rets);

    if ((nargs != 1) || (nret != 1)) {
        rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
        return;
    }
    if (!ics) {
        rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
        return;
    }

    nr = rtas_ld(args, 0);

    if (!ics_valid_irq(ics, nr)) {
        rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
        return;
    }

    srcno = nr - ics->offset;
    ics_simple_write_xive(ics, srcno, ics->irqs[srcno].server,
                          ics->irqs[srcno].saved_priority,
                          ics->irqs[srcno].saved_priority);

    rtas_st(rets, 0, RTAS_OUT_SUCCESS);
}

void xics_spapr_init(SpaprMachineState *spapr)
{
    spapr_rtas_register(RTAS_IBM_SET_XIVE, "ibm,set-xive", rtas_set_xive);
    spapr_rtas_register(RTAS_IBM_GET_XIVE, "ibm,get-xive", rtas_get_xive);
    spapr_rtas_register(RTAS_IBM_INT_OFF, "ibm,int-off", rtas_int_off);
    spapr_rtas_register(RTAS_IBM_INT_ON, "ibm,int-on", rtas_int_on);

    spapr_register_hypercall(H_CPPR, h_cppr);
    spapr_register_hypercall(H_IPI, h_ipi);
    spapr_register_hypercall(H_XIRR, h_xirr);
    spapr_register_hypercall(H_XIRR_X, h_xirr_x);
    spapr_register_hypercall(H_EOI, h_eoi);
    spapr_register_hypercall(H_IPOLL, h_ipoll);
}

void spapr_dt_xics(SpaprMachineState *spapr, uint32_t nr_servers, void *fdt,
                   uint32_t phandle)
{
    uint32_t interrupt_server_ranges_prop[] = {
        0, cpu_to_be32(nr_servers),
    };
    int node;

    _FDT(node = fdt_add_subnode(fdt, 0, XICS_NODENAME));

    _FDT(fdt_setprop_string(fdt, node, "device_type",
                            "PowerPC-External-Interrupt-Presentation"));
    _FDT(fdt_setprop_string(fdt, node, "compatible", "IBM,ppc-xicp"));
    _FDT(fdt_setprop(fdt, node, "interrupt-controller", NULL, 0));
    _FDT(fdt_setprop(fdt, node, "ibm,interrupt-server-ranges",
                     interrupt_server_ranges_prop,
                     sizeof(interrupt_server_ranges_prop)));
    _FDT(fdt_setprop_cell(fdt, node, "#interrupt-cells", 2));
    _FDT(fdt_setprop_cell(fdt, node, "linux,phandle", phandle));
    _FDT(fdt_setprop_cell(fdt, node, "phandle", phandle));
}
Commit	Line	Data
9c7027ba BH	1	/*
	2	* QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
	3	*
	4	* PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
	5	*
	6	* Copyright (c) 2010,2011 David Gibson, IBM Corporation.
	7	*
	8	* Permission is hereby granted, free of charge, to any person obtaining a copy
	9	* of this software and associated documentation files (the "Software"), to deal
	10	* in the Software without restriction, including without limitation the rights
	11	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	12	* copies of the Software, and to permit persons to whom the Software is
	13	* furnished to do so, subject to the following conditions:
	14	*
	15	* The above copyright notice and this permission notice shall be included in
	16	* all copies or substantial portions of the Software.
	17	*
	18	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	19	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	20	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	21	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	22	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	23	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	24	* THE SOFTWARE.
	25	*
	26	*/
	27
	28	#include "qemu/osdep.h"
	29	#include "cpu.h"
	30	#include "hw/hw.h"
	31	#include "trace.h"
	32	#include "qemu/timer.h"
	33	#include "hw/ppc/spapr.h"
a28b9a5a	34	#include "hw/ppc/spapr_cpu_core.h"
9c7027ba	35	#include "hw/ppc/xics.h"
a51d5afc	36	#include "hw/ppc/xics_spapr.h"
9b9a1908	37	#include "hw/ppc/fdt.h"
9c7027ba	38	#include "qapi/visitor.h"
9c7027ba BH	39
	40	/*
	41	* Guest interfaces
	42	*/
	43
25c79a30	44	static bool check_emulated_xics(SpaprMachineState spapr, const char func)
d9715d67	45	{
25c79a30 GK	46	if (spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT) \|\|
	47	kvm_irqchip_in_kernel()) {
	48	error_report("pseries: %s must only be called for emulated XICS",
d9715d67	49	func);
25c79a30	50	return false;
d9715d67 GK	51	}
d9715d67 GK	52
25c79a30	53	return true;
d9715d67 GK	54	}
d9715d67 GK	55
25c79a30 GK	56	#define CHECK_EMULATED_XICS_HCALL(spapr) \
	57	do { \
	58	if (!check_emulated_xics((spapr), __func__)) { \
	59	return H_HARDWARE; \
	60	} \
d9715d67 GK	61	} while (0)
d9715d67 GK	62
ce2918cb	63	static target_ulong h_cppr(PowerPCCPU cpu, SpaprMachineState spapr,
9c7027ba BH	64	target_ulong opcode, target_ulong *args)
9c7027ba BH	65	{
9c7027ba BH	66	target_ulong cppr = args[0];
9c7027ba BH	67
25c79a30	68	CHECK_EMULATED_XICS_HCALL(spapr);
d9715d67	69
a28b9a5a	70	icp_set_cppr(spapr_cpu_state(cpu)->icp, cppr);
9c7027ba BH	71	return H_SUCCESS;
	72	}
	73
ce2918cb	74	static target_ulong h_ipi(PowerPCCPU cpu, SpaprMachineState spapr,
9c7027ba BH	75	target_ulong opcode, target_ulong *args)
9c7027ba BH	76	{
9c7027ba	77	target_ulong mfrr = args[1];
06747ba6	78	ICPState *icp = xics_icp_get(XICS_FABRIC(spapr), args[0]);
9c7027ba	79
25c79a30	80	CHECK_EMULATED_XICS_HCALL(spapr);
d9715d67	81
b4f27d71	82	if (!icp) {
9c7027ba BH	83	return H_PARAMETER;
	84	}
	85
b4f27d71	86	icp_set_mfrr(icp, mfrr);
9c7027ba BH	87	return H_SUCCESS;
	88	}
	89
ce2918cb	90	static target_ulong h_xirr(PowerPCCPU cpu, SpaprMachineState spapr,
9c7027ba BH	91	target_ulong opcode, target_ulong *args)
9c7027ba BH	92	{
a28b9a5a	93	uint32_t xirr = icp_accept(spapr_cpu_state(cpu)->icp);
9c7027ba	94
25c79a30	95	CHECK_EMULATED_XICS_HCALL(spapr);
d9715d67	96
9c7027ba BH	97	args[0] = xirr;
	98	return H_SUCCESS;
	99	}
	100
ce2918cb	101	static target_ulong h_xirr_x(PowerPCCPU cpu, SpaprMachineState spapr,
9c7027ba BH	102	target_ulong opcode, target_ulong *args)
9c7027ba BH	103	{
a28b9a5a	104	uint32_t xirr = icp_accept(spapr_cpu_state(cpu)->icp);
9c7027ba	105
25c79a30	106	CHECK_EMULATED_XICS_HCALL(spapr);
d9715d67	107
9c7027ba BH	108	args[0] = xirr;
	109	args[1] = cpu_get_host_ticks();
	110	return H_SUCCESS;
	111	}
	112
ce2918cb	113	static target_ulong h_eoi(PowerPCCPU cpu, SpaprMachineState spapr,
9c7027ba BH	114	target_ulong opcode, target_ulong *args)
9c7027ba BH	115	{
9c7027ba BH	116	target_ulong xirr = args[0];
9c7027ba BH	117
25c79a30	118	CHECK_EMULATED_XICS_HCALL(spapr);
d9715d67	119
a28b9a5a	120	icp_eoi(spapr_cpu_state(cpu)->icp, xirr);
9c7027ba BH	121	return H_SUCCESS;
	122	}
	123
ce2918cb	124	static target_ulong h_ipoll(PowerPCCPU cpu, SpaprMachineState spapr,
9c7027ba BH	125	target_ulong opcode, target_ulong *args)
9c7027ba BH	126	{
ebc184be	127	ICPState *icp = xics_icp_get(XICS_FABRIC(spapr), args[0]);
1cbd2220	128	uint32_t mfrr;
ebc184be BH	129	uint32_t xirr;
ebc184be BH	130
25c79a30	131	CHECK_EMULATED_XICS_HCALL(spapr);
d9715d67	132
ebc184be BH	133	if (!icp) {
	134	return H_PARAMETER;
	135	}
	136
	137	xirr = icp_ipoll(icp, &mfrr);
9c7027ba	138
1cbd2220 BH	139	args[0] = xirr;
1cbd2220 BH	140	args[1] = mfrr;
9c7027ba BH	141
	142	return H_SUCCESS;
	143	}
	144
25c79a30 GK	145	#define CHECK_EMULATED_XICS_RTAS(spapr, rets) \
	146	do { \
	147	if (!check_emulated_xics((spapr), __func__)) { \
	148	rtas_st((rets), 0, RTAS_OUT_HW_ERROR); \
	149	return; \
	150	} \
d9715d67 GK	151	} while (0)
d9715d67 GK	152
ce2918cb	153	static void rtas_set_xive(PowerPCCPU cpu, SpaprMachineState spapr,
9c7027ba BH	154	uint32_t token,
	155	uint32_t nargs, target_ulong args,
	156	uint32_t nret, target_ulong rets)
	157	{
681bfade	158	ICSState *ics = spapr->ics;
d4d7a59a	159	uint32_t nr, srcno, server, priority;
9c7027ba	160
25c79a30	161	CHECK_EMULATED_XICS_RTAS(spapr, rets);
d9715d67	162
9c7027ba BH	163	if ((nargs != 3) \|\| (nret != 1)) {
	164	rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
	165	return;
	166	}
cc706a53 BH	167	if (!ics) {
	168	rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
	169	return;
	170	}
9c7027ba BH	171
9c7027ba BH	172	nr = rtas_ld(args, 0);
06747ba6	173	server = rtas_ld(args, 1);
9c7027ba BH	174	priority = rtas_ld(args, 2);
9c7027ba BH	175
b4f27d71	176	if (!ics_valid_irq(ics, nr) \|\| !xics_icp_get(XICS_FABRIC(spapr), server)
9c7027ba BH	177	\|\| (priority > 0xff)) {
	178	rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
	179	return;
	180	}
	181
d4d7a59a BH	182	srcno = nr - ics->offset;
d4d7a59a BH	183	ics_simple_write_xive(ics, srcno, server, priority, priority);
9c7027ba BH	184
	185	rtas_st(rets, 0, RTAS_OUT_SUCCESS);
	186	}
	187
ce2918cb	188	static void rtas_get_xive(PowerPCCPU cpu, SpaprMachineState spapr,
9c7027ba BH	189	uint32_t token,
	190	uint32_t nargs, target_ulong args,
	191	uint32_t nret, target_ulong rets)
	192	{
681bfade	193	ICSState *ics = spapr->ics;
d4d7a59a	194	uint32_t nr, srcno;
9c7027ba	195
25c79a30	196	CHECK_EMULATED_XICS_RTAS(spapr, rets);
d9715d67	197
9c7027ba BH	198	if ((nargs != 1) \|\| (nret != 3)) {
	199	rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
	200	return;
	201	}
cc706a53 BH	202	if (!ics) {
	203	rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
	204	return;
	205	}
9c7027ba BH	206
	207	nr = rtas_ld(args, 0);
	208
	209	if (!ics_valid_irq(ics, nr)) {
	210	rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
	211	return;
	212	}
	213
	214	rtas_st(rets, 0, RTAS_OUT_SUCCESS);
d4d7a59a BH	215	srcno = nr - ics->offset;
	216	rtas_st(rets, 1, ics->irqs[srcno].server);
	217	rtas_st(rets, 2, ics->irqs[srcno].priority);
9c7027ba BH	218	}
9c7027ba BH	219
ce2918cb	220	static void rtas_int_off(PowerPCCPU cpu, SpaprMachineState spapr,
9c7027ba BH	221	uint32_t token,
	222	uint32_t nargs, target_ulong args,
	223	uint32_t nret, target_ulong rets)
	224	{
681bfade	225	ICSState *ics = spapr->ics;
d4d7a59a	226	uint32_t nr, srcno;
9c7027ba	227
25c79a30	228	CHECK_EMULATED_XICS_RTAS(spapr, rets);
d9715d67	229
9c7027ba BH	230	if ((nargs != 1) \|\| (nret != 1)) {
	231	rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
	232	return;
	233	}
cc706a53 BH	234	if (!ics) {
	235	rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
	236	return;
	237	}
9c7027ba BH	238
	239	nr = rtas_ld(args, 0);
	240
	241	if (!ics_valid_irq(ics, nr)) {
	242	rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
	243	return;
	244	}
	245
d4d7a59a BH	246	srcno = nr - ics->offset;
	247	ics_simple_write_xive(ics, srcno, ics->irqs[srcno].server, 0xff,
	248	ics->irqs[srcno].priority);
9c7027ba BH	249
	250	rtas_st(rets, 0, RTAS_OUT_SUCCESS);
	251	}
	252
ce2918cb	253	static void rtas_int_on(PowerPCCPU cpu, SpaprMachineState spapr,
9c7027ba BH	254	uint32_t token,
	255	uint32_t nargs, target_ulong args,
	256	uint32_t nret, target_ulong rets)
	257	{
681bfade	258	ICSState *ics = spapr->ics;
d4d7a59a	259	uint32_t nr, srcno;
9c7027ba	260
25c79a30	261	CHECK_EMULATED_XICS_RTAS(spapr, rets);
d9715d67	262
9c7027ba BH	263	if ((nargs != 1) \|\| (nret != 1)) {
	264	rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
	265	return;
	266	}
cc706a53 BH	267	if (!ics) {
	268	rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
	269	return;
	270	}
9c7027ba BH	271
	272	nr = rtas_ld(args, 0);
	273
	274	if (!ics_valid_irq(ics, nr)) {
	275	rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
	276	return;
	277	}
	278
d4d7a59a BH	279	srcno = nr - ics->offset;
	280	ics_simple_write_xive(ics, srcno, ics->irqs[srcno].server,
	281	ics->irqs[srcno].saved_priority,
	282	ics->irqs[srcno].saved_priority);
9c7027ba BH	283
	284	rtas_st(rets, 0, RTAS_OUT_SUCCESS);
	285	}
	286
ce2918cb	287	void xics_spapr_init(SpaprMachineState *spapr)
9c7027ba	288	{
9c7027ba BH	289	spapr_rtas_register(RTAS_IBM_SET_XIVE, "ibm,set-xive", rtas_set_xive);
	290	spapr_rtas_register(RTAS_IBM_GET_XIVE, "ibm,get-xive", rtas_get_xive);
	291	spapr_rtas_register(RTAS_IBM_INT_OFF, "ibm,int-off", rtas_int_off);
	292	spapr_rtas_register(RTAS_IBM_INT_ON, "ibm,int-on", rtas_int_on);
	293
	294	spapr_register_hypercall(H_CPPR, h_cppr);
	295	spapr_register_hypercall(H_IPI, h_ipi);
	296	spapr_register_hypercall(H_XIRR, h_xirr);
	297	spapr_register_hypercall(H_XIRR_X, h_xirr_x);
	298	spapr_register_hypercall(H_EOI, h_eoi);
	299	spapr_register_hypercall(H_IPOLL, h_ipoll);
9c7027ba BH	300	}
9c7027ba BH	301
ce2918cb	302	void spapr_dt_xics(SpaprMachineState spapr, uint32_t nr_servers, void fdt,
6e21de4a	303	uint32_t phandle)
9b9a1908 DG	304	{
9b9a1908 DG	305	uint32_t interrupt_server_ranges_prop[] = {
b0ec3129	306	0, cpu_to_be32(nr_servers),
9b9a1908 DG	307	};
	308	int node;
	309
743ed566	310	_FDT(node = fdt_add_subnode(fdt, 0, XICS_NODENAME));
9b9a1908 DG	311
	312	_FDT(fdt_setprop_string(fdt, node, "device_type",
	313	"PowerPC-External-Interrupt-Presentation"));
	314	_FDT(fdt_setprop_string(fdt, node, "compatible", "IBM,ppc-xicp"));
	315	_FDT(fdt_setprop(fdt, node, "interrupt-controller", NULL, 0));
	316	_FDT(fdt_setprop(fdt, node, "ibm,interrupt-server-ranges",
	317	interrupt_server_ranges_prop,
	318	sizeof(interrupt_server_ranges_prop)));
	319	_FDT(fdt_setprop_cell(fdt, node, "#interrupt-cells", 2));
	320	_FDT(fdt_setprop_cell(fdt, node, "linux,phandle", phandle));
	321	_FDT(fdt_setprop_cell(fdt, node, "phandle", phandle));
	322	}