[mirror_qemu.git] / hw / intc / xics_spapr.c

/*
 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
 *
 * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
 *
 * Copyright (c) 2010,2011 David Gibson, IBM Corporation.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 *
 */

#include "qemu/osdep.h"
#include "cpu.h"
#include "hw/hw.h"
#include "trace.h"
#include "qemu/timer.h"
#include "hw/ppc/spapr.h"
#include "hw/ppc/spapr_cpu_core.h"
#include "hw/ppc/xics.h"
#include "hw/ppc/xics_spapr.h"
#include "hw/ppc/fdt.h"
#include "qapi/visitor.h"

/*
 * Guest interfaces
 */

static target_ulong h_cppr(PowerPCCPU *cpu, SpaprMachineState *spapr,
                           target_ulong opcode, target_ulong *args)
{
    target_ulong cppr = args[0];

    icp_set_cppr(spapr_cpu_state(cpu)->icp, cppr);
    return H_SUCCESS;
}

static target_ulong h_ipi(PowerPCCPU *cpu, SpaprMachineState *spapr,
                          target_ulong opcode, target_ulong *args)
{
    target_ulong mfrr = args[1];
    ICPState *icp = xics_icp_get(XICS_FABRIC(spapr), args[0]);

    if (!icp) {
        return H_PARAMETER;
    }

    icp_set_mfrr(icp, mfrr);
    return H_SUCCESS;
}

static target_ulong h_xirr(PowerPCCPU *cpu, SpaprMachineState *spapr,
                           target_ulong opcode, target_ulong *args)
{
    uint32_t xirr = icp_accept(spapr_cpu_state(cpu)->icp);

    args[0] = xirr;
    return H_SUCCESS;
}

static target_ulong h_xirr_x(PowerPCCPU *cpu, SpaprMachineState *spapr,
                             target_ulong opcode, target_ulong *args)
{
    uint32_t xirr = icp_accept(spapr_cpu_state(cpu)->icp);

    args[0] = xirr;
    args[1] = cpu_get_host_ticks();
    return H_SUCCESS;
}

static target_ulong h_eoi(PowerPCCPU *cpu, SpaprMachineState *spapr,
                          target_ulong opcode, target_ulong *args)
{
    target_ulong xirr = args[0];

    icp_eoi(spapr_cpu_state(cpu)->icp, xirr);
    return H_SUCCESS;
}

static target_ulong h_ipoll(PowerPCCPU *cpu, SpaprMachineState *spapr,
                            target_ulong opcode, target_ulong *args)
{
    ICPState *icp = xics_icp_get(XICS_FABRIC(spapr), args[0]);
    uint32_t mfrr;
    uint32_t xirr;

    if (!icp) {
        return H_PARAMETER;
    }

    xirr = icp_ipoll(icp, &mfrr);

    args[0] = xirr;
    args[1] = mfrr;

    return H_SUCCESS;
}

static void rtas_set_xive(PowerPCCPU *cpu, SpaprMachineState *spapr,
                          uint32_t token,
                          uint32_t nargs, target_ulong args,
                          uint32_t nret, target_ulong rets)
{
    ICSState *ics = spapr->ics;
    uint32_t nr, srcno, server, priority;

    if ((nargs != 3) || (nret != 1)) {
        rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
        return;
    }
    if (!ics) {
        rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
        return;
    }

    nr = rtas_ld(args, 0);
    server = rtas_ld(args, 1);
    priority = rtas_ld(args, 2);

    if (!ics_valid_irq(ics, nr) || !xics_icp_get(XICS_FABRIC(spapr), server)
        || (priority > 0xff)) {
        rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
        return;
    }

    srcno = nr - ics->offset;
    ics_simple_write_xive(ics, srcno, server, priority, priority);

    rtas_st(rets, 0, RTAS_OUT_SUCCESS);
}

static void rtas_get_xive(PowerPCCPU *cpu, SpaprMachineState *spapr,
                          uint32_t token,
                          uint32_t nargs, target_ulong args,
                          uint32_t nret, target_ulong rets)
{
    ICSState *ics = spapr->ics;
    uint32_t nr, srcno;

    if ((nargs != 1) || (nret != 3)) {
        rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
        return;
    }
    if (!ics) {
        rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
        return;
    }

    nr = rtas_ld(args, 0);

    if (!ics_valid_irq(ics, nr)) {
        rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
        return;
    }

    rtas_st(rets, 0, RTAS_OUT_SUCCESS);
    srcno = nr - ics->offset;
    rtas_st(rets, 1, ics->irqs[srcno].server);
    rtas_st(rets, 2, ics->irqs[srcno].priority);
}

static void rtas_int_off(PowerPCCPU *cpu, SpaprMachineState *spapr,
                         uint32_t token,
                         uint32_t nargs, target_ulong args,
                         uint32_t nret, target_ulong rets)
{
    ICSState *ics = spapr->ics;
    uint32_t nr, srcno;

    if ((nargs != 1) || (nret != 1)) {
        rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
        return;
    }
    if (!ics) {
        rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
        return;
    }

    nr = rtas_ld(args, 0);

    if (!ics_valid_irq(ics, nr)) {
        rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
        return;
    }

    srcno = nr - ics->offset;
    ics_simple_write_xive(ics, srcno, ics->irqs[srcno].server, 0xff,
                          ics->irqs[srcno].priority);

    rtas_st(rets, 0, RTAS_OUT_SUCCESS);
}

static void rtas_int_on(PowerPCCPU *cpu, SpaprMachineState *spapr,
                        uint32_t token,
                        uint32_t nargs, target_ulong args,
                        uint32_t nret, target_ulong rets)
{
    ICSState *ics = spapr->ics;
    uint32_t nr, srcno;

    if ((nargs != 1) || (nret != 1)) {
        rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
        return;
    }
    if (!ics) {
        rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
        return;
    }

    nr = rtas_ld(args, 0);

    if (!ics_valid_irq(ics, nr)) {
        rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
        return;
    }

    srcno = nr - ics->offset;
    ics_simple_write_xive(ics, srcno, ics->irqs[srcno].server,
                          ics->irqs[srcno].saved_priority,
                          ics->irqs[srcno].saved_priority);

    rtas_st(rets, 0, RTAS_OUT_SUCCESS);
}

void xics_spapr_init(SpaprMachineState *spapr)
{
    /* Emulated mode can only be initialized once. */
    if (spapr->ics->init) {
        return;
    }

    spapr->ics->init = true;

    /* Registration of global state belongs into realize */
    spapr_rtas_register(RTAS_IBM_SET_XIVE, "ibm,set-xive", rtas_set_xive);
    spapr_rtas_register(RTAS_IBM_GET_XIVE, "ibm,get-xive", rtas_get_xive);
    spapr_rtas_register(RTAS_IBM_INT_OFF, "ibm,int-off", rtas_int_off);
    spapr_rtas_register(RTAS_IBM_INT_ON, "ibm,int-on", rtas_int_on);

    spapr_register_hypercall(H_CPPR, h_cppr);
    spapr_register_hypercall(H_IPI, h_ipi);
    spapr_register_hypercall(H_XIRR, h_xirr);
    spapr_register_hypercall(H_XIRR_X, h_xirr_x);
    spapr_register_hypercall(H_EOI, h_eoi);
    spapr_register_hypercall(H_IPOLL, h_ipoll);
}

void spapr_dt_xics(SpaprMachineState *spapr, uint32_t nr_servers, void *fdt,
                   uint32_t phandle)
{
    uint32_t interrupt_server_ranges_prop[] = {
        0, cpu_to_be32(nr_servers),
    };
    int node;

    _FDT(node = fdt_add_subnode(fdt, 0, XICS_NODENAME));

    _FDT(fdt_setprop_string(fdt, node, "device_type",
                            "PowerPC-External-Interrupt-Presentation"));
    _FDT(fdt_setprop_string(fdt, node, "compatible", "IBM,ppc-xicp"));
    _FDT(fdt_setprop(fdt, node, "interrupt-controller", NULL, 0));
    _FDT(fdt_setprop(fdt, node, "ibm,interrupt-server-ranges",
                     interrupt_server_ranges_prop,
                     sizeof(interrupt_server_ranges_prop)));
    _FDT(fdt_setprop_cell(fdt, node, "#interrupt-cells", 2));
    _FDT(fdt_setprop_cell(fdt, node, "linux,phandle", phandle));
    _FDT(fdt_setprop_cell(fdt, node, "phandle", phandle));
}
Commit	Line	Data
9c7027ba BH	1	/*
	2	* QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
	3	*
	4	* PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
	5	*
	6	* Copyright (c) 2010,2011 David Gibson, IBM Corporation.
	7	*
	8	* Permission is hereby granted, free of charge, to any person obtaining a copy
	9	* of this software and associated documentation files (the "Software"), to deal
	10	* in the Software without restriction, including without limitation the rights
	11	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	12	* copies of the Software, and to permit persons to whom the Software is
	13	* furnished to do so, subject to the following conditions:
	14	*
	15	* The above copyright notice and this permission notice shall be included in
	16	* all copies or substantial portions of the Software.
	17	*
	18	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	19	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	20	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	21	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	22	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	23	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	24	* THE SOFTWARE.
	25	*
	26	*/
	27
	28	#include "qemu/osdep.h"
	29	#include "cpu.h"
	30	#include "hw/hw.h"
	31	#include "trace.h"
	32	#include "qemu/timer.h"
	33	#include "hw/ppc/spapr.h"
a28b9a5a	34	#include "hw/ppc/spapr_cpu_core.h"
9c7027ba	35	#include "hw/ppc/xics.h"
a51d5afc	36	#include "hw/ppc/xics_spapr.h"
9b9a1908	37	#include "hw/ppc/fdt.h"
9c7027ba	38	#include "qapi/visitor.h"
9c7027ba BH	39
	40	/*
	41	* Guest interfaces
	42	*/
	43
ce2918cb	44	static target_ulong h_cppr(PowerPCCPU cpu, SpaprMachineState spapr,
9c7027ba BH	45	target_ulong opcode, target_ulong *args)
9c7027ba BH	46	{
9c7027ba BH	47	target_ulong cppr = args[0];
9c7027ba BH	48
a28b9a5a	49	icp_set_cppr(spapr_cpu_state(cpu)->icp, cppr);
9c7027ba BH	50	return H_SUCCESS;
	51	}
	52
ce2918cb	53	static target_ulong h_ipi(PowerPCCPU cpu, SpaprMachineState spapr,
9c7027ba BH	54	target_ulong opcode, target_ulong *args)
9c7027ba BH	55	{
9c7027ba	56	target_ulong mfrr = args[1];
06747ba6	57	ICPState *icp = xics_icp_get(XICS_FABRIC(spapr), args[0]);
9c7027ba	58
b4f27d71	59	if (!icp) {
9c7027ba BH	60	return H_PARAMETER;
	61	}
	62
b4f27d71	63	icp_set_mfrr(icp, mfrr);
9c7027ba BH	64	return H_SUCCESS;
	65	}
	66
ce2918cb	67	static target_ulong h_xirr(PowerPCCPU cpu, SpaprMachineState spapr,
9c7027ba BH	68	target_ulong opcode, target_ulong *args)
9c7027ba BH	69	{
a28b9a5a	70	uint32_t xirr = icp_accept(spapr_cpu_state(cpu)->icp);
9c7027ba BH	71
	72	args[0] = xirr;
	73	return H_SUCCESS;
	74	}
	75
ce2918cb	76	static target_ulong h_xirr_x(PowerPCCPU cpu, SpaprMachineState spapr,
9c7027ba BH	77	target_ulong opcode, target_ulong *args)
9c7027ba BH	78	{
a28b9a5a	79	uint32_t xirr = icp_accept(spapr_cpu_state(cpu)->icp);
9c7027ba BH	80
	81	args[0] = xirr;
	82	args[1] = cpu_get_host_ticks();
	83	return H_SUCCESS;
	84	}
	85
ce2918cb	86	static target_ulong h_eoi(PowerPCCPU cpu, SpaprMachineState spapr,
9c7027ba BH	87	target_ulong opcode, target_ulong *args)
9c7027ba BH	88	{
9c7027ba BH	89	target_ulong xirr = args[0];
9c7027ba BH	90
a28b9a5a	91	icp_eoi(spapr_cpu_state(cpu)->icp, xirr);
9c7027ba BH	92	return H_SUCCESS;
	93	}
	94
ce2918cb	95	static target_ulong h_ipoll(PowerPCCPU cpu, SpaprMachineState spapr,
9c7027ba BH	96	target_ulong opcode, target_ulong *args)
9c7027ba BH	97	{
ebc184be	98	ICPState *icp = xics_icp_get(XICS_FABRIC(spapr), args[0]);
1cbd2220	99	uint32_t mfrr;
ebc184be BH	100	uint32_t xirr;
	101
	102	if (!icp) {
	103	return H_PARAMETER;
	104	}
	105
	106	xirr = icp_ipoll(icp, &mfrr);
9c7027ba	107
1cbd2220 BH	108	args[0] = xirr;
1cbd2220 BH	109	args[1] = mfrr;
9c7027ba BH	110
	111	return H_SUCCESS;
	112	}
	113
ce2918cb	114	static void rtas_set_xive(PowerPCCPU cpu, SpaprMachineState spapr,
9c7027ba BH	115	uint32_t token,
	116	uint32_t nargs, target_ulong args,
	117	uint32_t nret, target_ulong rets)
	118	{
681bfade	119	ICSState *ics = spapr->ics;
d4d7a59a	120	uint32_t nr, srcno, server, priority;
9c7027ba BH	121
	122	if ((nargs != 3) \|\| (nret != 1)) {
	123	rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
	124	return;
	125	}
cc706a53 BH	126	if (!ics) {
	127	rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
	128	return;
	129	}
9c7027ba BH	130
9c7027ba BH	131	nr = rtas_ld(args, 0);
06747ba6	132	server = rtas_ld(args, 1);
9c7027ba BH	133	priority = rtas_ld(args, 2);
9c7027ba BH	134
b4f27d71	135	if (!ics_valid_irq(ics, nr) \|\| !xics_icp_get(XICS_FABRIC(spapr), server)
9c7027ba BH	136	\|\| (priority > 0xff)) {
	137	rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
	138	return;
	139	}
	140
d4d7a59a BH	141	srcno = nr - ics->offset;
d4d7a59a BH	142	ics_simple_write_xive(ics, srcno, server, priority, priority);
9c7027ba BH	143
	144	rtas_st(rets, 0, RTAS_OUT_SUCCESS);
	145	}
	146
ce2918cb	147	static void rtas_get_xive(PowerPCCPU cpu, SpaprMachineState spapr,
9c7027ba BH	148	uint32_t token,
	149	uint32_t nargs, target_ulong args,
	150	uint32_t nret, target_ulong rets)
	151	{
681bfade	152	ICSState *ics = spapr->ics;
d4d7a59a	153	uint32_t nr, srcno;
9c7027ba BH	154
	155	if ((nargs != 1) \|\| (nret != 3)) {
	156	rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
	157	return;
	158	}
cc706a53 BH	159	if (!ics) {
	160	rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
	161	return;
	162	}
9c7027ba BH	163
	164	nr = rtas_ld(args, 0);
	165
	166	if (!ics_valid_irq(ics, nr)) {
	167	rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
	168	return;
	169	}
	170
	171	rtas_st(rets, 0, RTAS_OUT_SUCCESS);
d4d7a59a BH	172	srcno = nr - ics->offset;
	173	rtas_st(rets, 1, ics->irqs[srcno].server);
	174	rtas_st(rets, 2, ics->irqs[srcno].priority);
9c7027ba BH	175	}
9c7027ba BH	176
ce2918cb	177	static void rtas_int_off(PowerPCCPU cpu, SpaprMachineState spapr,
9c7027ba BH	178	uint32_t token,
	179	uint32_t nargs, target_ulong args,
	180	uint32_t nret, target_ulong rets)
	181	{
681bfade	182	ICSState *ics = spapr->ics;
d4d7a59a	183	uint32_t nr, srcno;
9c7027ba BH	184
	185	if ((nargs != 1) \|\| (nret != 1)) {
	186	rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
	187	return;
	188	}
cc706a53 BH	189	if (!ics) {
	190	rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
	191	return;
	192	}
9c7027ba BH	193
	194	nr = rtas_ld(args, 0);
	195
	196	if (!ics_valid_irq(ics, nr)) {
	197	rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
	198	return;
	199	}
	200
d4d7a59a BH	201	srcno = nr - ics->offset;
	202	ics_simple_write_xive(ics, srcno, ics->irqs[srcno].server, 0xff,
	203	ics->irqs[srcno].priority);
9c7027ba BH	204
	205	rtas_st(rets, 0, RTAS_OUT_SUCCESS);
	206	}
	207
ce2918cb	208	static void rtas_int_on(PowerPCCPU cpu, SpaprMachineState spapr,
9c7027ba BH	209	uint32_t token,
	210	uint32_t nargs, target_ulong args,
	211	uint32_t nret, target_ulong rets)
	212	{
681bfade	213	ICSState *ics = spapr->ics;
d4d7a59a	214	uint32_t nr, srcno;
9c7027ba BH	215
	216	if ((nargs != 1) \|\| (nret != 1)) {
	217	rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
	218	return;
	219	}
cc706a53 BH	220	if (!ics) {
	221	rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
	222	return;
	223	}
9c7027ba BH	224
	225	nr = rtas_ld(args, 0);
	226
	227	if (!ics_valid_irq(ics, nr)) {
	228	rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
	229	return;
	230	}
	231
d4d7a59a BH	232	srcno = nr - ics->offset;
	233	ics_simple_write_xive(ics, srcno, ics->irqs[srcno].server,
	234	ics->irqs[srcno].saved_priority,
	235	ics->irqs[srcno].saved_priority);
9c7027ba BH	236
	237	rtas_st(rets, 0, RTAS_OUT_SUCCESS);
	238	}
	239
ce2918cb	240	void xics_spapr_init(SpaprMachineState *spapr)
9c7027ba	241	{
cf435df6 CLG	242	/* Emulated mode can only be initialized once. */
	243	if (spapr->ics->init) {
	244	return;
	245	}
	246
	247	spapr->ics->init = true;
	248
9c7027ba BH	249	/* Registration of global state belongs into realize */
	250	spapr_rtas_register(RTAS_IBM_SET_XIVE, "ibm,set-xive", rtas_set_xive);
	251	spapr_rtas_register(RTAS_IBM_GET_XIVE, "ibm,get-xive", rtas_get_xive);
	252	spapr_rtas_register(RTAS_IBM_INT_OFF, "ibm,int-off", rtas_int_off);
	253	spapr_rtas_register(RTAS_IBM_INT_ON, "ibm,int-on", rtas_int_on);
	254
	255	spapr_register_hypercall(H_CPPR, h_cppr);
	256	spapr_register_hypercall(H_IPI, h_ipi);
	257	spapr_register_hypercall(H_XIRR, h_xirr);
	258	spapr_register_hypercall(H_XIRR_X, h_xirr_x);
	259	spapr_register_hypercall(H_EOI, h_eoi);
	260	spapr_register_hypercall(H_IPOLL, h_ipoll);
9c7027ba BH	261	}
9c7027ba BH	262
ce2918cb	263	void spapr_dt_xics(SpaprMachineState spapr, uint32_t nr_servers, void fdt,
6e21de4a	264	uint32_t phandle)
9b9a1908 DG	265	{
9b9a1908 DG	266	uint32_t interrupt_server_ranges_prop[] = {
b0ec3129	267	0, cpu_to_be32(nr_servers),
9b9a1908 DG	268	};
	269	int node;
	270
743ed566	271	_FDT(node = fdt_add_subnode(fdt, 0, XICS_NODENAME));
9b9a1908 DG	272
	273	_FDT(fdt_setprop_string(fdt, node, "device_type",
	274	"PowerPC-External-Interrupt-Presentation"));
	275	_FDT(fdt_setprop_string(fdt, node, "compatible", "IBM,ppc-xicp"));
	276	_FDT(fdt_setprop(fdt, node, "interrupt-controller", NULL, 0));
	277	_FDT(fdt_setprop(fdt, node, "ibm,interrupt-server-ranges",
	278	interrupt_server_ranges_prop,
	279	sizeof(interrupt_server_ranges_prop)));
	280	_FDT(fdt_setprop_cell(fdt, node, "#interrupt-cells", 2));
	281	_FDT(fdt_setprop_cell(fdt, node, "linux,phandle", phandle));
	282	_FDT(fdt_setprop_cell(fdt, node, "phandle", phandle));
	283	}