[mirror_qemu.git] / hw / intc / xics_spapr.c

/*
 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
 *
 * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
 *
 * Copyright (c) 2010,2011 David Gibson, IBM Corporation.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 *
 */

#include "qemu/osdep.h"
#include "cpu.h"
#include "hw/hw.h"
#include "trace.h"
#include "qemu/timer.h"
#include "hw/ppc/spapr.h"
#include "hw/ppc/spapr_cpu_core.h"
#include "hw/ppc/xics.h"
#include "hw/ppc/xics_spapr.h"
#include "hw/ppc/fdt.h"
#include "qapi/visitor.h"

/*
 * Guest interfaces
 */

static target_ulong h_cppr(PowerPCCPU *cpu, sPAPRMachineState *spapr,
                           target_ulong opcode, target_ulong *args)
{
    target_ulong cppr = args[0];

    icp_set_cppr(spapr_cpu_state(cpu)->icp, cppr);
    return H_SUCCESS;
}

static target_ulong h_ipi(PowerPCCPU *cpu, sPAPRMachineState *spapr,
                          target_ulong opcode, target_ulong *args)
{
    target_ulong mfrr = args[1];
    ICPState *icp = xics_icp_get(XICS_FABRIC(spapr), args[0]);

    if (!icp) {
        return H_PARAMETER;
    }

    icp_set_mfrr(icp, mfrr);
    return H_SUCCESS;
}

static target_ulong h_xirr(PowerPCCPU *cpu, sPAPRMachineState *spapr,
                           target_ulong opcode, target_ulong *args)
{
    uint32_t xirr = icp_accept(spapr_cpu_state(cpu)->icp);

    args[0] = xirr;
    return H_SUCCESS;
}

static target_ulong h_xirr_x(PowerPCCPU *cpu, sPAPRMachineState *spapr,
                             target_ulong opcode, target_ulong *args)
{
    uint32_t xirr = icp_accept(spapr_cpu_state(cpu)->icp);

    args[0] = xirr;
    args[1] = cpu_get_host_ticks();
    return H_SUCCESS;
}

static target_ulong h_eoi(PowerPCCPU *cpu, sPAPRMachineState *spapr,
                          target_ulong opcode, target_ulong *args)
{
    target_ulong xirr = args[0];

    icp_eoi(spapr_cpu_state(cpu)->icp, xirr);
    return H_SUCCESS;
}

static target_ulong h_ipoll(PowerPCCPU *cpu, sPAPRMachineState *spapr,
                            target_ulong opcode, target_ulong *args)
{
    uint32_t mfrr;
    uint32_t xirr = icp_ipoll(spapr_cpu_state(cpu)->icp, &mfrr);

    args[0] = xirr;
    args[1] = mfrr;

    return H_SUCCESS;
}

static void rtas_set_xive(PowerPCCPU *cpu, sPAPRMachineState *spapr,
                          uint32_t token,
                          uint32_t nargs, target_ulong args,
                          uint32_t nret, target_ulong rets)
{
    ICSState *ics = spapr->ics;
    uint32_t nr, srcno, server, priority;

    if ((nargs != 3) || (nret != 1)) {
        rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
        return;
    }
    if (!ics) {
        rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
        return;
    }

    nr = rtas_ld(args, 0);
    server = rtas_ld(args, 1);
    priority = rtas_ld(args, 2);

    if (!ics_valid_irq(ics, nr) || !xics_icp_get(XICS_FABRIC(spapr), server)
        || (priority > 0xff)) {
        rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
        return;
    }

    srcno = nr - ics->offset;
    ics_simple_write_xive(ics, srcno, server, priority, priority);

    rtas_st(rets, 0, RTAS_OUT_SUCCESS);
}

static void rtas_get_xive(PowerPCCPU *cpu, sPAPRMachineState *spapr,
                          uint32_t token,
                          uint32_t nargs, target_ulong args,
                          uint32_t nret, target_ulong rets)
{
    ICSState *ics = spapr->ics;
    uint32_t nr, srcno;

    if ((nargs != 1) || (nret != 3)) {
        rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
        return;
    }
    if (!ics) {
        rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
        return;
    }

    nr = rtas_ld(args, 0);

    if (!ics_valid_irq(ics, nr)) {
        rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
        return;
    }

    rtas_st(rets, 0, RTAS_OUT_SUCCESS);
    srcno = nr - ics->offset;
    rtas_st(rets, 1, ics->irqs[srcno].server);
    rtas_st(rets, 2, ics->irqs[srcno].priority);
}

static void rtas_int_off(PowerPCCPU *cpu, sPAPRMachineState *spapr,
                         uint32_t token,
                         uint32_t nargs, target_ulong args,
                         uint32_t nret, target_ulong rets)
{
    ICSState *ics = spapr->ics;
    uint32_t nr, srcno;

    if ((nargs != 1) || (nret != 1)) {
        rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
        return;
    }
    if (!ics) {
        rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
        return;
    }

    nr = rtas_ld(args, 0);

    if (!ics_valid_irq(ics, nr)) {
        rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
        return;
    }

    srcno = nr - ics->offset;
    ics_simple_write_xive(ics, srcno, ics->irqs[srcno].server, 0xff,
                          ics->irqs[srcno].priority);

    rtas_st(rets, 0, RTAS_OUT_SUCCESS);
}

static void rtas_int_on(PowerPCCPU *cpu, sPAPRMachineState *spapr,
                        uint32_t token,
                        uint32_t nargs, target_ulong args,
                        uint32_t nret, target_ulong rets)
{
    ICSState *ics = spapr->ics;
    uint32_t nr, srcno;

    if ((nargs != 1) || (nret != 1)) {
        rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
        return;
    }
    if (!ics) {
        rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
        return;
    }

    nr = rtas_ld(args, 0);

    if (!ics_valid_irq(ics, nr)) {
        rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
        return;
    }

    srcno = nr - ics->offset;
    ics_simple_write_xive(ics, srcno, ics->irqs[srcno].server,
                          ics->irqs[srcno].saved_priority,
                          ics->irqs[srcno].saved_priority);

    rtas_st(rets, 0, RTAS_OUT_SUCCESS);
}

void xics_spapr_init(sPAPRMachineState *spapr)
{
    /* Registration of global state belongs into realize */
    spapr_rtas_register(RTAS_IBM_SET_XIVE, "ibm,set-xive", rtas_set_xive);
    spapr_rtas_register(RTAS_IBM_GET_XIVE, "ibm,get-xive", rtas_get_xive);
    spapr_rtas_register(RTAS_IBM_INT_OFF, "ibm,int-off", rtas_int_off);
    spapr_rtas_register(RTAS_IBM_INT_ON, "ibm,int-on", rtas_int_on);

    spapr_register_hypercall(H_CPPR, h_cppr);
    spapr_register_hypercall(H_IPI, h_ipi);
    spapr_register_hypercall(H_XIRR, h_xirr);
    spapr_register_hypercall(H_XIRR_X, h_xirr_x);
    spapr_register_hypercall(H_EOI, h_eoi);
    spapr_register_hypercall(H_IPOLL, h_ipoll);
}

void spapr_dt_xics(sPAPRMachineState *spapr, uint32_t nr_servers, void *fdt,
                   uint32_t phandle)
{
    uint32_t interrupt_server_ranges_prop[] = {
        0, cpu_to_be32(nr_servers),
    };
    int node;

    _FDT(node = fdt_add_subnode(fdt, 0, XICS_NODENAME));

    _FDT(fdt_setprop_string(fdt, node, "device_type",
                            "PowerPC-External-Interrupt-Presentation"));
    _FDT(fdt_setprop_string(fdt, node, "compatible", "IBM,ppc-xicp"));
    _FDT(fdt_setprop(fdt, node, "interrupt-controller", NULL, 0));
    _FDT(fdt_setprop(fdt, node, "ibm,interrupt-server-ranges",
                     interrupt_server_ranges_prop,
                     sizeof(interrupt_server_ranges_prop)));
    _FDT(fdt_setprop_cell(fdt, node, "#interrupt-cells", 2));
    _FDT(fdt_setprop_cell(fdt, node, "linux,phandle", phandle));
    _FDT(fdt_setprop_cell(fdt, node, "phandle", phandle));
}
Commit	Line	Data
9c7027ba BH	1	/*
	2	* QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
	3	*
	4	* PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
	5	*
	6	* Copyright (c) 2010,2011 David Gibson, IBM Corporation.
	7	*
	8	* Permission is hereby granted, free of charge, to any person obtaining a copy
	9	* of this software and associated documentation files (the "Software"), to deal
	10	* in the Software without restriction, including without limitation the rights
	11	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	12	* copies of the Software, and to permit persons to whom the Software is
	13	* furnished to do so, subject to the following conditions:
	14	*
	15	* The above copyright notice and this permission notice shall be included in
	16	* all copies or substantial portions of the Software.
	17	*
	18	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	19	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	20	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	21	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	22	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	23	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	24	* THE SOFTWARE.
	25	*
	26	*/
	27
	28	#include "qemu/osdep.h"
	29	#include "cpu.h"
	30	#include "hw/hw.h"
	31	#include "trace.h"
	32	#include "qemu/timer.h"
	33	#include "hw/ppc/spapr.h"
a28b9a5a	34	#include "hw/ppc/spapr_cpu_core.h"
9c7027ba	35	#include "hw/ppc/xics.h"
a51d5afc	36	#include "hw/ppc/xics_spapr.h"
9b9a1908	37	#include "hw/ppc/fdt.h"
9c7027ba	38	#include "qapi/visitor.h"
9c7027ba BH	39
	40	/*
	41	* Guest interfaces
	42	*/
	43
	44	static target_ulong h_cppr(PowerPCCPU cpu, sPAPRMachineState spapr,
	45	target_ulong opcode, target_ulong *args)
	46	{
9c7027ba BH	47	target_ulong cppr = args[0];
9c7027ba BH	48
a28b9a5a	49	icp_set_cppr(spapr_cpu_state(cpu)->icp, cppr);
9c7027ba BH	50	return H_SUCCESS;
	51	}
	52
	53	static target_ulong h_ipi(PowerPCCPU cpu, sPAPRMachineState spapr,
	54	target_ulong opcode, target_ulong *args)
	55	{
9c7027ba	56	target_ulong mfrr = args[1];
06747ba6	57	ICPState *icp = xics_icp_get(XICS_FABRIC(spapr), args[0]);
9c7027ba	58
b4f27d71	59	if (!icp) {
9c7027ba BH	60	return H_PARAMETER;
	61	}
	62
b4f27d71	63	icp_set_mfrr(icp, mfrr);
9c7027ba BH	64	return H_SUCCESS;
	65	}
	66
	67	static target_ulong h_xirr(PowerPCCPU cpu, sPAPRMachineState spapr,
	68	target_ulong opcode, target_ulong *args)
	69	{
a28b9a5a	70	uint32_t xirr = icp_accept(spapr_cpu_state(cpu)->icp);
9c7027ba BH	71
	72	args[0] = xirr;
	73	return H_SUCCESS;
	74	}
	75
	76	static target_ulong h_xirr_x(PowerPCCPU cpu, sPAPRMachineState spapr,
	77	target_ulong opcode, target_ulong *args)
	78	{
a28b9a5a	79	uint32_t xirr = icp_accept(spapr_cpu_state(cpu)->icp);
9c7027ba BH	80
	81	args[0] = xirr;
	82	args[1] = cpu_get_host_ticks();
	83	return H_SUCCESS;
	84	}
	85
	86	static target_ulong h_eoi(PowerPCCPU cpu, sPAPRMachineState spapr,
	87	target_ulong opcode, target_ulong *args)
	88	{
9c7027ba BH	89	target_ulong xirr = args[0];
9c7027ba BH	90
a28b9a5a	91	icp_eoi(spapr_cpu_state(cpu)->icp, xirr);
9c7027ba BH	92	return H_SUCCESS;
	93	}
	94
	95	static target_ulong h_ipoll(PowerPCCPU cpu, sPAPRMachineState spapr,
	96	target_ulong opcode, target_ulong *args)
	97	{
1cbd2220	98	uint32_t mfrr;
a28b9a5a	99	uint32_t xirr = icp_ipoll(spapr_cpu_state(cpu)->icp, &mfrr);
9c7027ba	100
1cbd2220 BH	101	args[0] = xirr;
1cbd2220 BH	102	args[1] = mfrr;
9c7027ba BH	103
	104	return H_SUCCESS;
	105	}
	106
	107	static void rtas_set_xive(PowerPCCPU cpu, sPAPRMachineState spapr,
	108	uint32_t token,
	109	uint32_t nargs, target_ulong args,
	110	uint32_t nret, target_ulong rets)
	111	{
681bfade	112	ICSState *ics = spapr->ics;
d4d7a59a	113	uint32_t nr, srcno, server, priority;
9c7027ba BH	114
	115	if ((nargs != 3) \|\| (nret != 1)) {
	116	rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
	117	return;
	118	}
cc706a53 BH	119	if (!ics) {
	120	rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
	121	return;
	122	}
9c7027ba BH	123
9c7027ba BH	124	nr = rtas_ld(args, 0);
06747ba6	125	server = rtas_ld(args, 1);
9c7027ba BH	126	priority = rtas_ld(args, 2);
9c7027ba BH	127
b4f27d71	128	if (!ics_valid_irq(ics, nr) \|\| !xics_icp_get(XICS_FABRIC(spapr), server)
9c7027ba BH	129	\|\| (priority > 0xff)) {
	130	rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
	131	return;
	132	}
	133
d4d7a59a BH	134	srcno = nr - ics->offset;
d4d7a59a BH	135	ics_simple_write_xive(ics, srcno, server, priority, priority);
9c7027ba BH	136
	137	rtas_st(rets, 0, RTAS_OUT_SUCCESS);
	138	}
	139
	140	static void rtas_get_xive(PowerPCCPU cpu, sPAPRMachineState spapr,
	141	uint32_t token,
	142	uint32_t nargs, target_ulong args,
	143	uint32_t nret, target_ulong rets)
	144	{
681bfade	145	ICSState *ics = spapr->ics;
d4d7a59a	146	uint32_t nr, srcno;
9c7027ba BH	147
	148	if ((nargs != 1) \|\| (nret != 3)) {
	149	rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
	150	return;
	151	}
cc706a53 BH	152	if (!ics) {
	153	rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
	154	return;
	155	}
9c7027ba BH	156
	157	nr = rtas_ld(args, 0);
	158
	159	if (!ics_valid_irq(ics, nr)) {
	160	rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
	161	return;
	162	}
	163
	164	rtas_st(rets, 0, RTAS_OUT_SUCCESS);
d4d7a59a BH	165	srcno = nr - ics->offset;
	166	rtas_st(rets, 1, ics->irqs[srcno].server);
	167	rtas_st(rets, 2, ics->irqs[srcno].priority);
9c7027ba BH	168	}
	169
	170	static void rtas_int_off(PowerPCCPU cpu, sPAPRMachineState spapr,
	171	uint32_t token,
	172	uint32_t nargs, target_ulong args,
	173	uint32_t nret, target_ulong rets)
	174	{
681bfade	175	ICSState *ics = spapr->ics;
d4d7a59a	176	uint32_t nr, srcno;
9c7027ba BH	177
	178	if ((nargs != 1) \|\| (nret != 1)) {
	179	rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
	180	return;
	181	}
cc706a53 BH	182	if (!ics) {
	183	rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
	184	return;
	185	}
9c7027ba BH	186
	187	nr = rtas_ld(args, 0);
	188
	189	if (!ics_valid_irq(ics, nr)) {
	190	rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
	191	return;
	192	}
	193
d4d7a59a BH	194	srcno = nr - ics->offset;
	195	ics_simple_write_xive(ics, srcno, ics->irqs[srcno].server, 0xff,
	196	ics->irqs[srcno].priority);
9c7027ba BH	197
	198	rtas_st(rets, 0, RTAS_OUT_SUCCESS);
	199	}
	200
	201	static void rtas_int_on(PowerPCCPU cpu, sPAPRMachineState spapr,
	202	uint32_t token,
	203	uint32_t nargs, target_ulong args,
	204	uint32_t nret, target_ulong rets)
	205	{
681bfade	206	ICSState *ics = spapr->ics;
d4d7a59a	207	uint32_t nr, srcno;
9c7027ba BH	208
	209	if ((nargs != 1) \|\| (nret != 1)) {
	210	rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
	211	return;
	212	}
cc706a53 BH	213	if (!ics) {
	214	rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
	215	return;
	216	}
9c7027ba BH	217
	218	nr = rtas_ld(args, 0);
	219
	220	if (!ics_valid_irq(ics, nr)) {
	221	rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
	222	return;
	223	}
	224
d4d7a59a BH	225	srcno = nr - ics->offset;
	226	ics_simple_write_xive(ics, srcno, ics->irqs[srcno].server,
	227	ics->irqs[srcno].saved_priority,
	228	ics->irqs[srcno].saved_priority);
9c7027ba BH	229
	230	rtas_st(rets, 0, RTAS_OUT_SUCCESS);
	231	}
	232
f63ebfe0	233	void xics_spapr_init(sPAPRMachineState *spapr)
9c7027ba	234	{
9c7027ba BH	235	/* Registration of global state belongs into realize */
	236	spapr_rtas_register(RTAS_IBM_SET_XIVE, "ibm,set-xive", rtas_set_xive);
	237	spapr_rtas_register(RTAS_IBM_GET_XIVE, "ibm,get-xive", rtas_get_xive);
	238	spapr_rtas_register(RTAS_IBM_INT_OFF, "ibm,int-off", rtas_int_off);
	239	spapr_rtas_register(RTAS_IBM_INT_ON, "ibm,int-on", rtas_int_on);
	240
	241	spapr_register_hypercall(H_CPPR, h_cppr);
	242	spapr_register_hypercall(H_IPI, h_ipi);
	243	spapr_register_hypercall(H_XIRR, h_xirr);
	244	spapr_register_hypercall(H_XIRR_X, h_xirr_x);
	245	spapr_register_hypercall(H_EOI, h_eoi);
	246	spapr_register_hypercall(H_IPOLL, h_ipoll);
9c7027ba BH	247	}
9c7027ba BH	248
6e21de4a CLG	249	void spapr_dt_xics(sPAPRMachineState spapr, uint32_t nr_servers, void fdt,
6e21de4a CLG	250	uint32_t phandle)
9b9a1908 DG	251	{
9b9a1908 DG	252	uint32_t interrupt_server_ranges_prop[] = {
b0ec3129	253	0, cpu_to_be32(nr_servers),
9b9a1908 DG	254	};
	255	int node;
	256
743ed566	257	_FDT(node = fdt_add_subnode(fdt, 0, XICS_NODENAME));
9b9a1908 DG	258
	259	_FDT(fdt_setprop_string(fdt, node, "device_type",
	260	"PowerPC-External-Interrupt-Presentation"));
	261	_FDT(fdt_setprop_string(fdt, node, "compatible", "IBM,ppc-xicp"));
	262	_FDT(fdt_setprop(fdt, node, "interrupt-controller", NULL, 0));
	263	_FDT(fdt_setprop(fdt, node, "ibm,interrupt-server-ranges",
	264	interrupt_server_ranges_prop,
	265	sizeof(interrupt_server_ranges_prop)));
	266	_FDT(fdt_setprop_cell(fdt, node, "#interrupt-cells", 2));
	267	_FDT(fdt_setprop_cell(fdt, node, "linux,phandle", phandle));
	268	_FDT(fdt_setprop_cell(fdt, node, "phandle", phandle));
	269	}