]>
Commit | Line | Data |
---|---|---|
b350735e AF |
1 | /* |
2 | * QEMU model of the IPI Inter Processor Interrupt block | |
3 | * | |
4 | * Copyright (c) 2014 Xilinx Inc. | |
5 | * | |
6 | * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com> | |
7 | * Written by Alistair Francis <alistair.francis@xilinx.com> | |
8 | * | |
9 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
10 | * of this software and associated documentation files (the "Software"), to deal | |
11 | * in the Software without restriction, including without limitation the rights | |
12 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
13 | * copies of the Software, and to permit persons to whom the Software is | |
14 | * furnished to do so, subject to the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice shall be included in | |
17 | * all copies or substantial portions of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
20 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
21 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
22 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
23 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
24 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
25 | * THE SOFTWARE. | |
26 | */ | |
27 | ||
28 | #include "qemu/osdep.h" | |
29 | #include "hw/sysbus.h" | |
30 | #include "hw/register.h" | |
31 | #include "qemu/bitops.h" | |
32 | #include "qemu/log.h" | |
0b8fa32f | 33 | #include "qemu/module.h" |
b350735e AF |
34 | #include "hw/intc/xlnx-zynqmp-ipi.h" |
35 | ||
36 | #ifndef XLNX_ZYNQMP_IPI_ERR_DEBUG | |
37 | #define XLNX_ZYNQMP_IPI_ERR_DEBUG 0 | |
38 | #endif | |
39 | ||
40 | #define DB_PRINT_L(lvl, fmt, args...) do {\ | |
41 | if (XLNX_ZYNQMP_IPI_ERR_DEBUG >= lvl) {\ | |
42 | qemu_log(TYPE_XLNX_ZYNQMP_IPI ": %s:" fmt, __func__, ## args);\ | |
43 | } \ | |
44 | } while (0) | |
45 | ||
46 | #define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) | |
47 | ||
48 | REG32(IPI_TRIG, 0x0) | |
49 | FIELD(IPI_TRIG, PL_3, 27, 1) | |
50 | FIELD(IPI_TRIG, PL_2, 26, 1) | |
51 | FIELD(IPI_TRIG, PL_1, 25, 1) | |
52 | FIELD(IPI_TRIG, PL_0, 24, 1) | |
53 | FIELD(IPI_TRIG, PMU_3, 19, 1) | |
54 | FIELD(IPI_TRIG, PMU_2, 18, 1) | |
55 | FIELD(IPI_TRIG, PMU_1, 17, 1) | |
56 | FIELD(IPI_TRIG, PMU_0, 16, 1) | |
57 | FIELD(IPI_TRIG, RPU_1, 9, 1) | |
58 | FIELD(IPI_TRIG, RPU_0, 8, 1) | |
59 | FIELD(IPI_TRIG, APU, 0, 1) | |
60 | REG32(IPI_OBS, 0x4) | |
61 | FIELD(IPI_OBS, PL_3, 27, 1) | |
62 | FIELD(IPI_OBS, PL_2, 26, 1) | |
63 | FIELD(IPI_OBS, PL_1, 25, 1) | |
64 | FIELD(IPI_OBS, PL_0, 24, 1) | |
65 | FIELD(IPI_OBS, PMU_3, 19, 1) | |
66 | FIELD(IPI_OBS, PMU_2, 18, 1) | |
67 | FIELD(IPI_OBS, PMU_1, 17, 1) | |
68 | FIELD(IPI_OBS, PMU_0, 16, 1) | |
69 | FIELD(IPI_OBS, RPU_1, 9, 1) | |
70 | FIELD(IPI_OBS, RPU_0, 8, 1) | |
71 | FIELD(IPI_OBS, APU, 0, 1) | |
72 | REG32(IPI_ISR, 0x10) | |
73 | FIELD(IPI_ISR, PL_3, 27, 1) | |
74 | FIELD(IPI_ISR, PL_2, 26, 1) | |
75 | FIELD(IPI_ISR, PL_1, 25, 1) | |
76 | FIELD(IPI_ISR, PL_0, 24, 1) | |
77 | FIELD(IPI_ISR, PMU_3, 19, 1) | |
78 | FIELD(IPI_ISR, PMU_2, 18, 1) | |
79 | FIELD(IPI_ISR, PMU_1, 17, 1) | |
80 | FIELD(IPI_ISR, PMU_0, 16, 1) | |
81 | FIELD(IPI_ISR, RPU_1, 9, 1) | |
82 | FIELD(IPI_ISR, RPU_0, 8, 1) | |
83 | FIELD(IPI_ISR, APU, 0, 1) | |
84 | REG32(IPI_IMR, 0x14) | |
85 | FIELD(IPI_IMR, PL_3, 27, 1) | |
86 | FIELD(IPI_IMR, PL_2, 26, 1) | |
87 | FIELD(IPI_IMR, PL_1, 25, 1) | |
88 | FIELD(IPI_IMR, PL_0, 24, 1) | |
89 | FIELD(IPI_IMR, PMU_3, 19, 1) | |
90 | FIELD(IPI_IMR, PMU_2, 18, 1) | |
91 | FIELD(IPI_IMR, PMU_1, 17, 1) | |
92 | FIELD(IPI_IMR, PMU_0, 16, 1) | |
93 | FIELD(IPI_IMR, RPU_1, 9, 1) | |
94 | FIELD(IPI_IMR, RPU_0, 8, 1) | |
95 | FIELD(IPI_IMR, APU, 0, 1) | |
96 | REG32(IPI_IER, 0x18) | |
97 | FIELD(IPI_IER, PL_3, 27, 1) | |
98 | FIELD(IPI_IER, PL_2, 26, 1) | |
99 | FIELD(IPI_IER, PL_1, 25, 1) | |
100 | FIELD(IPI_IER, PL_0, 24, 1) | |
101 | FIELD(IPI_IER, PMU_3, 19, 1) | |
102 | FIELD(IPI_IER, PMU_2, 18, 1) | |
103 | FIELD(IPI_IER, PMU_1, 17, 1) | |
104 | FIELD(IPI_IER, PMU_0, 16, 1) | |
105 | FIELD(IPI_IER, RPU_1, 9, 1) | |
106 | FIELD(IPI_IER, RPU_0, 8, 1) | |
107 | FIELD(IPI_IER, APU, 0, 1) | |
108 | REG32(IPI_IDR, 0x1c) | |
109 | FIELD(IPI_IDR, PL_3, 27, 1) | |
110 | FIELD(IPI_IDR, PL_2, 26, 1) | |
111 | FIELD(IPI_IDR, PL_1, 25, 1) | |
112 | FIELD(IPI_IDR, PL_0, 24, 1) | |
113 | FIELD(IPI_IDR, PMU_3, 19, 1) | |
114 | FIELD(IPI_IDR, PMU_2, 18, 1) | |
115 | FIELD(IPI_IDR, PMU_1, 17, 1) | |
116 | FIELD(IPI_IDR, PMU_0, 16, 1) | |
117 | FIELD(IPI_IDR, RPU_1, 9, 1) | |
118 | FIELD(IPI_IDR, RPU_0, 8, 1) | |
119 | FIELD(IPI_IDR, APU, 0, 1) | |
120 | ||
121 | /* APU | |
122 | * RPU_0 | |
123 | * RPU_1 | |
124 | * PMU_0 | |
125 | * PMU_1 | |
126 | * PMU_2 | |
127 | * PMU_3 | |
128 | * PL_0 | |
129 | * PL_1 | |
130 | * PL_2 | |
131 | * PL_3 | |
132 | */ | |
133 | int index_array[NUM_IPIS] = {0, 8, 9, 16, 17, 18, 19, 24, 25, 26, 27}; | |
134 | static const char *index_array_names[NUM_IPIS] = {"APU", "RPU_0", "RPU_1", | |
135 | "PMU_0", "PMU_1", "PMU_2", | |
136 | "PMU_3", "PL_0", "PL_1", | |
137 | "PL_2", "PL_3"}; | |
138 | ||
139 | static void xlnx_zynqmp_ipi_set_trig(XlnxZynqMPIPI *s, uint32_t val) | |
140 | { | |
141 | int i, ipi_index, ipi_mask; | |
142 | ||
143 | for (i = 0; i < NUM_IPIS; i++) { | |
144 | ipi_index = index_array[i]; | |
145 | ipi_mask = (1 << ipi_index); | |
146 | DB_PRINT("Setting %s=%d\n", index_array_names[i], | |
147 | !!(val & ipi_mask)); | |
148 | qemu_set_irq(s->irq_trig_out[i], !!(val & ipi_mask)); | |
149 | } | |
150 | } | |
151 | ||
152 | static void xlnx_zynqmp_ipi_set_obs(XlnxZynqMPIPI *s, uint32_t val) | |
153 | { | |
154 | int i, ipi_index, ipi_mask; | |
155 | ||
156 | for (i = 0; i < NUM_IPIS; i++) { | |
157 | ipi_index = index_array[i]; | |
158 | ipi_mask = (1 << ipi_index); | |
159 | DB_PRINT("Setting %s=%d\n", index_array_names[i], | |
160 | !!(val & ipi_mask)); | |
161 | qemu_set_irq(s->irq_obs_out[i], !!(val & ipi_mask)); | |
162 | } | |
163 | } | |
164 | ||
165 | static void xlnx_zynqmp_ipi_update_irq(XlnxZynqMPIPI *s) | |
166 | { | |
167 | bool pending = s->regs[R_IPI_ISR] & ~s->regs[R_IPI_IMR]; | |
168 | ||
169 | DB_PRINT("irq=%d isr=%x mask=%x\n", | |
170 | pending, s->regs[R_IPI_ISR], s->regs[R_IPI_IMR]); | |
171 | qemu_set_irq(s->irq, pending); | |
172 | } | |
173 | ||
174 | static uint64_t xlnx_zynqmp_ipi_trig_prew(RegisterInfo *reg, uint64_t val64) | |
175 | { | |
176 | XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(reg->opaque); | |
177 | ||
178 | xlnx_zynqmp_ipi_set_trig(s, val64); | |
179 | ||
180 | return val64; | |
181 | } | |
182 | ||
183 | static void xlnx_zynqmp_ipi_trig_postw(RegisterInfo *reg, uint64_t val64) | |
184 | { | |
185 | XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(reg->opaque); | |
186 | ||
187 | /* TRIG generates a pulse on the outbound signals. We use the | |
188 | * post-write callback to bring the signal back-down. | |
189 | */ | |
190 | s->regs[R_IPI_TRIG] = 0; | |
191 | ||
192 | xlnx_zynqmp_ipi_set_trig(s, 0); | |
193 | } | |
194 | ||
195 | static uint64_t xlnx_zynqmp_ipi_isr_prew(RegisterInfo *reg, uint64_t val64) | |
196 | { | |
197 | XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(reg->opaque); | |
198 | ||
199 | xlnx_zynqmp_ipi_set_obs(s, val64); | |
200 | ||
201 | return val64; | |
202 | } | |
203 | ||
204 | static void xlnx_zynqmp_ipi_isr_postw(RegisterInfo *reg, uint64_t val64) | |
205 | { | |
206 | XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(reg->opaque); | |
207 | ||
208 | xlnx_zynqmp_ipi_update_irq(s); | |
209 | } | |
210 | ||
211 | static uint64_t xlnx_zynqmp_ipi_ier_prew(RegisterInfo *reg, uint64_t val64) | |
212 | { | |
213 | XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(reg->opaque); | |
214 | uint32_t val = val64; | |
215 | ||
216 | s->regs[R_IPI_IMR] &= ~val; | |
217 | xlnx_zynqmp_ipi_update_irq(s); | |
218 | return 0; | |
219 | } | |
220 | ||
221 | static uint64_t xlnx_zynqmp_ipi_idr_prew(RegisterInfo *reg, uint64_t val64) | |
222 | { | |
223 | XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(reg->opaque); | |
224 | uint32_t val = val64; | |
225 | ||
226 | s->regs[R_IPI_IMR] |= val; | |
227 | xlnx_zynqmp_ipi_update_irq(s); | |
228 | return 0; | |
229 | } | |
230 | ||
231 | static const RegisterAccessInfo xlnx_zynqmp_ipi_regs_info[] = { | |
232 | { .name = "IPI_TRIG", .addr = A_IPI_TRIG, | |
233 | .rsvd = 0xf0f0fcfe, | |
234 | .ro = 0xf0f0fcfe, | |
235 | .pre_write = xlnx_zynqmp_ipi_trig_prew, | |
236 | .post_write = xlnx_zynqmp_ipi_trig_postw, | |
237 | },{ .name = "IPI_OBS", .addr = A_IPI_OBS, | |
238 | .rsvd = 0xf0f0fcfe, | |
239 | .ro = 0xffffffff, | |
240 | },{ .name = "IPI_ISR", .addr = A_IPI_ISR, | |
241 | .rsvd = 0xf0f0fcfe, | |
242 | .ro = 0xf0f0fcfe, | |
243 | .w1c = 0xf0f0301, | |
244 | .pre_write = xlnx_zynqmp_ipi_isr_prew, | |
245 | .post_write = xlnx_zynqmp_ipi_isr_postw, | |
246 | },{ .name = "IPI_IMR", .addr = A_IPI_IMR, | |
247 | .reset = 0xf0f0301, | |
248 | .rsvd = 0xf0f0fcfe, | |
249 | .ro = 0xffffffff, | |
250 | },{ .name = "IPI_IER", .addr = A_IPI_IER, | |
251 | .rsvd = 0xf0f0fcfe, | |
252 | .ro = 0xf0f0fcfe, | |
253 | .pre_write = xlnx_zynqmp_ipi_ier_prew, | |
254 | },{ .name = "IPI_IDR", .addr = A_IPI_IDR, | |
255 | .rsvd = 0xf0f0fcfe, | |
256 | .ro = 0xf0f0fcfe, | |
257 | .pre_write = xlnx_zynqmp_ipi_idr_prew, | |
258 | } | |
259 | }; | |
260 | ||
261 | static void xlnx_zynqmp_ipi_reset(DeviceState *dev) | |
262 | { | |
263 | XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(dev); | |
264 | int i; | |
265 | ||
266 | for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) { | |
267 | register_reset(&s->regs_info[i]); | |
268 | } | |
269 | ||
270 | xlnx_zynqmp_ipi_update_irq(s); | |
271 | } | |
272 | ||
273 | static void xlnx_zynqmp_ipi_handler(void *opaque, int n, int level) | |
274 | { | |
275 | XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(opaque); | |
276 | uint32_t val = (!!level) << n; | |
277 | ||
278 | DB_PRINT("IPI input irq[%d]=%d\n", n, level); | |
279 | ||
280 | s->regs[R_IPI_ISR] |= val; | |
281 | xlnx_zynqmp_ipi_set_obs(s, s->regs[R_IPI_ISR]); | |
282 | xlnx_zynqmp_ipi_update_irq(s); | |
283 | } | |
284 | ||
285 | static void xlnx_zynqmp_obs_handler(void *opaque, int n, int level) | |
286 | { | |
287 | XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(opaque); | |
288 | ||
289 | DB_PRINT("OBS input irq[%d]=%d\n", n, level); | |
290 | ||
291 | s->regs[R_IPI_OBS] &= ~(1ULL << n); | |
292 | s->regs[R_IPI_OBS] |= (level << n); | |
293 | } | |
294 | ||
295 | static const MemoryRegionOps xlnx_zynqmp_ipi_ops = { | |
296 | .read = register_read_memory, | |
297 | .write = register_write_memory, | |
298 | .endianness = DEVICE_LITTLE_ENDIAN, | |
299 | .valid = { | |
300 | .min_access_size = 4, | |
301 | .max_access_size = 4, | |
302 | }, | |
303 | }; | |
304 | ||
305 | static void xlnx_zynqmp_ipi_realize(DeviceState *dev, Error **errp) | |
306 | { | |
307 | qdev_init_gpio_in_named(dev, xlnx_zynqmp_ipi_handler, "IPI_INPUTS", 32); | |
308 | qdev_init_gpio_in_named(dev, xlnx_zynqmp_obs_handler, "OBS_INPUTS", 32); | |
309 | } | |
310 | ||
311 | static void xlnx_zynqmp_ipi_init(Object *obj) | |
312 | { | |
313 | XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(obj); | |
314 | DeviceState *dev = DEVICE(obj); | |
315 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | |
316 | RegisterInfoArray *reg_array; | |
317 | char *irq_name; | |
318 | int i; | |
319 | ||
320 | memory_region_init(&s->iomem, obj, TYPE_XLNX_ZYNQMP_IPI, | |
321 | R_XLNX_ZYNQMP_IPI_MAX * 4); | |
322 | reg_array = | |
323 | register_init_block32(DEVICE(obj), xlnx_zynqmp_ipi_regs_info, | |
324 | ARRAY_SIZE(xlnx_zynqmp_ipi_regs_info), | |
325 | s->regs_info, s->regs, | |
326 | &xlnx_zynqmp_ipi_ops, | |
327 | XLNX_ZYNQMP_IPI_ERR_DEBUG, | |
328 | R_XLNX_ZYNQMP_IPI_MAX * 4); | |
329 | memory_region_add_subregion(&s->iomem, | |
330 | 0x0, | |
331 | ®_array->mem); | |
332 | sysbus_init_mmio(sbd, &s->iomem); | |
333 | sysbus_init_irq(sbd, &s->irq); | |
334 | ||
335 | for (i = 0; i < NUM_IPIS; i++) { | |
336 | qdev_init_gpio_out_named(dev, &s->irq_trig_out[i], | |
337 | index_array_names[i], 1); | |
338 | ||
339 | irq_name = g_strdup_printf("OBS_%s", index_array_names[i]); | |
340 | qdev_init_gpio_out_named(dev, &s->irq_obs_out[i], | |
341 | irq_name, 1); | |
342 | g_free(irq_name); | |
343 | } | |
344 | } | |
345 | ||
346 | static const VMStateDescription vmstate_zynqmp_pmu_ipi = { | |
347 | .name = TYPE_XLNX_ZYNQMP_IPI, | |
348 | .version_id = 1, | |
349 | .minimum_version_id = 1, | |
350 | .fields = (VMStateField[]) { | |
351 | VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPIPI, R_XLNX_ZYNQMP_IPI_MAX), | |
352 | VMSTATE_END_OF_LIST(), | |
353 | } | |
354 | }; | |
355 | ||
356 | static void xlnx_zynqmp_ipi_class_init(ObjectClass *klass, void *data) | |
357 | { | |
358 | DeviceClass *dc = DEVICE_CLASS(klass); | |
359 | ||
360 | dc->reset = xlnx_zynqmp_ipi_reset; | |
361 | dc->realize = xlnx_zynqmp_ipi_realize; | |
362 | dc->vmsd = &vmstate_zynqmp_pmu_ipi; | |
363 | } | |
364 | ||
365 | static const TypeInfo xlnx_zynqmp_ipi_info = { | |
366 | .name = TYPE_XLNX_ZYNQMP_IPI, | |
367 | .parent = TYPE_SYS_BUS_DEVICE, | |
368 | .instance_size = sizeof(XlnxZynqMPIPI), | |
369 | .class_init = xlnx_zynqmp_ipi_class_init, | |
370 | .instance_init = xlnx_zynqmp_ipi_init, | |
371 | }; | |
372 | ||
373 | static void xlnx_zynqmp_ipi_register_types(void) | |
374 | { | |
375 | type_register_static(&xlnx_zynqmp_ipi_info); | |
376 | } | |
377 | ||
378 | type_init(xlnx_zynqmp_ipi_register_types) |