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qdev: Move bus properties to a separate global
[mirror_qemu.git] / hw / intel-hda.c
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d61a4ce8
GH		 1/*
2 * Copyright (C) 2010 Red Hat, Inc.
3 *
4 * written by Gerd Hoffmann <kraxel@redhat.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 or
9 * (at your option) version 3 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include "hw.h"
21#include "pci.h"
17786d52 22#include "msi.h"
d61a4ce8
GH		 23#include "qemu-timer.h"
24#include "audiodev.h"
25#include "intel-hda.h"
26#include "intel-hda-defs.h"
fa0ce55c 27#include "dma.h"
d61a4ce8
GH		 28
29/* --------------------------------------------------------------------- */
30/* hda bus */
31
3cb75a7c
PB		 32static Property hda_props[] = {
33 DEFINE_PROP_UINT32("cad", HDACodecDevice, cad, -1),
34 DEFINE_PROP_END_OF_LIST()
35};
36
d61a4ce8
GH		 37static struct BusInfo hda_codec_bus_info = {
38 .name = "HDA",
39 .size = sizeof(HDACodecBus),
3cb75a7c 40 .props = hda_props,
d61a4ce8
GH		 41};
42
43void hda_codec_bus_init(DeviceState *dev, HDACodecBus *bus,
44 hda_codec_response_func response,
45 hda_codec_xfer_func xfer)
46{
47 qbus_create_inplace(&bus->qbus, &hda_codec_bus_info, dev, NULL);
48 bus->response = response;
49 bus->xfer = xfer;
50}
51
d307af79 52static int hda_codec_dev_init(DeviceState *qdev)
d61a4ce8
GH		 53{
54 HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, qdev->parent_bus);
55 HDACodecDevice *dev = DO_UPCAST(HDACodecDevice, qdev, qdev);
dbaa7904 56 HDACodecDeviceClass *cdc = HDA_CODEC_DEVICE_GET_CLASS(dev);
d61a4ce8 57
d61a4ce8
GH		 58 if (dev->cad == -1) {
59 dev->cad = bus->next_cad;
60 }
df0db221 61 if (dev->cad >= 15) {
d61a4ce8 62 return -1;
df0db221 63 }
d61a4ce8 64 bus->next_cad = dev->cad + 1;
dbaa7904 65 return cdc->init(dev);
d61a4ce8
GH		 66}
67
dc4b9240
GH		 68static int hda_codec_dev_exit(DeviceState *qdev)
69{
70 HDACodecDevice *dev = DO_UPCAST(HDACodecDevice, qdev, qdev);
dbaa7904 71 HDACodecDeviceClass *cdc = HDA_CODEC_DEVICE_GET_CLASS(dev);
dc4b9240 72
dbaa7904
AL		 73 if (cdc->exit) {
74 cdc->exit(dev);
dc4b9240
GH		 75 }
76 return 0;
77}
78
d61a4ce8
GH		 79HDACodecDevice *hda_codec_find(HDACodecBus *bus, uint32_t cad)
80{
81 DeviceState *qdev;
82 HDACodecDevice *cdev;
83
d8bb00d6 84 QTAILQ_FOREACH(qdev, &bus->qbus.children, sibling) {
d61a4ce8
GH		 85 cdev = DO_UPCAST(HDACodecDevice, qdev, qdev);
86 if (cdev->cad == cad) {
87 return cdev;
88 }
89 }
90 return NULL;
91}
92
93void hda_codec_response(HDACodecDevice *dev, bool solicited, uint32_t response)
94{
95 HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus);
96 bus->response(dev, solicited, response);
97}
98
99bool hda_codec_xfer(HDACodecDevice *dev, uint32_t stnr, bool output,
100 uint8_t *buf, uint32_t len)
101{
102 HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus);
103 return bus->xfer(dev, stnr, output, buf, len);
104}
105
106/* --------------------------------------------------------------------- */
107/* intel hda emulation */
108
109typedef struct IntelHDAStream IntelHDAStream;
110typedef struct IntelHDAState IntelHDAState;
111typedef struct IntelHDAReg IntelHDAReg;
112
113typedef struct bpl {
114 uint64_t addr;
115 uint32_t len;
116 uint32_t flags;
117} bpl;
118
119struct IntelHDAStream {
120 /* registers */
121 uint32_t ctl;
122 uint32_t lpib;
123 uint32_t cbl;
124 uint32_t lvi;
125 uint32_t fmt;
126 uint32_t bdlp_lbase;
127 uint32_t bdlp_ubase;
128
129 /* state */
130 bpl *bpl;
131 uint32_t bentries;
132 uint32_t bsize, be, bp;
133};
134
135struct IntelHDAState {
136 PCIDevice pci;
137 const char *name;
138 HDACodecBus codecs;
139
140 /* registers */
141 uint32_t g_ctl;
142 uint32_t wake_en;
143 uint32_t state_sts;
144 uint32_t int_ctl;
145 uint32_t int_sts;
146 uint32_t wall_clk;
147
148 uint32_t corb_lbase;
149 uint32_t corb_ubase;
150 uint32_t corb_rp;
151 uint32_t corb_wp;
152 uint32_t corb_ctl;
153 uint32_t corb_sts;
154 uint32_t corb_size;
155
156 uint32_t rirb_lbase;
157 uint32_t rirb_ubase;
158 uint32_t rirb_wp;
159 uint32_t rirb_cnt;
160 uint32_t rirb_ctl;
161 uint32_t rirb_sts;
162 uint32_t rirb_size;
163
164 uint32_t dp_lbase;
165 uint32_t dp_ubase;
166
167 uint32_t icw;
168 uint32_t irr;
169 uint32_t ics;
170
171 /* streams */
172 IntelHDAStream st[8];
173
174 /* state */
234bbdf1 175 MemoryRegion mmio;
d61a4ce8
GH		 176 uint32_t rirb_count;
177 int64_t wall_base_ns;
178
179 /* debug logging */
180 const IntelHDAReg *last_reg;
181 uint32_t last_val;
182 uint32_t last_write;
183 uint32_t last_sec;
184 uint32_t repeat_count;
185
186 /* properties */
187 uint32_t debug;
17786d52 188 uint32_t msi;
d61a4ce8
GH		 189};
190
191struct IntelHDAReg {
192 const char *name; /* register name */
193 uint32_t size; /* size in bytes */
194 uint32_t reset; /* reset value */
195 uint32_t wmask; /* write mask */
196 uint32_t wclear; /* write 1 to clear bits */
197 uint32_t offset; /* location in IntelHDAState */
198 uint32_t shift; /* byte access entries for dwords */
199 uint32_t stream;
200 void (*whandler)(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old);
201 void (*rhandler)(IntelHDAState *d, const IntelHDAReg *reg);
202};
203
204static void intel_hda_reset(DeviceState *dev);
205
206/* --------------------------------------------------------------------- */
207
208static target_phys_addr_t intel_hda_addr(uint32_t lbase, uint32_t ubase)
209{
210 target_phys_addr_t addr;
211
212#if TARGET_PHYS_ADDR_BITS == 32
213 addr = lbase;
214#else
215 addr = ubase;
216 addr <<= 32;
217 addr |= lbase;
218#endif
219 return addr;
220}
221
d61a4ce8
GH		 222static void intel_hda_update_int_sts(IntelHDAState *d)
223{
224 uint32_t sts = 0;
225 uint32_t i;
226
227 /* update controller status */
228 if (d->rirb_sts & ICH6_RBSTS_IRQ) {
229 sts |= (1 << 30);
230 }
231 if (d->rirb_sts & ICH6_RBSTS_OVERRUN) {
232 sts |= (1 << 30);
233 }
af93485c 234 if (d->state_sts & d->wake_en) {
d61a4ce8
GH		 235 sts |= (1 << 30);
236 }
237
238 /* update stream status */
239 for (i = 0; i < 8; i++) {
240 /* buffer completion interrupt */
241 if (d->st[i].ctl & (1 << 26)) {
242 sts |= (1 << i);
243 }
244 }
245
246 /* update global status */
247 if (sts & d->int_ctl) {
248 sts |= (1 << 31);
249 }
250
251 d->int_sts = sts;
252}
253
254static void intel_hda_update_irq(IntelHDAState *d)
255{
17786d52 256 int msi = d->msi && msi_enabled(&d->pci);
d61a4ce8
GH		 257 int level;
258
259 intel_hda_update_int_sts(d);
260 if (d->int_sts & (1 << 31) && d->int_ctl & (1 << 31)) {
261 level = 1;
262 } else {
263 level = 0;
264 }
17786d52
GH		 265 dprint(d, 2, "%s: level %d [%s]\n", __FUNCTION__,
266 level, msi ? "msi" : "intx");
267 if (msi) {
268 if (level) {
269 msi_notify(&d->pci, 0);
270 }
271 } else {
272 qemu_set_irq(d->pci.irq[0], level);
273 }
d61a4ce8
GH		 274}
275
276static int intel_hda_send_command(IntelHDAState *d, uint32_t verb)
277{
278 uint32_t cad, nid, data;
279 HDACodecDevice *codec;
dbaa7904 280 HDACodecDeviceClass *cdc;
d61a4ce8
GH		 281
282 cad = (verb >> 28) & 0x0f;
283 if (verb & (1 << 27)) {
284 /* indirect node addressing, not specified in HDA 1.0 */
285 dprint(d, 1, "%s: indirect node addressing (guest bug?)\n", __FUNCTION__);
286 return -1;
287 }
288 nid = (verb >> 20) & 0x7f;
289 data = verb & 0xfffff;
290
291 codec = hda_codec_find(&d->codecs, cad);
292 if (codec == NULL) {
293 dprint(d, 1, "%s: addressed non-existing codec\n", __FUNCTION__);
294 return -1;
295 }
dbaa7904
AL		 296 cdc = HDA_CODEC_DEVICE_GET_CLASS(codec);
297 cdc->command(codec, nid, data);
d61a4ce8
GH		 298 return 0;
299}
300
301static void intel_hda_corb_run(IntelHDAState *d)
302{
303 target_phys_addr_t addr;
304 uint32_t rp, verb;
305
306 if (d->ics & ICH6_IRS_BUSY) {
307 dprint(d, 2, "%s: [icw] verb 0x%08x\n", __FUNCTION__, d->icw);
308 intel_hda_send_command(d, d->icw);
309 return;
310 }
311
312 for (;;) {
313 if (!(d->corb_ctl & ICH6_CORBCTL_RUN)) {
314 dprint(d, 2, "%s: !run\n", __FUNCTION__);
315 return;
316 }
317 if ((d->corb_rp & 0xff) == d->corb_wp) {
318 dprint(d, 2, "%s: corb ring empty\n", __FUNCTION__);
319 return;
320 }
321 if (d->rirb_count == d->rirb_cnt) {
322 dprint(d, 2, "%s: rirb count reached\n", __FUNCTION__);
323 return;
324 }
325
326 rp = (d->corb_rp + 1) & 0xff;
327 addr = intel_hda_addr(d->corb_lbase, d->corb_ubase);
fa0ce55c 328 verb = ldl_le_pci_dma(&d->pci, addr + 4*rp);
d61a4ce8
GH		 329 d->corb_rp = rp;
330
331 dprint(d, 2, "%s: [rp 0x%x] verb 0x%08x\n", __FUNCTION__, rp, verb);
332 intel_hda_send_command(d, verb);
333 }
334}
335
336static void intel_hda_response(HDACodecDevice *dev, bool solicited, uint32_t response)
337{
338 HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus);
339 IntelHDAState *d = container_of(bus, IntelHDAState, codecs);
340 target_phys_addr_t addr;
341 uint32_t wp, ex;
342
343 if (d->ics & ICH6_IRS_BUSY) {
344 dprint(d, 2, "%s: [irr] response 0x%x, cad 0x%x\n",
345 __FUNCTION__, response, dev->cad);
346 d->irr = response;
347 d->ics &= ~(ICH6_IRS_BUSY | 0xf0);
348 d->ics |= (ICH6_IRS_VALID | (dev->cad << 4));
349 return;
350 }
351
352 if (!(d->rirb_ctl & ICH6_RBCTL_DMA_EN)) {
353 dprint(d, 1, "%s: rirb dma disabled, drop codec response\n", __FUNCTION__);
354 return;
355 }
356
357 ex = (solicited ? 0 : (1 << 4)) | dev->cad;
358 wp = (d->rirb_wp + 1) & 0xff;
359 addr = intel_hda_addr(d->rirb_lbase, d->rirb_ubase);
fa0ce55c
DG		 360 stl_le_pci_dma(&d->pci, addr + 8*wp, response);
361 stl_le_pci_dma(&d->pci, addr + 8*wp + 4, ex);
d61a4ce8
GH		 362 d->rirb_wp = wp;
363
364 dprint(d, 2, "%s: [wp 0x%x] response 0x%x, extra 0x%x\n",
365 __FUNCTION__, wp, response, ex);
366
367 d->rirb_count++;
368 if (d->rirb_count == d->rirb_cnt) {
369 dprint(d, 2, "%s: rirb count reached (%d)\n", __FUNCTION__, d->rirb_count);
370 if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) {
371 d->rirb_sts |= ICH6_RBSTS_IRQ;
372 intel_hda_update_irq(d);
373 }
374 } else if ((d->corb_rp & 0xff) == d->corb_wp) {
375 dprint(d, 2, "%s: corb ring empty (%d/%d)\n", __FUNCTION__,
376 d->rirb_count, d->rirb_cnt);
377 if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) {
378 d->rirb_sts |= ICH6_RBSTS_IRQ;
379 intel_hda_update_irq(d);
380 }
381 }
382}
383
384static bool intel_hda_xfer(HDACodecDevice *dev, uint32_t stnr, bool output,
385 uint8_t *buf, uint32_t len)
386{
387 HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus);
388 IntelHDAState *d = container_of(bus, IntelHDAState, codecs);
d61a4ce8
GH		 389 target_phys_addr_t addr;
390 uint32_t s, copy, left;
36ac4ad3 391 IntelHDAStream *st;
d61a4ce8
GH		 392 bool irq = false;
393
36ac4ad3
MAL		 394 st = output ? d->st + 4 : d->st;
395 for (s = 0; s < 4; s++) {
396 if (stnr == ((st[s].ctl >> 20) & 0x0f)) {
397 st = st + s;
d61a4ce8
GH		 398 break;
399 }
400 }
18ebcc86 401 if (s == 4) {
d61a4ce8
GH		 402 return false;
403 }
404 if (st->bpl == NULL) {
405 return false;
406 }
407 if (st->ctl & (1 << 26)) {
408 /*
409 * Wait with the next DMA xfer until the guest
410 * has acked the buffer completion interrupt
411 */
412 return false;
413 }
414
415 left = len;
416 while (left > 0) {
417 copy = left;
418 if (copy > st->bsize - st->lpib)
419 copy = st->bsize - st->lpib;
420 if (copy > st->bpl[st->be].len - st->bp)
421 copy = st->bpl[st->be].len - st->bp;
422
423 dprint(d, 3, "dma: entry %d, pos %d/%d, copy %d\n",
424 st->be, st->bp, st->bpl[st->be].len, copy);
425
fa0ce55c 426 pci_dma_rw(&d->pci, st->bpl[st->be].addr + st->bp, buf, copy, !output);
d61a4ce8
GH		 427 st->lpib += copy;
428 st->bp += copy;
429 buf += copy;
430 left -= copy;
431
432 if (st->bpl[st->be].len == st->bp) {
433 /* bpl entry filled */
434 if (st->bpl[st->be].flags & 0x01) {
435 irq = true;
436 }
437 st->bp = 0;
438 st->be++;
439 if (st->be == st->bentries) {
440 /* bpl wrap around */
441 st->be = 0;
442 st->lpib = 0;
443 }
444 }
445 }
446 if (d->dp_lbase & 0x01) {
447 addr = intel_hda_addr(d->dp_lbase & ~0x01, d->dp_ubase);
fa0ce55c 448 stl_le_pci_dma(&d->pci, addr + 8*s, st->lpib);
d61a4ce8
GH		 449 }
450 dprint(d, 3, "dma: --\n");
451
452 if (irq) {
453 st->ctl |= (1 << 26); /* buffer completion interrupt */
454 intel_hda_update_irq(d);
455 }
456 return true;
457}
458
459static void intel_hda_parse_bdl(IntelHDAState *d, IntelHDAStream *st)
460{
461 target_phys_addr_t addr;
462 uint8_t buf[16];
463 uint32_t i;
464
465 addr = intel_hda_addr(st->bdlp_lbase, st->bdlp_ubase);
466 st->bentries = st->lvi +1;
7267c094
AL		 467 g_free(st->bpl);
468 st->bpl = g_malloc(sizeof(bpl) * st->bentries);
d61a4ce8 469 for (i = 0; i < st->bentries; i++, addr += 16) {
fa0ce55c 470 pci_dma_read(&d->pci, addr, buf, 16);
d61a4ce8
GH		 471 st->bpl[i].addr = le64_to_cpu(*(uint64_t *)buf);
472 st->bpl[i].len = le32_to_cpu(*(uint32_t *)(buf + 8));
473 st->bpl[i].flags = le32_to_cpu(*(uint32_t *)(buf + 12));
474 dprint(d, 1, "bdl/%d: 0x%" PRIx64 " +0x%x, 0x%x\n",
475 i, st->bpl[i].addr, st->bpl[i].len, st->bpl[i].flags);
476 }
477
478 st->bsize = st->cbl;
479 st->lpib = 0;
480 st->be = 0;
481 st->bp = 0;
482}
483
ba43d289 484static void intel_hda_notify_codecs(IntelHDAState *d, uint32_t stream, bool running, bool output)
d61a4ce8
GH		 485{
486 DeviceState *qdev;
487 HDACodecDevice *cdev;
488
d8bb00d6 489 QTAILQ_FOREACH(qdev, &d->codecs.qbus.children, sibling) {
dbaa7904
AL		 490 HDACodecDeviceClass *cdc;
491
d61a4ce8 492 cdev = DO_UPCAST(HDACodecDevice, qdev, qdev);
dbaa7904
AL		 493 cdc = HDA_CODEC_DEVICE_GET_CLASS(cdev);
494 if (cdc->stream) {
495 cdc->stream(cdev, stream, running, output);
d61a4ce8
GH		 496 }
497 }
498}
499
500/* --------------------------------------------------------------------- */
501
502static void intel_hda_set_g_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
503{
504 if ((d->g_ctl & ICH6_GCTL_RESET) == 0) {
505 intel_hda_reset(&d->pci.qdev);
506 }
507}
508
6a0d02f5
GH		 509static void intel_hda_set_wake_en(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
510{
511 intel_hda_update_irq(d);
512}
513
d61a4ce8
GH		 514static void intel_hda_set_state_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
515{
516 intel_hda_update_irq(d);
517}
518
519static void intel_hda_set_int_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
520{
521 intel_hda_update_irq(d);
522}
523
524static void intel_hda_get_wall_clk(IntelHDAState *d, const IntelHDAReg *reg)
525{
526 int64_t ns;
527
528 ns = qemu_get_clock_ns(vm_clock) - d->wall_base_ns;
529 d->wall_clk = (uint32_t)(ns * 24 / 1000); /* 24 MHz */
530}
531
532static void intel_hda_set_corb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
533{
534 intel_hda_corb_run(d);
535}
536
537static void intel_hda_set_corb_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
538{
539 intel_hda_corb_run(d);
540}
541
542static void intel_hda_set_rirb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
543{
544 if (d->rirb_wp & ICH6_RIRBWP_RST) {
545 d->rirb_wp = 0;
546 }
547}
548
549static void intel_hda_set_rirb_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
550{
551 intel_hda_update_irq(d);
552
553 if ((old & ICH6_RBSTS_IRQ) && !(d->rirb_sts & ICH6_RBSTS_IRQ)) {
554 /* cleared ICH6_RBSTS_IRQ */
555 d->rirb_count = 0;
556 intel_hda_corb_run(d);
557 }
558}
559
560static void intel_hda_set_ics(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
561{
562 if (d->ics & ICH6_IRS_BUSY) {
563 intel_hda_corb_run(d);
564 }
565}
566
567static void intel_hda_set_st_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
568{
ba43d289 569 bool output = reg->stream >= 4;
d61a4ce8
GH		 570 IntelHDAStream *st = d->st + reg->stream;
571
572 if (st->ctl & 0x01) {
573 /* reset */
574 dprint(d, 1, "st #%d: reset\n", reg->stream);
575 st->ctl = 0;
576 }
577 if ((st->ctl & 0x02) != (old & 0x02)) {
578 uint32_t stnr = (st->ctl >> 20) & 0x0f;
579 /* run bit flipped */
580 if (st->ctl & 0x02) {
581 /* start */
582 dprint(d, 1, "st #%d: start %d (ring buf %d bytes)\n",
583 reg->stream, stnr, st->cbl);
584 intel_hda_parse_bdl(d, st);
ba43d289 585 intel_hda_notify_codecs(d, stnr, true, output);
d61a4ce8
GH		 586 } else {
587 /* stop */
588 dprint(d, 1, "st #%d: stop %d\n", reg->stream, stnr);
ba43d289 589 intel_hda_notify_codecs(d, stnr, false, output);
d61a4ce8
GH		 590 }
591 }
592 intel_hda_update_irq(d);
593}
594
595/* --------------------------------------------------------------------- */
596
597#define ST_REG(_n, _o) (0x80 + (_n) * 0x20 + (_o))
598
599static const struct IntelHDAReg regtab[] = {
600 /* global */
601 [ ICH6_REG_GCAP ] = {
602 .name = "GCAP",
603 .size = 2,
604 .reset = 0x4401,
605 },
606 [ ICH6_REG_VMIN ] = {
607 .name = "VMIN",
608 .size = 1,
609 },
610 [ ICH6_REG_VMAJ ] = {
611 .name = "VMAJ",
612 .size = 1,
613 .reset = 1,
614 },
615 [ ICH6_REG_OUTPAY ] = {
616 .name = "OUTPAY",
617 .size = 2,
618 .reset = 0x3c,
619 },
620 [ ICH6_REG_INPAY ] = {
621 .name = "INPAY",
622 .size = 2,
623 .reset = 0x1d,
624 },
625 [ ICH6_REG_GCTL ] = {
626 .name = "GCTL",
627 .size = 4,
628 .wmask = 0x0103,
629 .offset = offsetof(IntelHDAState, g_ctl),
630 .whandler = intel_hda_set_g_ctl,
631 },
632 [ ICH6_REG_WAKEEN ] = {
633 .name = "WAKEEN",
634 .size = 2,
df0db221 635 .wmask = 0x7fff,
d61a4ce8 636 .offset = offsetof(IntelHDAState, wake_en),
6a0d02f5 637 .whandler = intel_hda_set_wake_en,
d61a4ce8
GH		 638 },
639 [ ICH6_REG_STATESTS ] = {
640 .name = "STATESTS",
641 .size = 2,
df0db221
GH		 642 .wmask = 0x7fff,
643 .wclear = 0x7fff,
d61a4ce8
GH		 644 .offset = offsetof(IntelHDAState, state_sts),
645 .whandler = intel_hda_set_state_sts,
646 },
647
648 /* interrupts */
649 [ ICH6_REG_INTCTL ] = {
650 .name = "INTCTL",
651 .size = 4,
652 .wmask = 0xc00000ff,
653 .offset = offsetof(IntelHDAState, int_ctl),
654 .whandler = intel_hda_set_int_ctl,
655 },
656 [ ICH6_REG_INTSTS ] = {
657 .name = "INTSTS",
658 .size = 4,
659 .wmask = 0xc00000ff,
660 .wclear = 0xc00000ff,
661 .offset = offsetof(IntelHDAState, int_sts),
662 },
663
664 /* misc */
665 [ ICH6_REG_WALLCLK ] = {
666 .name = "WALLCLK",
667 .size = 4,
668 .offset = offsetof(IntelHDAState, wall_clk),
669 .rhandler = intel_hda_get_wall_clk,
670 },
671 [ ICH6_REG_WALLCLK + 0x2000 ] = {
672 .name = "WALLCLK(alias)",
673 .size = 4,
674 .offset = offsetof(IntelHDAState, wall_clk),
675 .rhandler = intel_hda_get_wall_clk,
676 },
677
678 /* dma engine */
679 [ ICH6_REG_CORBLBASE ] = {
680 .name = "CORBLBASE",
681 .size = 4,
682 .wmask = 0xffffff80,
683 .offset = offsetof(IntelHDAState, corb_lbase),
684 },
685 [ ICH6_REG_CORBUBASE ] = {
686 .name = "CORBUBASE",
687 .size = 4,
688 .wmask = 0xffffffff,
689 .offset = offsetof(IntelHDAState, corb_ubase),
690 },
691 [ ICH6_REG_CORBWP ] = {
692 .name = "CORBWP",
693 .size = 2,
694 .wmask = 0xff,
695 .offset = offsetof(IntelHDAState, corb_wp),
696 .whandler = intel_hda_set_corb_wp,
697 },
698 [ ICH6_REG_CORBRP ] = {
699 .name = "CORBRP",
700 .size = 2,
701 .wmask = 0x80ff,
702 .offset = offsetof(IntelHDAState, corb_rp),
703 },
704 [ ICH6_REG_CORBCTL ] = {
705 .name = "CORBCTL",
706 .size = 1,
707 .wmask = 0x03,
708 .offset = offsetof(IntelHDAState, corb_ctl),
709 .whandler = intel_hda_set_corb_ctl,
710 },
711 [ ICH6_REG_CORBSTS ] = {
712 .name = "CORBSTS",
713 .size = 1,
714 .wmask = 0x01,
715 .wclear = 0x01,
716 .offset = offsetof(IntelHDAState, corb_sts),
717 },
718 [ ICH6_REG_CORBSIZE ] = {
719 .name = "CORBSIZE",
720 .size = 1,
721 .reset = 0x42,
722 .offset = offsetof(IntelHDAState, corb_size),
723 },
724 [ ICH6_REG_RIRBLBASE ] = {
725 .name = "RIRBLBASE",
726 .size = 4,
727 .wmask = 0xffffff80,
728 .offset = offsetof(IntelHDAState, rirb_lbase),
729 },
730 [ ICH6_REG_RIRBUBASE ] = {
731 .name = "RIRBUBASE",
732 .size = 4,
733 .wmask = 0xffffffff,
734 .offset = offsetof(IntelHDAState, rirb_ubase),
735 },
736 [ ICH6_REG_RIRBWP ] = {
737 .name = "RIRBWP",
738 .size = 2,
739 .wmask = 0x8000,
740 .offset = offsetof(IntelHDAState, rirb_wp),
741 .whandler = intel_hda_set_rirb_wp,
742 },
743 [ ICH6_REG_RINTCNT ] = {
744 .name = "RINTCNT",
745 .size = 2,
746 .wmask = 0xff,
747 .offset = offsetof(IntelHDAState, rirb_cnt),
748 },
749 [ ICH6_REG_RIRBCTL ] = {
750 .name = "RIRBCTL",
751 .size = 1,
752 .wmask = 0x07,
753 .offset = offsetof(IntelHDAState, rirb_ctl),
754 },
755 [ ICH6_REG_RIRBSTS ] = {
756 .name = "RIRBSTS",
757 .size = 1,
758 .wmask = 0x05,
759 .wclear = 0x05,
760 .offset = offsetof(IntelHDAState, rirb_sts),
761 .whandler = intel_hda_set_rirb_sts,
762 },
763 [ ICH6_REG_RIRBSIZE ] = {
764 .name = "RIRBSIZE",
765 .size = 1,
766 .reset = 0x42,
767 .offset = offsetof(IntelHDAState, rirb_size),
768 },
769
770 [ ICH6_REG_DPLBASE ] = {
771 .name = "DPLBASE",
772 .size = 4,
773 .wmask = 0xffffff81,
774 .offset = offsetof(IntelHDAState, dp_lbase),
775 },
776 [ ICH6_REG_DPUBASE ] = {
777 .name = "DPUBASE",
778 .size = 4,
779 .wmask = 0xffffffff,
780 .offset = offsetof(IntelHDAState, dp_ubase),
781 },
782
783 [ ICH6_REG_IC ] = {
784 .name = "ICW",
785 .size = 4,
786 .wmask = 0xffffffff,
787 .offset = offsetof(IntelHDAState, icw),
788 },
789 [ ICH6_REG_IR ] = {
790 .name = "IRR",
791 .size = 4,
792 .offset = offsetof(IntelHDAState, irr),
793 },
794 [ ICH6_REG_IRS ] = {
795 .name = "ICS",
796 .size = 2,
797 .wmask = 0x0003,
798 .wclear = 0x0002,
799 .offset = offsetof(IntelHDAState, ics),
800 .whandler = intel_hda_set_ics,
801 },
802
803#define HDA_STREAM(_t, _i) \
804 [ ST_REG(_i, ICH6_REG_SD_CTL) ] = { \
805 .stream = _i, \
806 .name = _t stringify(_i) " CTL", \
807 .size = 4, \
808 .wmask = 0x1cff001f, \
809 .offset = offsetof(IntelHDAState, st[_i].ctl), \
810 .whandler = intel_hda_set_st_ctl, \
811 }, \
812 [ ST_REG(_i, ICH6_REG_SD_CTL) + 2] = { \
813 .stream = _i, \
814 .name = _t stringify(_i) " CTL(stnr)", \
815 .size = 1, \
816 .shift = 16, \
817 .wmask = 0x00ff0000, \
818 .offset = offsetof(IntelHDAState, st[_i].ctl), \
819 .whandler = intel_hda_set_st_ctl, \
820 }, \
821 [ ST_REG(_i, ICH6_REG_SD_STS)] = { \
822 .stream = _i, \
823 .name = _t stringify(_i) " CTL(sts)", \
824 .size = 1, \
825 .shift = 24, \
826 .wmask = 0x1c000000, \
827 .wclear = 0x1c000000, \
828 .offset = offsetof(IntelHDAState, st[_i].ctl), \
829 .whandler = intel_hda_set_st_ctl, \
830 }, \
831 [ ST_REG(_i, ICH6_REG_SD_LPIB) ] = { \
832 .stream = _i, \
833 .name = _t stringify(_i) " LPIB", \
834 .size = 4, \
835 .offset = offsetof(IntelHDAState, st[_i].lpib), \
836 }, \
837 [ ST_REG(_i, ICH6_REG_SD_LPIB) + 0x2000 ] = { \
838 .stream = _i, \
839 .name = _t stringify(_i) " LPIB(alias)", \
840 .size = 4, \
841 .offset = offsetof(IntelHDAState, st[_i].lpib), \
842 }, \
843 [ ST_REG(_i, ICH6_REG_SD_CBL) ] = { \
844 .stream = _i, \
845 .name = _t stringify(_i) " CBL", \
846 .size = 4, \
847 .wmask = 0xffffffff, \
848 .offset = offsetof(IntelHDAState, st[_i].cbl), \
849 }, \
850 [ ST_REG(_i, ICH6_REG_SD_LVI) ] = { \
851 .stream = _i, \
852 .name = _t stringify(_i) " LVI", \
853 .size = 2, \
854 .wmask = 0x00ff, \
855 .offset = offsetof(IntelHDAState, st[_i].lvi), \
856 }, \
857 [ ST_REG(_i, ICH6_REG_SD_FIFOSIZE) ] = { \
858 .stream = _i, \
859 .name = _t stringify(_i) " FIFOS", \
860 .size = 2, \
861 .reset = HDA_BUFFER_SIZE, \
862 }, \
863 [ ST_REG(_i, ICH6_REG_SD_FORMAT) ] = { \
864 .stream = _i, \
865 .name = _t stringify(_i) " FMT", \
866 .size = 2, \
867 .wmask = 0x7f7f, \
868 .offset = offsetof(IntelHDAState, st[_i].fmt), \
869 }, \
870 [ ST_REG(_i, ICH6_REG_SD_BDLPL) ] = { \
871 .stream = _i, \
872 .name = _t stringify(_i) " BDLPL", \
873 .size = 4, \
874 .wmask = 0xffffff80, \
875 .offset = offsetof(IntelHDAState, st[_i].bdlp_lbase), \
876 }, \
877 [ ST_REG(_i, ICH6_REG_SD_BDLPU) ] = { \
878 .stream = _i, \
879 .name = _t stringify(_i) " BDLPU", \
880 .size = 4, \
881 .wmask = 0xffffffff, \
882 .offset = offsetof(IntelHDAState, st[_i].bdlp_ubase), \
883 }, \
884
885 HDA_STREAM("IN", 0)
886 HDA_STREAM("IN", 1)
887 HDA_STREAM("IN", 2)
888 HDA_STREAM("IN", 3)
889
890 HDA_STREAM("OUT", 4)
891 HDA_STREAM("OUT", 5)
892 HDA_STREAM("OUT", 6)
893 HDA_STREAM("OUT", 7)
894
895};
896
897static const IntelHDAReg *intel_hda_reg_find(IntelHDAState *d, target_phys_addr_t addr)
898{
899 const IntelHDAReg *reg;
900
901 if (addr >= sizeof(regtab)/sizeof(regtab[0])) {
902 goto noreg;
903 }
904 reg = regtab+addr;
905 if (reg->name == NULL) {
906 goto noreg;
907 }
908 return reg;
909
910noreg:
911 dprint(d, 1, "unknown register, addr 0x%x\n", (int) addr);
912 return NULL;
913}
914
915static uint32_t *intel_hda_reg_addr(IntelHDAState *d, const IntelHDAReg *reg)
916{
917 uint8_t *addr = (void*)d;
918
919 addr += reg->offset;
920 return (uint32_t*)addr;
921}
922
923static void intel_hda_reg_write(IntelHDAState *d, const IntelHDAReg *reg, uint32_t val,
924 uint32_t wmask)
925{
926 uint32_t *addr;
927 uint32_t old;
928
929 if (!reg) {
930 return;
931 }
932
933 if (d->debug) {
934 time_t now = time(NULL);
935 if (d->last_write && d->last_reg == reg && d->last_val == val) {
936 d->repeat_count++;
937 if (d->last_sec != now) {
938 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
939 d->last_sec = now;
940 d->repeat_count = 0;
941 }
942 } else {
943 if (d->repeat_count) {
944 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
945 }
946 dprint(d, 2, "write %-16s: 0x%x (%x)\n", reg->name, val, wmask);
947 d->last_write = 1;
948 d->last_reg = reg;
949 d->last_val = val;
950 d->last_sec = now;
951 d->repeat_count = 0;
952 }
953 }
954 assert(reg->offset != 0);
955
956 addr = intel_hda_reg_addr(d, reg);
957 old = *addr;
958
959 if (reg->shift) {
960 val <<= reg->shift;
961 wmask <<= reg->shift;
962 }
963 wmask &= reg->wmask;
964 *addr &= ~wmask;
965 *addr |= wmask & val;
966 *addr &= ~(val & reg->wclear);
967
968 if (reg->whandler) {
969 reg->whandler(d, reg, old);
970 }
971}
972
973static uint32_t intel_hda_reg_read(IntelHDAState *d, const IntelHDAReg *reg,
974 uint32_t rmask)
975{
976 uint32_t *addr, ret;
977
978 if (!reg) {
979 return 0;
980 }
981
982 if (reg->rhandler) {
983 reg->rhandler(d, reg);
984 }
985
986 if (reg->offset == 0) {
987 /* constant read-only register */
988 ret = reg->reset;
989 } else {
990 addr = intel_hda_reg_addr(d, reg);
991 ret = *addr;
992 if (reg->shift) {
993 ret >>= reg->shift;
994 }
995 ret &= rmask;
996 }
997 if (d->debug) {
998 time_t now = time(NULL);
999 if (!d->last_write && d->last_reg == reg && d->last_val == ret) {
1000 d->repeat_count++;
1001 if (d->last_sec != now) {
1002 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
1003 d->last_sec = now;
1004 d->repeat_count = 0;
1005 }
1006 } else {
1007 if (d->repeat_count) {
1008 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
1009 }
1010 dprint(d, 2, "read %-16s: 0x%x (%x)\n", reg->name, ret, rmask);
1011 d->last_write = 0;
1012 d->last_reg = reg;
1013 d->last_val = ret;
1014 d->last_sec = now;
1015 d->repeat_count = 0;
1016 }
1017 }
1018 return ret;
1019}
1020
1021static void intel_hda_regs_reset(IntelHDAState *d)
1022{
1023 uint32_t *addr;
1024 int i;
1025
1026 for (i = 0; i < sizeof(regtab)/sizeof(regtab[0]); i++) {
1027 if (regtab[i].name == NULL) {
1028 continue;
1029 }
1030 if (regtab[i].offset == 0) {
1031 continue;
1032 }
1033 addr = intel_hda_reg_addr(d, regtab + i);
1034 *addr = regtab[i].reset;
1035 }
1036}
1037
1038/* --------------------------------------------------------------------- */
1039
1040static void intel_hda_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1041{
1042 IntelHDAState *d = opaque;
1043 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1044
1045 intel_hda_reg_write(d, reg, val, 0xff);
1046}
1047
1048static void intel_hda_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1049{
1050 IntelHDAState *d = opaque;
1051 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1052
1053 intel_hda_reg_write(d, reg, val, 0xffff);
1054}
1055
1056static void intel_hda_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1057{
1058 IntelHDAState *d = opaque;
1059 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1060
1061 intel_hda_reg_write(d, reg, val, 0xffffffff);
1062}
1063
1064static uint32_t intel_hda_mmio_readb(void *opaque, target_phys_addr_t addr)
1065{
1066 IntelHDAState *d = opaque;
1067 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1068
1069 return intel_hda_reg_read(d, reg, 0xff);
1070}
1071
1072static uint32_t intel_hda_mmio_readw(void *opaque, target_phys_addr_t addr)
1073{
1074 IntelHDAState *d = opaque;
1075 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1076
1077 return intel_hda_reg_read(d, reg, 0xffff);
1078}
1079
1080static uint32_t intel_hda_mmio_readl(void *opaque, target_phys_addr_t addr)
1081{
1082 IntelHDAState *d = opaque;
1083 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1084
1085 return intel_hda_reg_read(d, reg, 0xffffffff);
1086}
1087
234bbdf1
AK		 1088static const MemoryRegionOps intel_hda_mmio_ops = {
1089 .old_mmio = {
1090 .read = {
1091 intel_hda_mmio_readb,
1092 intel_hda_mmio_readw,
1093 intel_hda_mmio_readl,
1094 },
1095 .write = {
1096 intel_hda_mmio_writeb,
1097 intel_hda_mmio_writew,
1098 intel_hda_mmio_writel,
1099 },
1100 },
1101 .endianness = DEVICE_NATIVE_ENDIAN,
d61a4ce8
GH		 1102};
1103
d61a4ce8
GH		 1104/* --------------------------------------------------------------------- */
1105
1106static void intel_hda_reset(DeviceState *dev)
1107{
1108 IntelHDAState *d = DO_UPCAST(IntelHDAState, pci.qdev, dev);
1109 DeviceState *qdev;
1110 HDACodecDevice *cdev;
1111
1112 intel_hda_regs_reset(d);
74475455 1113 d->wall_base_ns = qemu_get_clock_ns(vm_clock);
d61a4ce8
GH		 1114
1115 /* reset codecs */
d8bb00d6 1116 QTAILQ_FOREACH(qdev, &d->codecs.qbus.children, sibling) {
d61a4ce8 1117 cdev = DO_UPCAST(HDACodecDevice, qdev, qdev);
94afdadc 1118 device_reset(DEVICE(cdev));
d61a4ce8
GH		 1119 d->state_sts |= (1 << cdev->cad);
1120 }
1121 intel_hda_update_irq(d);
1122}
1123
1124static int intel_hda_init(PCIDevice *pci)
1125{
1126 IntelHDAState *d = DO_UPCAST(IntelHDAState, pci, pci);
1127 uint8_t *conf = d->pci.config;
1128
f79f2bfc 1129 d->name = object_get_typename(OBJECT(d));
d61a4ce8 1130
d61a4ce8
GH		 1131 pci_config_set_interrupt_pin(conf, 1);
1132
1133 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
1134 conf[0x40] = 0x01;
1135
234bbdf1
AK		 1136 memory_region_init_io(&d->mmio, &intel_hda_mmio_ops, d,
1137 "intel-hda", 0x4000);
e824b2cc 1138 pci_register_bar(&d->pci, 0, 0, &d->mmio);
17786d52
GH		 1139 if (d->msi) {
1140 msi_init(&d->pci, 0x50, 1, true, false);
1141 }
d61a4ce8
GH		 1142
1143 hda_codec_bus_init(&d->pci.qdev, &d->codecs,
1144 intel_hda_response, intel_hda_xfer);
1145
1146 return 0;
1147}
1148
dc4b9240
GH		 1149static int intel_hda_exit(PCIDevice *pci)
1150{
1151 IntelHDAState *d = DO_UPCAST(IntelHDAState, pci, pci);
1152
45fe15c2 1153 msi_uninit(&d->pci);
234bbdf1 1154 memory_region_destroy(&d->mmio);
dc4b9240
GH		 1155 return 0;
1156}
1157
17786d52
GH		 1158static void intel_hda_write_config(PCIDevice *pci, uint32_t addr,
1159 uint32_t val, int len)
1160{
1161 IntelHDAState *d = DO_UPCAST(IntelHDAState, pci, pci);
1162
1163 pci_default_write_config(pci, addr, val, len);
1164 if (d->msi) {
1165 msi_write_config(pci, addr, val, len);
1166 }
1167}
1168
d61a4ce8
GH		 1169static int intel_hda_post_load(void *opaque, int version)
1170{
1171 IntelHDAState* d = opaque;
1172 int i;
1173
1174 dprint(d, 1, "%s\n", __FUNCTION__);
1175 for (i = 0; i < ARRAY_SIZE(d->st); i++) {
1176 if (d->st[i].ctl & 0x02) {
1177 intel_hda_parse_bdl(d, &d->st[i]);
1178 }
1179 }
1180 intel_hda_update_irq(d);
1181 return 0;
1182}
1183
1184static const VMStateDescription vmstate_intel_hda_stream = {
1185 .name = "intel-hda-stream",
1186 .version_id = 1,
1187 .fields = (VMStateField []) {
1188 VMSTATE_UINT32(ctl, IntelHDAStream),
1189 VMSTATE_UINT32(lpib, IntelHDAStream),
1190 VMSTATE_UINT32(cbl, IntelHDAStream),
1191 VMSTATE_UINT32(lvi, IntelHDAStream),
1192 VMSTATE_UINT32(fmt, IntelHDAStream),
1193 VMSTATE_UINT32(bdlp_lbase, IntelHDAStream),
1194 VMSTATE_UINT32(bdlp_ubase, IntelHDAStream),
1195 VMSTATE_END_OF_LIST()
1196 }
1197};
1198
1199static const VMStateDescription vmstate_intel_hda = {
1200 .name = "intel-hda",
1201 .version_id = 1,
1202 .post_load = intel_hda_post_load,
1203 .fields = (VMStateField []) {
1204 VMSTATE_PCI_DEVICE(pci, IntelHDAState),
1205
1206 /* registers */
1207 VMSTATE_UINT32(g_ctl, IntelHDAState),
1208 VMSTATE_UINT32(wake_en, IntelHDAState),
1209 VMSTATE_UINT32(state_sts, IntelHDAState),
1210 VMSTATE_UINT32(int_ctl, IntelHDAState),
1211 VMSTATE_UINT32(int_sts, IntelHDAState),
1212 VMSTATE_UINT32(wall_clk, IntelHDAState),
1213 VMSTATE_UINT32(corb_lbase, IntelHDAState),
1214 VMSTATE_UINT32(corb_ubase, IntelHDAState),
1215 VMSTATE_UINT32(corb_rp, IntelHDAState),
1216 VMSTATE_UINT32(corb_wp, IntelHDAState),
1217 VMSTATE_UINT32(corb_ctl, IntelHDAState),
1218 VMSTATE_UINT32(corb_sts, IntelHDAState),
1219 VMSTATE_UINT32(corb_size, IntelHDAState),
1220 VMSTATE_UINT32(rirb_lbase, IntelHDAState),
1221 VMSTATE_UINT32(rirb_ubase, IntelHDAState),
1222 VMSTATE_UINT32(rirb_wp, IntelHDAState),
1223 VMSTATE_UINT32(rirb_cnt, IntelHDAState),
1224 VMSTATE_UINT32(rirb_ctl, IntelHDAState),
1225 VMSTATE_UINT32(rirb_sts, IntelHDAState),
1226 VMSTATE_UINT32(rirb_size, IntelHDAState),
1227 VMSTATE_UINT32(dp_lbase, IntelHDAState),
1228 VMSTATE_UINT32(dp_ubase, IntelHDAState),
1229 VMSTATE_UINT32(icw, IntelHDAState),
1230 VMSTATE_UINT32(irr, IntelHDAState),
1231 VMSTATE_UINT32(ics, IntelHDAState),
1232 VMSTATE_STRUCT_ARRAY(st, IntelHDAState, 8, 0,
1233 vmstate_intel_hda_stream,
1234 IntelHDAStream),
1235
1236 /* additional state info */
1237 VMSTATE_UINT32(rirb_count, IntelHDAState),
1238 VMSTATE_INT64(wall_base_ns, IntelHDAState),
1239
1240 VMSTATE_END_OF_LIST()
1241 }
1242};
1243
40021f08
AL		 1244static Property intel_hda_properties[] = {
1245 DEFINE_PROP_UINT32("debug", IntelHDAState, debug, 0),
1246 DEFINE_PROP_UINT32("msi", IntelHDAState, msi, 1),
1247 DEFINE_PROP_END_OF_LIST(),
1248};
1249
1250static void intel_hda_class_init(ObjectClass *klass, void *data)
1251{
39bffca2 1252 DeviceClass *dc = DEVICE_CLASS(klass);
40021f08
AL		 1253 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1254
1255 k->init = intel_hda_init;
1256 k->exit = intel_hda_exit;
1257 k->config_write = intel_hda_write_config;
1258 k->vendor_id = PCI_VENDOR_ID_INTEL;
1259 k->device_id = 0x2668;
1260 k->revision = 1;
1261 k->class_id = PCI_CLASS_MULTIMEDIA_HD_AUDIO;
39bffca2
AL		 1262 dc->desc = "Intel HD Audio Controller";
1263 dc->reset = intel_hda_reset;
1264 dc->vmsd = &vmstate_intel_hda;
1265 dc->props = intel_hda_properties;
40021f08
AL		 1266}
1267
39bffca2
AL		 1268static TypeInfo intel_hda_info = {
1269 .name = "intel-hda",
1270 .parent = TYPE_PCI_DEVICE,
1271 .instance_size = sizeof(IntelHDAState),
1272 .class_init = intel_hda_class_init,
40021f08
AL		 1273};
1274
39bffca2
AL		 1275static void hda_codec_device_class_init(ObjectClass *klass, void *data)
1276{
1277 DeviceClass *k = DEVICE_CLASS(klass);
1278 k->init = hda_codec_dev_init;
1279 k->exit = hda_codec_dev_exit;
1280 k->bus_info = &hda_codec_bus_info;
1281}
1282
40021f08
AL		 1283static TypeInfo hda_codec_device_type_info = {
1284 .name = TYPE_HDA_CODEC_DEVICE,
1285 .parent = TYPE_DEVICE,
1286 .instance_size = sizeof(HDACodecDevice),
1287 .abstract = true,
1288 .class_size = sizeof(HDACodecDeviceClass),
39bffca2 1289 .class_init = hda_codec_device_class_init,
d61a4ce8
GH		 1290};
1291
83f7d43a 1292static void intel_hda_register_types(void)
d61a4ce8 1293{
39bffca2 1294 type_register_static(&intel_hda_info);
40021f08 1295 type_register_static(&hda_codec_device_type_info);
d61a4ce8 1296}
83f7d43a
AF		 1297
1298type_init(intel_hda_register_types)
d61a4ce8
GH		 1299
1300/*
1301 * create intel hda controller with codec attached to it,
1302 * so '-soundhw hda' works.
1303 */
1304int intel_hda_and_codec_init(PCIBus *bus)
1305{
1306 PCIDevice *controller;
1307 BusState *hdabus;
1308 DeviceState *codec;
1309
1310 controller = pci_create_simple(bus, -1, "intel-hda");
1311 hdabus = QLIST_FIRST(&controller->qdev.child_bus);
1312 codec = qdev_create(hdabus, "hda-duplex");
1313 qdev_init_nofail(codec);
1314 return 0;
1315}
1316
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