]>
Commit | Line | Data |
---|---|---|
610626af AL |
1 | /* |
2 | * ioapic.c IOAPIC emulation logic | |
3 | * | |
4 | * Copyright (c) 2004-2005 Fabrice Bellard | |
5 | * | |
6 | * Split the ioapic logic from apic.c | |
7 | * Xiantao Zhang <xiantao.zhang@intel.com> | |
8 | * | |
9 | * This library is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU Lesser General Public | |
11 | * License as published by the Free Software Foundation; either | |
12 | * version 2 of the License, or (at your option) any later version. | |
13 | * | |
14 | * This library is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * Lesser General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 20 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
610626af AL |
21 | */ |
22 | ||
23 | #include "hw.h" | |
24 | #include "pc.h" | |
aa28b9bf | 25 | #include "apic.h" |
0280b571 | 26 | #include "ioapic.h" |
610626af AL |
27 | #include "qemu-timer.h" |
28 | #include "host-utils.h" | |
96051119 | 29 | #include "sysbus.h" |
610626af AL |
30 | |
31 | //#define DEBUG_IOAPIC | |
32 | ||
9af9b330 BS |
33 | #ifdef DEBUG_IOAPIC |
34 | #define DPRINTF(fmt, ...) \ | |
35 | do { printf("ioapic: " fmt , ## __VA_ARGS__); } while (0) | |
36 | #else | |
37 | #define DPRINTF(fmt, ...) | |
38 | #endif | |
39 | ||
0280b571 JK |
40 | #define MAX_IOAPICS 1 |
41 | ||
42 | #define IOAPIC_LVT_MASKED (1 << 16) | |
43 | #define IOAPIC_LVT_REMOTE_IRR (1 << 14) | |
610626af AL |
44 | |
45 | #define IOAPIC_TRIGGER_EDGE 0 | |
46 | #define IOAPIC_TRIGGER_LEVEL 1 | |
47 | ||
48 | /*io{apic,sapic} delivery mode*/ | |
49 | #define IOAPIC_DM_FIXED 0x0 | |
50 | #define IOAPIC_DM_LOWEST_PRIORITY 0x1 | |
51 | #define IOAPIC_DM_PMI 0x2 | |
52 | #define IOAPIC_DM_NMI 0x4 | |
53 | #define IOAPIC_DM_INIT 0x5 | |
54 | #define IOAPIC_DM_SIPI 0x5 | |
55 | #define IOAPIC_DM_EXTINT 0x7 | |
56 | ||
96051119 BS |
57 | typedef struct IOAPICState IOAPICState; |
58 | ||
610626af | 59 | struct IOAPICState { |
96051119 | 60 | SysBusDevice busdev; |
610626af AL |
61 | uint8_t id; |
62 | uint8_t ioregsel; | |
63 | ||
64 | uint32_t irr; | |
65 | uint64_t ioredtbl[IOAPIC_NUM_PINS]; | |
66 | }; | |
67 | ||
0280b571 JK |
68 | static IOAPICState *ioapics[MAX_IOAPICS]; |
69 | ||
610626af AL |
70 | static void ioapic_service(IOAPICState *s) |
71 | { | |
72 | uint8_t i; | |
73 | uint8_t trig_mode; | |
74 | uint8_t vector; | |
75 | uint8_t delivery_mode; | |
76 | uint32_t mask; | |
77 | uint64_t entry; | |
78 | uint8_t dest; | |
79 | uint8_t dest_mode; | |
80 | uint8_t polarity; | |
81 | ||
82 | for (i = 0; i < IOAPIC_NUM_PINS; i++) { | |
83 | mask = 1 << i; | |
84 | if (s->irr & mask) { | |
85 | entry = s->ioredtbl[i]; | |
86 | if (!(entry & IOAPIC_LVT_MASKED)) { | |
87 | trig_mode = ((entry >> 15) & 1); | |
88 | dest = entry >> 56; | |
89 | dest_mode = (entry >> 11) & 1; | |
90 | delivery_mode = (entry >> 8) & 7; | |
91 | polarity = (entry >> 13) & 1; | |
0280b571 | 92 | if (trig_mode == IOAPIC_TRIGGER_EDGE) { |
610626af | 93 | s->irr &= ~mask; |
0280b571 JK |
94 | } else { |
95 | s->ioredtbl[i] |= IOAPIC_LVT_REMOTE_IRR; | |
96 | } | |
610626af AL |
97 | if (delivery_mode == IOAPIC_DM_EXTINT) |
98 | vector = pic_read_irq(isa_pic); | |
99 | else | |
100 | vector = entry & 0xff; | |
101 | ||
102 | apic_deliver_irq(dest, dest_mode, delivery_mode, | |
103 | vector, polarity, trig_mode); | |
104 | } | |
105 | } | |
106 | } | |
107 | } | |
108 | ||
7d0500c4 | 109 | static void ioapic_set_irq(void *opaque, int vector, int level) |
610626af AL |
110 | { |
111 | IOAPICState *s = opaque; | |
112 | ||
113 | /* ISA IRQs map to GSI 1-1 except for IRQ0 which maps | |
114 | * to GSI 2. GSI maps to ioapic 1-1. This is not | |
115 | * the cleanest way of doing it but it should work. */ | |
116 | ||
9af9b330 | 117 | DPRINTF("%s: %s vec %x\n", __func__, level? "raise" : "lower", vector); |
610626af AL |
118 | if (vector == 0) |
119 | vector = 2; | |
120 | ||
121 | if (vector >= 0 && vector < IOAPIC_NUM_PINS) { | |
122 | uint32_t mask = 1 << vector; | |
123 | uint64_t entry = s->ioredtbl[vector]; | |
124 | ||
125 | if ((entry >> 15) & 1) { | |
126 | /* level triggered */ | |
127 | if (level) { | |
128 | s->irr |= mask; | |
129 | ioapic_service(s); | |
130 | } else { | |
131 | s->irr &= ~mask; | |
132 | } | |
133 | } else { | |
134 | /* edge triggered */ | |
135 | if (level) { | |
136 | s->irr |= mask; | |
137 | ioapic_service(s); | |
138 | } | |
139 | } | |
140 | } | |
141 | } | |
142 | ||
0280b571 JK |
143 | void ioapic_eoi_broadcast(int vector) |
144 | { | |
145 | IOAPICState *s; | |
146 | uint64_t entry; | |
147 | int i, n; | |
148 | ||
149 | for (i = 0; i < MAX_IOAPICS; i++) { | |
150 | s = ioapics[i]; | |
151 | if (!s) { | |
152 | continue; | |
153 | } | |
154 | for (n = 0; n < IOAPIC_NUM_PINS; n++) { | |
155 | entry = s->ioredtbl[n]; | |
156 | if ((entry & IOAPIC_LVT_REMOTE_IRR) && (entry & 0xff) == vector) { | |
157 | s->ioredtbl[n] = entry & ~IOAPIC_LVT_REMOTE_IRR; | |
158 | if (!(entry & IOAPIC_LVT_MASKED) && (s->irr & (1 << n))) { | |
159 | ioapic_service(s); | |
160 | } | |
161 | } | |
162 | } | |
163 | } | |
164 | } | |
165 | ||
c227f099 | 166 | static uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr) |
610626af AL |
167 | { |
168 | IOAPICState *s = opaque; | |
169 | int index; | |
170 | uint32_t val = 0; | |
171 | ||
172 | addr &= 0xff; | |
173 | if (addr == 0x00) { | |
174 | val = s->ioregsel; | |
175 | } else if (addr == 0x10) { | |
176 | switch (s->ioregsel) { | |
177 | case 0x00: | |
178 | val = s->id << 24; | |
179 | break; | |
180 | case 0x01: | |
181 | val = 0x11 | ((IOAPIC_NUM_PINS - 1) << 16); /* version 0x11 */ | |
182 | break; | |
183 | case 0x02: | |
184 | val = 0; | |
185 | break; | |
186 | default: | |
187 | index = (s->ioregsel - 0x10) >> 1; | |
188 | if (index >= 0 && index < IOAPIC_NUM_PINS) { | |
189 | if (s->ioregsel & 1) | |
190 | val = s->ioredtbl[index] >> 32; | |
191 | else | |
192 | val = s->ioredtbl[index] & 0xffffffff; | |
193 | } | |
194 | } | |
9af9b330 | 195 | DPRINTF("read: %08x = %08x\n", s->ioregsel, val); |
610626af AL |
196 | } |
197 | return val; | |
198 | } | |
199 | ||
c227f099 | 200 | static void ioapic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
610626af AL |
201 | { |
202 | IOAPICState *s = opaque; | |
203 | int index; | |
204 | ||
205 | addr &= 0xff; | |
206 | if (addr == 0x00) { | |
207 | s->ioregsel = val; | |
208 | return; | |
209 | } else if (addr == 0x10) { | |
9af9b330 | 210 | DPRINTF("write: %08x = %08x\n", s->ioregsel, val); |
610626af AL |
211 | switch (s->ioregsel) { |
212 | case 0x00: | |
213 | s->id = (val >> 24) & 0xff; | |
214 | return; | |
215 | case 0x01: | |
216 | case 0x02: | |
217 | return; | |
218 | default: | |
219 | index = (s->ioregsel - 0x10) >> 1; | |
220 | if (index >= 0 && index < IOAPIC_NUM_PINS) { | |
221 | if (s->ioregsel & 1) { | |
222 | s->ioredtbl[index] &= 0xffffffff; | |
223 | s->ioredtbl[index] |= (uint64_t)val << 32; | |
224 | } else { | |
225 | s->ioredtbl[index] &= ~0xffffffffULL; | |
226 | s->ioredtbl[index] |= val; | |
227 | } | |
228 | ioapic_service(s); | |
229 | } | |
230 | } | |
231 | } | |
232 | } | |
233 | ||
35a74c5c JK |
234 | static int ioapic_post_load(void *opaque, int version_id) |
235 | { | |
236 | IOAPICState *s = opaque; | |
237 | ||
238 | if (version_id == 1) { | |
239 | /* set sane value */ | |
240 | s->irr = 0; | |
241 | } | |
242 | return 0; | |
243 | } | |
244 | ||
3e9e9888 JQ |
245 | static const VMStateDescription vmstate_ioapic = { |
246 | .name = "ioapic", | |
5dce4999 | 247 | .version_id = 3, |
35a74c5c | 248 | .post_load = ioapic_post_load, |
3e9e9888 JQ |
249 | .minimum_version_id = 1, |
250 | .minimum_version_id_old = 1, | |
251 | .fields = (VMStateField []) { | |
252 | VMSTATE_UINT8(id, IOAPICState), | |
253 | VMSTATE_UINT8(ioregsel, IOAPICState), | |
5dce4999 | 254 | VMSTATE_UNUSED_V(2, 8), /* to account for qemu-kvm's v2 format */ |
35a74c5c | 255 | VMSTATE_UINT32_V(irr, IOAPICState, 2), |
3e9e9888 JQ |
256 | VMSTATE_UINT64_ARRAY(ioredtbl, IOAPICState, IOAPIC_NUM_PINS), |
257 | VMSTATE_END_OF_LIST() | |
610626af | 258 | } |
3e9e9888 | 259 | }; |
610626af | 260 | |
96051119 | 261 | static void ioapic_reset(DeviceState *d) |
610626af | 262 | { |
96051119 | 263 | IOAPICState *s = DO_UPCAST(IOAPICState, busdev.qdev, d); |
610626af AL |
264 | int i; |
265 | ||
96051119 BS |
266 | s->id = 0; |
267 | s->ioregsel = 0; | |
268 | s->irr = 0; | |
610626af AL |
269 | for(i = 0; i < IOAPIC_NUM_PINS; i++) |
270 | s->ioredtbl[i] = 1 << 16; /* mask LVT */ | |
271 | } | |
272 | ||
d60efc6b | 273 | static CPUReadMemoryFunc * const ioapic_mem_read[3] = { |
610626af AL |
274 | ioapic_mem_readl, |
275 | ioapic_mem_readl, | |
276 | ioapic_mem_readl, | |
277 | }; | |
278 | ||
d60efc6b | 279 | static CPUWriteMemoryFunc * const ioapic_mem_write[3] = { |
610626af AL |
280 | ioapic_mem_writel, |
281 | ioapic_mem_writel, | |
282 | ioapic_mem_writel, | |
283 | }; | |
284 | ||
96051119 | 285 | static int ioapic_init1(SysBusDevice *dev) |
610626af | 286 | { |
96051119 | 287 | IOAPICState *s = FROM_SYSBUS(IOAPICState, dev); |
610626af | 288 | int io_memory; |
0280b571 JK |
289 | static int ioapic_no; |
290 | ||
291 | if (ioapic_no >= MAX_IOAPICS) { | |
292 | return -1; | |
293 | } | |
610626af | 294 | |
1eed09cb | 295 | io_memory = cpu_register_io_memory(ioapic_mem_read, |
2507c12a AG |
296 | ioapic_mem_write, s, |
297 | DEVICE_NATIVE_ENDIAN); | |
96051119 | 298 | sysbus_init_mmio(dev, 0x1000, io_memory); |
610626af | 299 | |
96051119 | 300 | qdev_init_gpio_in(&dev->qdev, ioapic_set_irq, IOAPIC_NUM_PINS); |
610626af | 301 | |
0280b571 JK |
302 | ioapics[ioapic_no++] = s; |
303 | ||
96051119 | 304 | return 0; |
610626af | 305 | } |
96051119 BS |
306 | |
307 | static SysBusDeviceInfo ioapic_info = { | |
308 | .init = ioapic_init1, | |
309 | .qdev.name = "ioapic", | |
310 | .qdev.size = sizeof(IOAPICState), | |
311 | .qdev.vmsd = &vmstate_ioapic, | |
312 | .qdev.reset = ioapic_reset, | |
313 | .qdev.no_user = 1, | |
314 | }; | |
315 | ||
316 | static void ioapic_register_devices(void) | |
317 | { | |
318 | sysbus_register_withprop(&ioapic_info); | |
319 | } | |
320 | ||
321 | device_init(ioapic_register_devices) |