[mirror_qemu.git] / hw / iommu.c

/*
 * QEMU SPARC iommu emulation
 *
 * Copyright (c) 2003-2005 Fabrice Bellard
 * 
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "vl.h"

/* debug iommu */
//#define DEBUG_IOMMU

#ifdef DEBUG_IOMMU
#define DPRINTF(fmt, args...) \
do { printf("IOMMU: " fmt , ##args); } while (0)
#else
#define DPRINTF(fmt, args...)
#endif

#define IOMMU_NREGS (3*4096/4)
#define IOMMU_CTRL          (0x0000 >> 2)
#define IOMMU_CTRL_IMPL     0xf0000000 /* Implementation */
#define IOMMU_CTRL_VERS     0x0f000000 /* Version */
#define IOMMU_VERSION       0x04000000
#define IOMMU_CTRL_RNGE     0x0000001c /* Mapping RANGE */
#define IOMMU_RNGE_16MB     0x00000000 /* 0xff000000 -> 0xffffffff */
#define IOMMU_RNGE_32MB     0x00000004 /* 0xfe000000 -> 0xffffffff */
#define IOMMU_RNGE_64MB     0x00000008 /* 0xfc000000 -> 0xffffffff */
#define IOMMU_RNGE_128MB    0x0000000c /* 0xf8000000 -> 0xffffffff */
#define IOMMU_RNGE_256MB    0x00000010 /* 0xf0000000 -> 0xffffffff */
#define IOMMU_RNGE_512MB    0x00000014 /* 0xe0000000 -> 0xffffffff */
#define IOMMU_RNGE_1GB      0x00000018 /* 0xc0000000 -> 0xffffffff */
#define IOMMU_RNGE_2GB      0x0000001c /* 0x80000000 -> 0xffffffff */
#define IOMMU_CTRL_ENAB     0x00000001 /* IOMMU Enable */
#define IOMMU_CTRL_MASK     0x0000001d

#define IOMMU_BASE          (0x0004 >> 2)
#define IOMMU_BASE_MASK     0x07fffc00

#define IOMMU_TLBFLUSH      (0x0014 >> 2)
#define IOMMU_TLBFLUSH_MASK 0xffffffff

#define IOMMU_PGFLUSH       (0x0018 >> 2)
#define IOMMU_PGFLUSH_MASK  0xffffffff

#define IOMMU_SBCFG0        (0x1010 >> 2) /* SBUS configration per-slot */
#define IOMMU_SBCFG1        (0x1014 >> 2) /* SBUS configration per-slot */
#define IOMMU_SBCFG2        (0x1018 >> 2) /* SBUS configration per-slot */
#define IOMMU_SBCFG3        (0x101c >> 2) /* SBUS configration per-slot */
#define IOMMU_SBCFG_SAB30   0x00010000 /* Phys-address bit 30 when bypass enabled */
#define IOMMU_SBCFG_BA16    0x00000004 /* Slave supports 16 byte bursts */
#define IOMMU_SBCFG_BA8     0x00000002 /* Slave supports 8 byte bursts */
#define IOMMU_SBCFG_BYPASS  0x00000001 /* Bypass IOMMU, treat all addresses
       	                                  produced by this device as pure
                                          physical. */
#define IOMMU_SBCFG_MASK    0x00010003

#define IOMMU_ARBEN         (0x2000 >> 2) /* SBUS arbitration enable */
#define IOMMU_ARBEN_MASK    0x001f0000
#define IOMMU_MID           0x00000008

/* The format of an iopte in the page tables */
#define IOPTE_PAGE          0x07ffff00 /* Physical page number (PA[30:12]) */
#define IOPTE_CACHE         0x00000080 /* Cached (in vme IOCACHE or Viking/MXCC) */
#define IOPTE_WRITE         0x00000004 /* Writeable */
#define IOPTE_VALID         0x00000002 /* IOPTE is valid */
#define IOPTE_WAZ           0x00000001 /* Write as zeros */

#define PAGE_SHIFT      12
#define PAGE_SIZE       (1 << PAGE_SHIFT)
#define PAGE_MASK	(PAGE_SIZE - 1)

typedef struct IOMMUState {
    target_phys_addr_t addr;
    uint32_t regs[IOMMU_NREGS];
    target_phys_addr_t iostart;
} IOMMUState;

static uint32_t iommu_mem_readw(void *opaque, target_phys_addr_t addr)
{
    IOMMUState *s = opaque;
    target_phys_addr_t saddr;

    saddr = (addr - s->addr) >> 2;
    switch (saddr) {
    default:
	DPRINTF("read reg[%d] = %x\n", saddr, s->regs[saddr]);
	return s->regs[saddr];
	break;
    }
    return 0;
}

static void iommu_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
{
    IOMMUState *s = opaque;
    target_phys_addr_t saddr;

    saddr = (addr - s->addr) >> 2;
    DPRINTF("write reg[%d] = %x\n", saddr, val);
    switch (saddr) {
    case IOMMU_CTRL:
	switch (val & IOMMU_CTRL_RNGE) {
	case IOMMU_RNGE_16MB:
	    s->iostart = 0xffffffffff000000ULL;
	    break;
	case IOMMU_RNGE_32MB:
	    s->iostart = 0xfffffffffe000000ULL;
	    break;
	case IOMMU_RNGE_64MB:
	    s->iostart = 0xfffffffffc000000ULL;
	    break;
	case IOMMU_RNGE_128MB:
	    s->iostart = 0xfffffffff8000000ULL;
	    break;
	case IOMMU_RNGE_256MB:
	    s->iostart = 0xfffffffff0000000ULL;
	    break;
	case IOMMU_RNGE_512MB:
	    s->iostart = 0xffffffffe0000000ULL;
	    break;
	case IOMMU_RNGE_1GB:
	    s->iostart = 0xffffffffc0000000ULL;
	    break;
	default:
	case IOMMU_RNGE_2GB:
	    s->iostart = 0xffffffff80000000ULL;
	    break;
	}
	DPRINTF("iostart = %llx\n", s->iostart);
	s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | IOMMU_VERSION);
	break;
    case IOMMU_BASE:
	s->regs[saddr] = val & IOMMU_BASE_MASK;
	break;
    case IOMMU_TLBFLUSH:
	DPRINTF("tlb flush %x\n", val);
	s->regs[saddr] = val & IOMMU_TLBFLUSH_MASK;
	break;
    case IOMMU_PGFLUSH:
	DPRINTF("page flush %x\n", val);
	s->regs[saddr] = val & IOMMU_PGFLUSH_MASK;
	break;
    case IOMMU_SBCFG0:
    case IOMMU_SBCFG1:
    case IOMMU_SBCFG2:
    case IOMMU_SBCFG3:
	s->regs[saddr] = val & IOMMU_SBCFG_MASK;
	break;
    case IOMMU_ARBEN:
        // XXX implement SBus probing: fault when reading unmapped
        // addresses, fault cause and address stored to MMU/IOMMU
	s->regs[saddr] = (val & IOMMU_ARBEN_MASK) | IOMMU_MID;
	break;
    default:
	s->regs[saddr] = val;
	break;
    }
}

static CPUReadMemoryFunc *iommu_mem_read[3] = {
    iommu_mem_readw,
    iommu_mem_readw,
    iommu_mem_readw,
};

static CPUWriteMemoryFunc *iommu_mem_write[3] = {
    iommu_mem_writew,
    iommu_mem_writew,
    iommu_mem_writew,
};

static uint32_t iommu_page_get_flags(IOMMUState *s, target_phys_addr_t addr)
{
    uint32_t iopte;

    iopte = s->regs[1] << 4;
    addr &= ~s->iostart;
    iopte += (addr >> (PAGE_SHIFT - 2)) & ~3;
    return ldl_phys(iopte);
}

static target_phys_addr_t iommu_translate_pa(IOMMUState *s,
                                             target_phys_addr_t addr,
                                             uint32_t pte)
{
    uint32_t tmppte;
    target_phys_addr_t pa;

    tmppte = pte;
    pa = ((pte & IOPTE_PAGE) << 4) + (addr & PAGE_MASK);
    DPRINTF("xlate dva " TARGET_FMT_plx " => pa " TARGET_FMT_plx
            " (iopte = %x)\n", addr, pa, tmppte);

    return pa;
}

void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
                           uint8_t *buf, int len, int is_write)
{
    int l;
    uint32_t flags;
    target_phys_addr_t page, phys_addr;

    while (len > 0) {
        page = addr & TARGET_PAGE_MASK;
        l = (page + TARGET_PAGE_SIZE) - addr;
        if (l > len)
            l = len;
        flags = iommu_page_get_flags(opaque, page);
        if (!(flags & IOPTE_VALID))
            return;
        phys_addr = iommu_translate_pa(opaque, addr, flags);
        if (is_write) {
            if (!(flags & IOPTE_WRITE))
                return;
            cpu_physical_memory_write(phys_addr, buf, len);
        } else {
            cpu_physical_memory_read(phys_addr, buf, len);
        }
        len -= l;
        buf += l;
        addr += l;
    }
}

static void iommu_save(QEMUFile *f, void *opaque)
{
    IOMMUState *s = opaque;
    int i;
    
    for (i = 0; i < IOMMU_NREGS; i++)
	qemu_put_be32s(f, &s->regs[i]);
    qemu_put_be64s(f, &s->iostart);
}

static int iommu_load(QEMUFile *f, void *opaque, int version_id)
{
    IOMMUState *s = opaque;
    int i;
    
    if (version_id != 2)
        return -EINVAL;

    for (i = 0; i < IOMMU_NREGS; i++)
        qemu_get_be32s(f, &s->regs[i]);
    qemu_get_be64s(f, &s->iostart);

    return 0;
}

static void iommu_reset(void *opaque)
{
    IOMMUState *s = opaque;

    memset(s->regs, 0, IOMMU_NREGS * 4);
    s->iostart = 0;
    s->regs[0] = IOMMU_VERSION;
}

void *iommu_init(target_phys_addr_t addr)
{
    IOMMUState *s;
    int iommu_io_memory;

    s = qemu_mallocz(sizeof(IOMMUState));
    if (!s)
        return NULL;

    s->addr = addr;

    iommu_io_memory = cpu_register_io_memory(0, iommu_mem_read, iommu_mem_write, s);
    cpu_register_physical_memory(addr, IOMMU_NREGS * 4, iommu_io_memory);
    
    register_savevm("iommu", addr, 2, iommu_save, iommu_load, s);
    qemu_register_reset(iommu_reset, s);
    return s;
}
Commit	Line	Data
420557e8 FB	1	/*
	2	* QEMU SPARC iommu emulation
	3	*
66321a11	4	* Copyright (c) 2003-2005 Fabrice Bellard
420557e8 FB	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24	#include "vl.h"
	25
	26	/* debug iommu */
	27	//#define DEBUG_IOMMU
	28
66321a11 FB	29	#ifdef DEBUG_IOMMU
	30	#define DPRINTF(fmt, args...) \
	31	do { printf("IOMMU: " fmt , ##args); } while (0)
	32	#else
	33	#define DPRINTF(fmt, args...)
	34	#endif
420557e8	35
4e3b1ea1 FB	36	#define IOMMU_NREGS (3*4096/4)
4e3b1ea1 FB	37	#define IOMMU_CTRL (0x0000 >> 2)
420557e8 FB	38	#define IOMMU_CTRL_IMPL 0xf0000000 /* Implementation */
420557e8 FB	39	#define IOMMU_CTRL_VERS 0x0f000000 /* Version */
4e3b1ea1	40	#define IOMMU_VERSION 0x04000000
420557e8 FB	41	#define IOMMU_CTRL_RNGE 0x0000001c /* Mapping RANGE */
	42	#define IOMMU_RNGE_16MB 0x00000000 /* 0xff000000 -> 0xffffffff */
	43	#define IOMMU_RNGE_32MB 0x00000004 /* 0xfe000000 -> 0xffffffff */
	44	#define IOMMU_RNGE_64MB 0x00000008 /* 0xfc000000 -> 0xffffffff */
	45	#define IOMMU_RNGE_128MB 0x0000000c /* 0xf8000000 -> 0xffffffff */
	46	#define IOMMU_RNGE_256MB 0x00000010 /* 0xf0000000 -> 0xffffffff */
	47	#define IOMMU_RNGE_512MB 0x00000014 /* 0xe0000000 -> 0xffffffff */
	48	#define IOMMU_RNGE_1GB 0x00000018 /* 0xc0000000 -> 0xffffffff */
	49	#define IOMMU_RNGE_2GB 0x0000001c /* 0x80000000 -> 0xffffffff */
	50	#define IOMMU_CTRL_ENAB 0x00000001 /* IOMMU Enable */
4e3b1ea1 FB	51	#define IOMMU_CTRL_MASK 0x0000001d
	52
	53	#define IOMMU_BASE (0x0004 >> 2)
	54	#define IOMMU_BASE_MASK 0x07fffc00
	55
	56	#define IOMMU_TLBFLUSH (0x0014 >> 2)
	57	#define IOMMU_TLBFLUSH_MASK 0xffffffff
	58
	59	#define IOMMU_PGFLUSH (0x0018 >> 2)
	60	#define IOMMU_PGFLUSH_MASK 0xffffffff
	61
	62	#define IOMMU_SBCFG0 (0x1010 >> 2) /* SBUS configration per-slot */
	63	#define IOMMU_SBCFG1 (0x1014 >> 2) /* SBUS configration per-slot */
	64	#define IOMMU_SBCFG2 (0x1018 >> 2) /* SBUS configration per-slot */
	65	#define IOMMU_SBCFG3 (0x101c >> 2) /* SBUS configration per-slot */
	66	#define IOMMU_SBCFG_SAB30 0x00010000 /* Phys-address bit 30 when bypass enabled */
	67	#define IOMMU_SBCFG_BA16 0x00000004 /* Slave supports 16 byte bursts */
	68	#define IOMMU_SBCFG_BA8 0x00000002 /* Slave supports 8 byte bursts */
	69	#define IOMMU_SBCFG_BYPASS 0x00000001 /* Bypass IOMMU, treat all addresses
	70	produced by this device as pure
	71	physical. */
	72	#define IOMMU_SBCFG_MASK 0x00010003
	73
	74	#define IOMMU_ARBEN (0x2000 >> 2) /* SBUS arbitration enable */
	75	#define IOMMU_ARBEN_MASK 0x001f0000
	76	#define IOMMU_MID 0x00000008
420557e8	77
420557e8 FB	78	/* The format of an iopte in the page tables */
	79	#define IOPTE_PAGE 0x07ffff00 /* Physical page number (PA[30:12]) */
	80	#define IOPTE_CACHE 0x00000080 /* Cached (in vme IOCACHE or Viking/MXCC) */
	81	#define IOPTE_WRITE 0x00000004 /* Writeable */
	82	#define IOPTE_VALID 0x00000002 /* IOPTE is valid */
	83	#define IOPTE_WAZ 0x00000001 /* Write as zeros */
	84
420557e8 FB	85	#define PAGE_SHIFT 12
	86	#define PAGE_SIZE (1 << PAGE_SHIFT)
	87	#define PAGE_MASK (PAGE_SIZE - 1)
	88
	89	typedef struct IOMMUState {
5dcb6b91	90	target_phys_addr_t addr;
66321a11	91	uint32_t regs[IOMMU_NREGS];
5dcb6b91	92	target_phys_addr_t iostart;
420557e8 FB	93	} IOMMUState;
420557e8 FB	94
420557e8 FB	95	static uint32_t iommu_mem_readw(void *opaque, target_phys_addr_t addr)
	96	{
	97	IOMMUState *s = opaque;
5dcb6b91	98	target_phys_addr_t saddr;
420557e8	99
8d5f07fa	100	saddr = (addr - s->addr) >> 2;
420557e8 FB	101	switch (saddr) {
420557e8 FB	102	default:
66321a11	103	DPRINTF("read reg[%d] = %x\n", saddr, s->regs[saddr]);
420557e8 FB	104	return s->regs[saddr];
	105	break;
	106	}
	107	return 0;
	108	}
	109
	110	static void iommu_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
	111	{
	112	IOMMUState *s = opaque;
5dcb6b91	113	target_phys_addr_t saddr;
420557e8	114
8d5f07fa	115	saddr = (addr - s->addr) >> 2;
66321a11	116	DPRINTF("write reg[%d] = %x\n", saddr, val);
420557e8	117	switch (saddr) {
4e3b1ea1	118	case IOMMU_CTRL:
8d5f07fa FB	119	switch (val & IOMMU_CTRL_RNGE) {
8d5f07fa FB	120	case IOMMU_RNGE_16MB:
5dcb6b91	121	s->iostart = 0xffffffffff000000ULL;
8d5f07fa FB	122	break;
8d5f07fa FB	123	case IOMMU_RNGE_32MB:
5dcb6b91	124	s->iostart = 0xfffffffffe000000ULL;
8d5f07fa FB	125	break;
8d5f07fa FB	126	case IOMMU_RNGE_64MB:
5dcb6b91	127	s->iostart = 0xfffffffffc000000ULL;
8d5f07fa FB	128	break;
8d5f07fa FB	129	case IOMMU_RNGE_128MB:
5dcb6b91	130	s->iostart = 0xfffffffff8000000ULL;
8d5f07fa FB	131	break;
8d5f07fa FB	132	case IOMMU_RNGE_256MB:
5dcb6b91	133	s->iostart = 0xfffffffff0000000ULL;
8d5f07fa FB	134	break;
8d5f07fa FB	135	case IOMMU_RNGE_512MB:
5dcb6b91	136	s->iostart = 0xffffffffe0000000ULL;
8d5f07fa FB	137	break;
8d5f07fa FB	138	case IOMMU_RNGE_1GB:
5dcb6b91	139	s->iostart = 0xffffffffc0000000ULL;
8d5f07fa FB	140	break;
	141	default:
	142	case IOMMU_RNGE_2GB:
5dcb6b91	143	s->iostart = 0xffffffff80000000ULL;
8d5f07fa FB	144	break;
8d5f07fa FB	145	}
5dcb6b91	146	DPRINTF("iostart = %llx\n", s->iostart);
4e3b1ea1 FB	147	s->regs[saddr] = ((val & IOMMU_CTRL_MASK) \| IOMMU_VERSION);
	148	break;
	149	case IOMMU_BASE:
	150	s->regs[saddr] = val & IOMMU_BASE_MASK;
	151	break;
	152	case IOMMU_TLBFLUSH:
	153	DPRINTF("tlb flush %x\n", val);
	154	s->regs[saddr] = val & IOMMU_TLBFLUSH_MASK;
	155	break;
	156	case IOMMU_PGFLUSH:
	157	DPRINTF("page flush %x\n", val);
	158	s->regs[saddr] = val & IOMMU_PGFLUSH_MASK;
	159	break;
	160	case IOMMU_SBCFG0:
	161	case IOMMU_SBCFG1:
	162	case IOMMU_SBCFG2:
	163	case IOMMU_SBCFG3:
	164	s->regs[saddr] = val & IOMMU_SBCFG_MASK;
	165	break;
	166	case IOMMU_ARBEN:
	167	// XXX implement SBus probing: fault when reading unmapped
	168	// addresses, fault cause and address stored to MMU/IOMMU
	169	s->regs[saddr] = (val & IOMMU_ARBEN_MASK) \| IOMMU_MID;
	170	break;
420557e8 FB	171	default:
	172	s->regs[saddr] = val;
	173	break;
	174	}
	175	}
	176
	177	static CPUReadMemoryFunc *iommu_mem_read[3] = {
	178	iommu_mem_readw,
	179	iommu_mem_readw,
	180	iommu_mem_readw,
	181	};
	182
	183	static CPUWriteMemoryFunc *iommu_mem_write[3] = {
	184	iommu_mem_writew,
	185	iommu_mem_writew,
	186	iommu_mem_writew,
	187	};
	188
5dcb6b91	189	static uint32_t iommu_page_get_flags(IOMMUState *s, target_phys_addr_t addr)
420557e8	190	{
a917d384	191	uint32_t iopte;
420557e8	192
66321a11 FB	193	iopte = s->regs[1] << 4;
	194	addr &= ~s->iostart;
	195	iopte += (addr >> (PAGE_SHIFT - 2)) & ~3;
a917d384 PB	196	return ldl_phys(iopte);
	197	}
	198
5dcb6b91 BS	199	static target_phys_addr_t iommu_translate_pa(IOMMUState *s,
	200	target_phys_addr_t addr,
	201	uint32_t pte)
a917d384 PB	202	{
a917d384 PB	203	uint32_t tmppte;
5dcb6b91 BS	204	target_phys_addr_t pa;
	205
	206	tmppte = pte;
	207	pa = ((pte & IOPTE_PAGE) << 4) + (addr & PAGE_MASK);
	208	DPRINTF("xlate dva " TARGET_FMT_plx " => pa " TARGET_FMT_plx
	209	" (iopte = %x)\n", addr, pa, tmppte);
a917d384	210
66321a11	211	return pa;
420557e8 FB	212	}
420557e8 FB	213
67e999be FB	214	void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
67e999be FB	215	uint8_t *buf, int len, int is_write)
a917d384	216	{
5dcb6b91 BS	217	int l;
	218	uint32_t flags;
	219	target_phys_addr_t page, phys_addr;
a917d384 PB	220
	221	while (len > 0) {
	222	page = addr & TARGET_PAGE_MASK;
	223	l = (page + TARGET_PAGE_SIZE) - addr;
	224	if (l > len)
	225	l = len;
	226	flags = iommu_page_get_flags(opaque, page);
	227	if (!(flags & IOPTE_VALID))
	228	return;
	229	phys_addr = iommu_translate_pa(opaque, addr, flags);
	230	if (is_write) {
	231	if (!(flags & IOPTE_WRITE))
	232	return;
	233	cpu_physical_memory_write(phys_addr, buf, len);
	234	} else {
	235	cpu_physical_memory_read(phys_addr, buf, len);
	236	}
	237	len -= l;
	238	buf += l;
	239	addr += l;
	240	}
	241	}
	242
e80cfcfc FB	243	static void iommu_save(QEMUFile f, void opaque)
	244	{
	245	IOMMUState *s = opaque;
	246	int i;
	247
66321a11	248	for (i = 0; i < IOMMU_NREGS; i++)
e80cfcfc	249	qemu_put_be32s(f, &s->regs[i]);
5dcb6b91	250	qemu_put_be64s(f, &s->iostart);
e80cfcfc FB	251	}
	252
	253	static int iommu_load(QEMUFile f, void opaque, int version_id)
	254	{
	255	IOMMUState *s = opaque;
	256	int i;
	257
5dcb6b91	258	if (version_id != 2)
e80cfcfc FB	259	return -EINVAL;
e80cfcfc FB	260
66321a11	261	for (i = 0; i < IOMMU_NREGS; i++)
fda77c2d	262	qemu_get_be32s(f, &s->regs[i]);
5dcb6b91	263	qemu_get_be64s(f, &s->iostart);
e80cfcfc FB	264
	265	return 0;
	266	}
	267
	268	static void iommu_reset(void *opaque)
	269	{
	270	IOMMUState *s = opaque;
	271
66321a11	272	memset(s->regs, 0, IOMMU_NREGS * 4);
e80cfcfc	273	s->iostart = 0;
4e3b1ea1	274	s->regs[0] = IOMMU_VERSION;
e80cfcfc FB	275	}
e80cfcfc FB	276
5dcb6b91	277	void *iommu_init(target_phys_addr_t addr)
420557e8 FB	278	{
420557e8 FB	279	IOMMUState *s;
8d5f07fa	280	int iommu_io_memory;
420557e8 FB	281
	282	s = qemu_mallocz(sizeof(IOMMUState));
	283	if (!s)
e80cfcfc	284	return NULL;
420557e8	285
8d5f07fa FB	286	s->addr = addr;
8d5f07fa FB	287
420557e8	288	iommu_io_memory = cpu_register_io_memory(0, iommu_mem_read, iommu_mem_write, s);
66321a11	289	cpu_register_physical_memory(addr, IOMMU_NREGS * 4, iommu_io_memory);
420557e8	290
5dcb6b91	291	register_savevm("iommu", addr, 2, iommu_save, iommu_load, s);
e80cfcfc FB	292	qemu_register_reset(iommu_reset, s);
e80cfcfc FB	293	return s;
420557e8 FB	294	}
420557e8 FB	295