[mirror_qemu.git] / hw / iommu.c

/*
 * QEMU SPARC iommu emulation
 *
 * Copyright (c) 2003 Fabrice Bellard
 * 
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "vl.h"

/* debug iommu */
//#define DEBUG_IOMMU

/* The IOMMU registers occupy three pages in IO space. */
struct iommu_regs {
	/* First page */
	volatile unsigned long control;    /* IOMMU control */
	volatile unsigned long base;       /* Physical base of iopte page table */
	volatile unsigned long _unused1[3];
	volatile unsigned long tlbflush;   /* write only */
	volatile unsigned long pageflush;  /* write only */
	volatile unsigned long _unused2[1017];
	/* Second page */
	volatile unsigned long afsr;       /* Async-fault status register */
	volatile unsigned long afar;       /* Async-fault physical address */
	volatile unsigned long _unused3[2];
	volatile unsigned long sbuscfg0;   /* SBUS configuration registers, per-slot */
	volatile unsigned long sbuscfg1;
	volatile unsigned long sbuscfg2;
	volatile unsigned long sbuscfg3;
	volatile unsigned long mfsr;       /* Memory-fault status register */
	volatile unsigned long mfar;       /* Memory-fault physical address */
	volatile unsigned long _unused4[1014];
	/* Third page */
	volatile unsigned long mid;        /* IOMMU module-id */
};

#define IOMMU_CTRL_IMPL     0xf0000000 /* Implementation */
#define IOMMU_CTRL_VERS     0x0f000000 /* Version */
#define IOMMU_CTRL_RNGE     0x0000001c /* Mapping RANGE */
#define IOMMU_RNGE_16MB     0x00000000 /* 0xff000000 -> 0xffffffff */
#define IOMMU_RNGE_32MB     0x00000004 /* 0xfe000000 -> 0xffffffff */
#define IOMMU_RNGE_64MB     0x00000008 /* 0xfc000000 -> 0xffffffff */
#define IOMMU_RNGE_128MB    0x0000000c /* 0xf8000000 -> 0xffffffff */
#define IOMMU_RNGE_256MB    0x00000010 /* 0xf0000000 -> 0xffffffff */
#define IOMMU_RNGE_512MB    0x00000014 /* 0xe0000000 -> 0xffffffff */
#define IOMMU_RNGE_1GB      0x00000018 /* 0xc0000000 -> 0xffffffff */
#define IOMMU_RNGE_2GB      0x0000001c /* 0x80000000 -> 0xffffffff */
#define IOMMU_CTRL_ENAB     0x00000001 /* IOMMU Enable */

#define IOMMU_AFSR_ERR      0x80000000 /* LE, TO, or BE asserted */
#define IOMMU_AFSR_LE       0x40000000 /* SBUS reports error after transaction */
#define IOMMU_AFSR_TO       0x20000000 /* Write access took more than 12.8 us. */
#define IOMMU_AFSR_BE       0x10000000 /* Write access received error acknowledge */
#define IOMMU_AFSR_SIZE     0x0e000000 /* Size of transaction causing error */
#define IOMMU_AFSR_S        0x01000000 /* Sparc was in supervisor mode */
#define IOMMU_AFSR_RESV     0x00f00000 /* Reserver, forced to 0x8 by hardware */
#define IOMMU_AFSR_ME       0x00080000 /* Multiple errors occurred */
#define IOMMU_AFSR_RD       0x00040000 /* A read operation was in progress */
#define IOMMU_AFSR_FAV      0x00020000 /* IOMMU afar has valid contents */

#define IOMMU_SBCFG_SAB30   0x00010000 /* Phys-address bit 30 when bypass enabled */
#define IOMMU_SBCFG_BA16    0x00000004 /* Slave supports 16 byte bursts */
#define IOMMU_SBCFG_BA8     0x00000002 /* Slave supports 8 byte bursts */
#define IOMMU_SBCFG_BYPASS  0x00000001 /* Bypass IOMMU, treat all addresses
					  produced by this device as pure
					  physical. */

#define IOMMU_MFSR_ERR      0x80000000 /* One or more of PERR1 or PERR0 */
#define IOMMU_MFSR_S        0x01000000 /* Sparc was in supervisor mode */
#define IOMMU_MFSR_CPU      0x00800000 /* CPU transaction caused parity error */
#define IOMMU_MFSR_ME       0x00080000 /* Multiple parity errors occurred */
#define IOMMU_MFSR_PERR     0x00006000 /* high bit indicates parity error occurred
					  on the even word of the access, low bit
					  indicated odd word caused the parity error */
#define IOMMU_MFSR_BM       0x00001000 /* Error occurred while in boot mode */
#define IOMMU_MFSR_C        0x00000800 /* Address causing error was marked cacheable */
#define IOMMU_MFSR_RTYP     0x000000f0 /* Memory request transaction type */

#define IOMMU_MID_SBAE      0x001f0000 /* SBus arbitration enable */
#define IOMMU_MID_SE        0x00100000 /* Enables SCSI/ETHERNET arbitration */
#define IOMMU_MID_SB3       0x00080000 /* Enable SBUS device 3 arbitration */
#define IOMMU_MID_SB2       0x00040000 /* Enable SBUS device 2 arbitration */
#define IOMMU_MID_SB1       0x00020000 /* Enable SBUS device 1 arbitration */
#define IOMMU_MID_SB0       0x00010000 /* Enable SBUS device 0 arbitration */
#define IOMMU_MID_MID       0x0000000f /* Module-id, hardcoded to 0x8 */

/* The format of an iopte in the page tables */
#define IOPTE_PAGE          0x07ffff00 /* Physical page number (PA[30:12]) */
#define IOPTE_CACHE         0x00000080 /* Cached (in vme IOCACHE or Viking/MXCC) */
#define IOPTE_WRITE         0x00000004 /* Writeable */
#define IOPTE_VALID         0x00000002 /* IOPTE is valid */
#define IOPTE_WAZ           0x00000001 /* Write as zeros */

#define PAGE_SHIFT      12
#define PAGE_SIZE       (1 << PAGE_SHIFT)
#define PAGE_MASK	(PAGE_SIZE - 1)

typedef struct IOMMUState {
    uint32_t addr;
    uint32_t regs[sizeof(struct iommu_regs)];
    uint32_t iostart;
} IOMMUState;

static uint32_t iommu_mem_readw(void *opaque, target_phys_addr_t addr)
{
    IOMMUState *s = opaque;
    uint32_t saddr;

    saddr = (addr - s->addr) >> 2;
    switch (saddr) {
    default:
	return s->regs[saddr];
	break;
    }
    return 0;
}

static void iommu_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
{
    IOMMUState *s = opaque;
    uint32_t saddr;

    saddr = (addr - s->addr) >> 2;
    switch (saddr) {
    case 0:
	switch (val & IOMMU_CTRL_RNGE) {
	case IOMMU_RNGE_16MB:
	    s->iostart = 0xff000000;
	    break;
	case IOMMU_RNGE_32MB:
	    s->iostart = 0xfe000000;
	    break;
	case IOMMU_RNGE_64MB:
	    s->iostart = 0xfc000000;
	    break;
	case IOMMU_RNGE_128MB:
	    s->iostart = 0xf8000000;
	    break;
	case IOMMU_RNGE_256MB:
	    s->iostart = 0xf0000000;
	    break;
	case IOMMU_RNGE_512MB:
	    s->iostart = 0xe0000000;
	    break;
	case IOMMU_RNGE_1GB:
	    s->iostart = 0xc0000000;
	    break;
	default:
	case IOMMU_RNGE_2GB:
	    s->iostart = 0x80000000;
	    break;
	}
	/* Fall through */
    default:
	s->regs[saddr] = val;
	break;
    }
}

static CPUReadMemoryFunc *iommu_mem_read[3] = {
    iommu_mem_readw,
    iommu_mem_readw,
    iommu_mem_readw,
};

static CPUWriteMemoryFunc *iommu_mem_write[3] = {
    iommu_mem_writew,
    iommu_mem_writew,
    iommu_mem_writew,
};

uint32_t iommu_translate_local(void *opaque, uint32_t addr)
{
    IOMMUState *s = opaque;
    uint32_t *iopte = (void *)(s->regs[1] << 4), pa;

    iopte += ((addr - s->iostart) >> PAGE_SHIFT);
    cpu_physical_memory_read((uint32_t)iopte, (void *) &pa, 4);
    bswap32s(&pa);
    pa = (pa & IOPTE_PAGE) << 4;		/* Loose higher bits of 36 */
    return pa + (addr & PAGE_MASK);
}

static void iommu_save(QEMUFile *f, void *opaque)
{
    IOMMUState *s = opaque;
    int i;
    
    qemu_put_be32s(f, &s->addr);
    for (i = 0; i < sizeof(struct iommu_regs); i += 4)
	qemu_put_be32s(f, &s->regs[i]);
    qemu_put_be32s(f, &s->iostart);
}

static int iommu_load(QEMUFile *f, void *opaque, int version_id)
{
    IOMMUState *s = opaque;
    int i;
    
    if (version_id != 1)
        return -EINVAL;

    qemu_get_be32s(f, &s->addr);
    for (i = 0; i < sizeof(struct iommu_regs); i += 4)
	qemu_put_be32s(f, &s->regs[i]);
    qemu_get_be32s(f, &s->iostart);

    return 0;
}

static void iommu_reset(void *opaque)
{
    IOMMUState *s = opaque;

    memset(s->regs, 0, sizeof(struct iommu_regs));
    s->iostart = 0;
}

void *iommu_init(uint32_t addr)
{
    IOMMUState *s;
    int iommu_io_memory;

    s = qemu_mallocz(sizeof(IOMMUState));
    if (!s)
        return NULL;

    s->addr = addr;

    iommu_io_memory = cpu_register_io_memory(0, iommu_mem_read, iommu_mem_write, s);
    cpu_register_physical_memory(addr, sizeof(struct iommu_regs),
                                 iommu_io_memory);
    
    register_savevm("iommu", addr, 1, iommu_save, iommu_load, s);
    qemu_register_reset(iommu_reset, s);
    return s;
}
Commit	Line	Data
420557e8 FB	1	/*
	2	* QEMU SPARC iommu emulation
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24	#include "vl.h"
	25
	26	/* debug iommu */
	27	//#define DEBUG_IOMMU
	28
	29	/* The IOMMU registers occupy three pages in IO space. */
	30	struct iommu_regs {
	31	/* First page */
	32	volatile unsigned long control; /* IOMMU control */
	33	volatile unsigned long base; /* Physical base of iopte page table */
	34	volatile unsigned long _unused1[3];
	35	volatile unsigned long tlbflush; /* write only */
	36	volatile unsigned long pageflush; /* write only */
	37	volatile unsigned long _unused2[1017];
	38	/* Second page */
	39	volatile unsigned long afsr; /* Async-fault status register */
	40	volatile unsigned long afar; /* Async-fault physical address */
	41	volatile unsigned long _unused3[2];
	42	volatile unsigned long sbuscfg0; /* SBUS configuration registers, per-slot */
	43	volatile unsigned long sbuscfg1;
	44	volatile unsigned long sbuscfg2;
	45	volatile unsigned long sbuscfg3;
	46	volatile unsigned long mfsr; /* Memory-fault status register */
	47	volatile unsigned long mfar; /* Memory-fault physical address */
	48	volatile unsigned long _unused4[1014];
	49	/* Third page */
	50	volatile unsigned long mid; /* IOMMU module-id */
	51	};
	52
	53	#define IOMMU_CTRL_IMPL 0xf0000000 /* Implementation */
	54	#define IOMMU_CTRL_VERS 0x0f000000 /* Version */
	55	#define IOMMU_CTRL_RNGE 0x0000001c /* Mapping RANGE */
	56	#define IOMMU_RNGE_16MB 0x00000000 /* 0xff000000 -> 0xffffffff */
	57	#define IOMMU_RNGE_32MB 0x00000004 /* 0xfe000000 -> 0xffffffff */
	58	#define IOMMU_RNGE_64MB 0x00000008 /* 0xfc000000 -> 0xffffffff */
	59	#define IOMMU_RNGE_128MB 0x0000000c /* 0xf8000000 -> 0xffffffff */
	60	#define IOMMU_RNGE_256MB 0x00000010 /* 0xf0000000 -> 0xffffffff */
	61	#define IOMMU_RNGE_512MB 0x00000014 /* 0xe0000000 -> 0xffffffff */
	62	#define IOMMU_RNGE_1GB 0x00000018 /* 0xc0000000 -> 0xffffffff */
	63	#define IOMMU_RNGE_2GB 0x0000001c /* 0x80000000 -> 0xffffffff */
	64	#define IOMMU_CTRL_ENAB 0x00000001 /* IOMMU Enable */
65
66	#define IOMMU_AFSR_ERR 0x80000000 /* LE, TO, or BE asserted */
67	#define IOMMU_AFSR_LE 0x40000000 /* SBUS reports error after transaction */
68	#define IOMMU_AFSR_TO 0x20000000 /* Write access took more than 12.8 us. */
69	#define IOMMU_AFSR_BE 0x10000000 /* Write access received error acknowledge */
70	#define IOMMU_AFSR_SIZE 0x0e000000 /* Size of transaction causing error */
71	#define IOMMU_AFSR_S 0x01000000 /* Sparc was in supervisor mode */
72	#define IOMMU_AFSR_RESV 0x00f00000 /* Reserver, forced to 0x8 by hardware */
73	#define IOMMU_AFSR_ME 0x00080000 /* Multiple errors occurred */
74	#define IOMMU_AFSR_RD 0x00040000 /* A read operation was in progress */
75	#define IOMMU_AFSR_FAV 0x00020000 /* IOMMU afar has valid contents */
76
77	#define IOMMU_SBCFG_SAB30 0x00010000 /* Phys-address bit 30 when bypass enabled */
78	#define IOMMU_SBCFG_BA16 0x00000004 /* Slave supports 16 byte bursts */
79	#define IOMMU_SBCFG_BA8 0x00000002 /* Slave supports 8 byte bursts */
80	#define IOMMU_SBCFG_BYPASS 0x00000001 /* Bypass IOMMU, treat all addresses
81	produced by this device as pure
82	physical. */
83
84	#define IOMMU_MFSR_ERR 0x80000000 /* One or more of PERR1 or PERR0 */
85	#define IOMMU_MFSR_S 0x01000000 /* Sparc was in supervisor mode */
86	#define IOMMU_MFSR_CPU 0x00800000 /* CPU transaction caused parity error */
87	#define IOMMU_MFSR_ME 0x00080000 /* Multiple parity errors occurred */
88	#define IOMMU_MFSR_PERR 0x00006000 /* high bit indicates parity error occurred
89	on the even word of the access, low bit
90	indicated odd word caused the parity error */
91	#define IOMMU_MFSR_BM 0x00001000 /* Error occurred while in boot mode */
92	#define IOMMU_MFSR_C 0x00000800 /* Address causing error was marked cacheable */
93	#define IOMMU_MFSR_RTYP 0x000000f0 /* Memory request transaction type */
94
95	#define IOMMU_MID_SBAE 0x001f0000 /* SBus arbitration enable */
96	#define IOMMU_MID_SE 0x00100000 /* Enables SCSI/ETHERNET arbitration */
97	#define IOMMU_MID_SB3 0x00080000 /* Enable SBUS device 3 arbitration */
98	#define IOMMU_MID_SB2 0x00040000 /* Enable SBUS device 2 arbitration */
99	#define IOMMU_MID_SB1 0x00020000 /* Enable SBUS device 1 arbitration */
100	#define IOMMU_MID_SB0 0x00010000 /* Enable SBUS device 0 arbitration */
101	#define IOMMU_MID_MID 0x0000000f /* Module-id, hardcoded to 0x8 */
102
103	/* The format of an iopte in the page tables */
104	#define IOPTE_PAGE 0x07ffff00 /* Physical page number (PA[30:12]) */
105	#define IOPTE_CACHE 0x00000080 /* Cached (in vme IOCACHE or Viking/MXCC) */
106	#define IOPTE_WRITE 0x00000004 /* Writeable */
107	#define IOPTE_VALID 0x00000002 /* IOPTE is valid */
108	#define IOPTE_WAZ 0x00000001 /* Write as zeros */
109
420557e8 FB	110	#define PAGE_SHIFT 12
	111	#define PAGE_SIZE (1 << PAGE_SHIFT)
	112	#define PAGE_MASK (PAGE_SIZE - 1)
	113
	114	typedef struct IOMMUState {
8d5f07fa	115	uint32_t addr;
420557e8	116	uint32_t regs[sizeof(struct iommu_regs)];
8d5f07fa	117	uint32_t iostart;
420557e8 FB	118	} IOMMUState;
420557e8 FB	119
420557e8 FB	120	static uint32_t iommu_mem_readw(void *opaque, target_phys_addr_t addr)
	121	{
	122	IOMMUState *s = opaque;
	123	uint32_t saddr;
	124
8d5f07fa	125	saddr = (addr - s->addr) >> 2;
420557e8 FB	126	switch (saddr) {
	127	default:
	128	return s->regs[saddr];
	129	break;
	130	}
	131	return 0;
	132	}
	133
	134	static void iommu_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
	135	{
	136	IOMMUState *s = opaque;
	137	uint32_t saddr;
	138
8d5f07fa	139	saddr = (addr - s->addr) >> 2;
420557e8	140	switch (saddr) {
8d5f07fa FB	141	case 0:
	142	switch (val & IOMMU_CTRL_RNGE) {
	143	case IOMMU_RNGE_16MB:
	144	s->iostart = 0xff000000;
	145	break;
	146	case IOMMU_RNGE_32MB:
	147	s->iostart = 0xfe000000;
	148	break;
	149	case IOMMU_RNGE_64MB:
	150	s->iostart = 0xfc000000;
	151	break;
	152	case IOMMU_RNGE_128MB:
	153	s->iostart = 0xf8000000;
	154	break;
	155	case IOMMU_RNGE_256MB:
	156	s->iostart = 0xf0000000;
	157	break;
	158	case IOMMU_RNGE_512MB:
	159	s->iostart = 0xe0000000;
	160	break;
	161	case IOMMU_RNGE_1GB:
	162	s->iostart = 0xc0000000;
	163	break;
	164	default:
	165	case IOMMU_RNGE_2GB:
	166	s->iostart = 0x80000000;
	167	break;
	168	}
	169	/* Fall through */
420557e8 FB	170	default:
	171	s->regs[saddr] = val;
	172	break;
	173	}
	174	}
	175
	176	static CPUReadMemoryFunc *iommu_mem_read[3] = {
	177	iommu_mem_readw,
	178	iommu_mem_readw,
	179	iommu_mem_readw,
	180	};
	181
	182	static CPUWriteMemoryFunc *iommu_mem_write[3] = {
	183	iommu_mem_writew,
	184	iommu_mem_writew,
	185	iommu_mem_writew,
	186	};
	187
e80cfcfc	188	uint32_t iommu_translate_local(void *opaque, uint32_t addr)
420557e8	189	{
e80cfcfc FB	190	IOMMUState *s = opaque;
e80cfcfc FB	191	uint32_t iopte = (void )(s->regs[1] << 4), pa;
420557e8	192
e80cfcfc FB	193	iopte += ((addr - s->iostart) >> PAGE_SHIFT);
e80cfcfc FB	194	cpu_physical_memory_read((uint32_t)iopte, (void *) &pa, 4);
420557e8 FB	195	bswap32s(&pa);
420557e8 FB	196	pa = (pa & IOPTE_PAGE) << 4; /* Loose higher bits of 36 */
420557e8 FB	197	return pa + (addr & PAGE_MASK);
	198	}
	199
e80cfcfc FB	200	static void iommu_save(QEMUFile f, void opaque)
	201	{
	202	IOMMUState *s = opaque;
	203	int i;
	204
	205	qemu_put_be32s(f, &s->addr);
	206	for (i = 0; i < sizeof(struct iommu_regs); i += 4)
	207	qemu_put_be32s(f, &s->regs[i]);
	208	qemu_put_be32s(f, &s->iostart);
	209	}
	210
	211	static int iommu_load(QEMUFile f, void opaque, int version_id)
	212	{
	213	IOMMUState *s = opaque;
	214	int i;
	215
	216	if (version_id != 1)
	217	return -EINVAL;
	218
	219	qemu_get_be32s(f, &s->addr);
	220	for (i = 0; i < sizeof(struct iommu_regs); i += 4)
	221	qemu_put_be32s(f, &s->regs[i]);
	222	qemu_get_be32s(f, &s->iostart);
	223
	224	return 0;
	225	}
	226
	227	static void iommu_reset(void *opaque)
	228	{
	229	IOMMUState *s = opaque;
	230
	231	memset(s->regs, 0, sizeof(struct iommu_regs));
	232	s->iostart = 0;
	233	}
	234
	235	void *iommu_init(uint32_t addr)
420557e8 FB	236	{
420557e8 FB	237	IOMMUState *s;
8d5f07fa	238	int iommu_io_memory;
420557e8 FB	239
	240	s = qemu_mallocz(sizeof(IOMMUState));
	241	if (!s)
e80cfcfc	242	return NULL;
420557e8	243
8d5f07fa FB	244	s->addr = addr;
8d5f07fa FB	245
420557e8	246	iommu_io_memory = cpu_register_io_memory(0, iommu_mem_read, iommu_mem_write, s);
8d5f07fa	247	cpu_register_physical_memory(addr, sizeof(struct iommu_regs),
420557e8 FB	248	iommu_io_memory);
420557e8 FB	249
e80cfcfc FB	250	register_savevm("iommu", addr, 1, iommu_save, iommu_load, s);
	251	qemu_register_reset(iommu_reset, s);
	252	return s;
420557e8 FB	253	}
420557e8 FB	254