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a04ff940 AF |
1 | /* |
2 | * QEMU Intel i82378 emulation (PCI to ISA bridge) | |
3 | * | |
4 | * Copyright (c) 2010-2011 Hervé Poussineau | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
0430891c | 20 | #include "qemu/osdep.h" |
83c9f4ca | 21 | #include "hw/pci/pci.h" |
0d09e41a PB |
22 | #include "hw/i386/pc.h" |
23 | #include "hw/timer/i8254.h" | |
6c646a11 | 24 | #include "hw/timer/mc146818rtc.h" |
0d09e41a | 25 | #include "hw/audio/pcspk.h" |
a04ff940 | 26 | |
5c973678 HP |
27 | #define TYPE_I82378 "i82378" |
28 | #define I82378(obj) \ | |
29 | OBJECT_CHECK(I82378State, (obj), TYPE_I82378) | |
a04ff940 AF |
30 | |
31 | typedef struct I82378State { | |
5c973678 HP |
32 | PCIDevice parent_obj; |
33 | ||
a04ff940 AF |
34 | qemu_irq out[2]; |
35 | qemu_irq *i8259; | |
36 | MemoryRegion io; | |
a04ff940 AF |
37 | } I82378State; |
38 | ||
5c973678 | 39 | static const VMStateDescription vmstate_i82378 = { |
a04ff940 AF |
40 | .name = "pci-i82378", |
41 | .version_id = 0, | |
42 | .minimum_version_id = 0, | |
43 | .fields = (VMStateField[]) { | |
5c973678 | 44 | VMSTATE_PCI_DEVICE(parent_obj, I82378State), |
a04ff940 AF |
45 | VMSTATE_END_OF_LIST() |
46 | }, | |
47 | }; | |
48 | ||
a04ff940 AF |
49 | static void i82378_request_out0_irq(void *opaque, int irq, int level) |
50 | { | |
51 | I82378State *s = opaque; | |
52 | qemu_set_irq(s->out[0], level); | |
53 | } | |
54 | ||
55 | static void i82378_request_pic_irq(void *opaque, int irq, int level) | |
56 | { | |
57 | DeviceState *dev = opaque; | |
5c973678 | 58 | I82378State *s = I82378(dev); |
a04ff940 | 59 | |
5c973678 | 60 | qemu_set_irq(s->i8259[irq], level); |
a04ff940 AF |
61 | } |
62 | ||
9af21dbe | 63 | static void i82378_realize(PCIDevice *pci, Error **errp) |
a04ff940 | 64 | { |
5c973678 HP |
65 | DeviceState *dev = DEVICE(pci); |
66 | I82378State *s = I82378(dev); | |
67 | uint8_t *pci_conf; | |
68 | ISABus *isabus; | |
049a9f7b | 69 | ISADevice *isa; |
a04ff940 | 70 | |
5c973678 HP |
71 | pci_conf = pci->config; |
72 | pci_set_word(pci_conf + PCI_COMMAND, | |
73 | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); | |
74 | pci_set_word(pci_conf + PCI_STATUS, | |
75 | PCI_STATUS_DEVSEL_MEDIUM); | |
76 | ||
77 | pci_config_set_interrupt_pin(pci_conf, 1); /* interrupt pin 0 */ | |
78 | ||
bb2ed009 | 79 | isabus = isa_bus_new(dev, get_system_memory(), |
d10e5432 MA |
80 | pci_address_space_io(pci), errp); |
81 | if (!isabus) { | |
82 | return; | |
83 | } | |
5c973678 | 84 | |
a04ff940 AF |
85 | /* This device has: |
86 | 2 82C59 (irq) | |
87 | 1 82C54 (pit) | |
88 | 2 82C37 (dma) | |
89 | NMI | |
90 | Utility Bus Support Registers | |
91 | ||
92 | All devices accept byte access only, except timer | |
93 | */ | |
94 | ||
a04ff940 | 95 | /* 2 82C59 (irq) */ |
5105505e SZ |
96 | s->i8259 = i8259_init(isabus, |
97 | qemu_allocate_irq(i82378_request_out0_irq, s, 0)); | |
a04ff940 AF |
98 | isa_bus_irqs(isabus, s->i8259); |
99 | ||
100 | /* 1 82C54 (pit) */ | |
acf695ec | 101 | isa = i8254_pit_init(isabus, 0x40, 0, NULL); |
a04ff940 AF |
102 | |
103 | /* speaker */ | |
5c973678 | 104 | pcspk_init(isabus, isa); |
a04ff940 AF |
105 | |
106 | /* 2 82C37 (dma) */ | |
049a9f7b | 107 | isa = isa_create_simple(isabus, "i82374"); |
a04ff940 AF |
108 | |
109 | /* timer */ | |
6c646a11 | 110 | isa_create_simple(isabus, TYPE_MC146818_RTC); |
a04ff940 AF |
111 | } |
112 | ||
5c973678 | 113 | static void i82378_init(Object *obj) |
a04ff940 | 114 | { |
5c973678 HP |
115 | DeviceState *dev = DEVICE(obj); |
116 | I82378State *s = I82378(obj); | |
a04ff940 | 117 | |
5039d6e2 | 118 | qdev_init_gpio_out(dev, s->out, 1); |
5c973678 | 119 | qdev_init_gpio_in(dev, i82378_request_pic_irq, 16); |
a04ff940 AF |
120 | } |
121 | ||
5c973678 | 122 | static void i82378_class_init(ObjectClass *klass, void *data) |
40021f08 AL |
123 | { |
124 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
39bffca2 | 125 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 | 126 | |
9af21dbe | 127 | k->realize = i82378_realize; |
40021f08 AL |
128 | k->vendor_id = PCI_VENDOR_ID_INTEL; |
129 | k->device_id = PCI_DEVICE_ID_INTEL_82378; | |
130 | k->revision = 0x03; | |
131 | k->class_id = PCI_CLASS_BRIDGE_ISA; | |
5c973678 | 132 | dc->vmsd = &vmstate_i82378; |
125ee0ed | 133 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
40021f08 AL |
134 | } |
135 | ||
5c973678 HP |
136 | static const TypeInfo i82378_type_info = { |
137 | .name = TYPE_I82378, | |
39bffca2 | 138 | .parent = TYPE_PCI_DEVICE, |
5c973678 HP |
139 | .instance_size = sizeof(I82378State), |
140 | .instance_init = i82378_init, | |
141 | .class_init = i82378_class_init, | |
fd3b02c8 EH |
142 | .interfaces = (InterfaceInfo[]) { |
143 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
144 | { }, | |
145 | }, | |
a04ff940 AF |
146 | }; |
147 | ||
83f7d43a | 148 | static void i82378_register_types(void) |
a04ff940 | 149 | { |
5c973678 | 150 | type_register_static(&i82378_type_info); |
a04ff940 AF |
151 | } |
152 | ||
83f7d43a | 153 | type_init(i82378_register_types) |