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4d00636e | 1 | /* |
6f918e40 JB |
2 | * QEMU ICH9 Emulation |
3 | * | |
4d00636e | 4 | * Copyright (c) 2006 Fabrice Bellard |
6f918e40 JB |
5 | * Copyright (c) 2009, 2010, 2011 |
6 | * Isaku Yamahata <yamahata at valinux co jp> | |
7 | * VA Linux Systems Japan K.K. | |
8 | * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> | |
9 | * | |
ef9f7b58 | 10 | * This is based on piix.c, but heavily modified. |
4d00636e JB |
11 | * |
12 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
13 | * of this software and associated documentation files (the "Software"), to deal | |
14 | * in the Software without restriction, including without limitation the rights | |
15 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
16 | * copies of the Software, and to permit persons to whom the Software is | |
17 | * furnished to do so, subject to the following conditions: | |
18 | * | |
19 | * The above copyright notice and this permission notice shall be included in | |
20 | * all copies or substantial portions of the Software. | |
21 | * | |
22 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
23 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
24 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
25 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
26 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
27 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
28 | * THE SOFTWARE. | |
29 | */ | |
b6a0aa05 | 30 | #include "qemu/osdep.h" |
4771d756 | 31 | #include "cpu.h" |
83c9f4ca | 32 | #include "hw/hw.h" |
6f1426ab | 33 | #include "qapi/visitor.h" |
1de7afc9 | 34 | #include "qemu/range.h" |
0d09e41a | 35 | #include "hw/isa/isa.h" |
83c9f4ca | 36 | #include "hw/sysbus.h" |
0d09e41a PB |
37 | #include "hw/i386/pc.h" |
38 | #include "hw/isa/apm.h" | |
39 | #include "hw/i386/ioapic.h" | |
83c9f4ca | 40 | #include "hw/pci/pci.h" |
83c9f4ca | 41 | #include "hw/pci/pci_bridge.h" |
0d09e41a PB |
42 | #include "hw/i386/ich9.h" |
43 | #include "hw/acpi/acpi.h" | |
44 | #include "hw/acpi/ich9.h" | |
83c9f4ca | 45 | #include "hw/pci/pci_bus.h" |
022c62cb | 46 | #include "exec/address-spaces.h" |
9c17d615 | 47 | #include "sysemu/sysemu.h" |
7d0c99a9 | 48 | #include "qom/cpu.h" |
50de920b LE |
49 | #include "hw/nvram/fw_cfg.h" |
50 | #include "qemu/cutils.h" | |
4d00636e | 51 | |
4d00636e JB |
52 | /*****************************************************************************/ |
53 | /* ICH9 LPC PCI to ISA bridge */ | |
54 | ||
55 | static void ich9_lpc_reset(DeviceState *qdev); | |
56 | ||
57 | /* chipset configuration register | |
58 | * to access chipset configuration registers, pci_[sg]et_{byte, word, long} | |
59 | * are used. | |
60 | * Although it's not pci configuration space, it's little endian as Intel. | |
61 | */ | |
62 | ||
63 | static void ich9_cc_update_ir(uint8_t irr[PCI_NUM_PINS], uint16_t ir) | |
64 | { | |
65 | int intx; | |
66 | for (intx = 0; intx < PCI_NUM_PINS; intx++) { | |
67 | irr[intx] = (ir >> (intx * ICH9_CC_DIR_SHIFT)) & ICH9_CC_DIR_MASK; | |
68 | } | |
69 | } | |
70 | ||
71 | static void ich9_cc_update(ICH9LPCState *lpc) | |
72 | { | |
73 | int slot; | |
74 | int pci_intx; | |
75 | ||
76 | const int reg_offsets[] = { | |
77 | ICH9_CC_D25IR, | |
78 | ICH9_CC_D26IR, | |
79 | ICH9_CC_D27IR, | |
80 | ICH9_CC_D28IR, | |
81 | ICH9_CC_D29IR, | |
82 | ICH9_CC_D30IR, | |
83 | ICH9_CC_D31IR, | |
84 | }; | |
85 | const int *offset; | |
86 | ||
87 | /* D{25 - 31}IR, but D30IR is read only to 0. */ | |
88 | for (slot = 25, offset = reg_offsets; slot < 32; slot++, offset++) { | |
89 | if (slot == 30) { | |
90 | continue; | |
91 | } | |
92 | ich9_cc_update_ir(lpc->irr[slot], | |
93 | pci_get_word(lpc->chip_config + *offset)); | |
94 | } | |
95 | ||
96 | /* | |
97 | * D30: DMI2PCI bridge | |
0668a06b C |
98 | * It is arbitrarily decided how INTx lines of PCI devices behind |
99 | * the bridge are connected to pirq lines. Our choice is PIRQ[E-H]. | |
4d00636e JB |
100 | * INT[A-D] are connected to PIRQ[E-H] |
101 | */ | |
102 | for (pci_intx = 0; pci_intx < PCI_NUM_PINS; pci_intx++) { | |
103 | lpc->irr[30][pci_intx] = pci_intx + 4; | |
104 | } | |
105 | } | |
106 | ||
107 | static void ich9_cc_init(ICH9LPCState *lpc) | |
108 | { | |
109 | int slot; | |
110 | int intx; | |
111 | ||
112 | /* the default irq routing is arbitrary as long as it matches with | |
113 | * acpi irq routing table. | |
114 | * The one that is incompatible with piix_pci(= bochs) one is | |
115 | * intentionally chosen to let the users know that the different | |
116 | * board is used. | |
117 | * | |
118 | * int[A-D] -> pirq[E-F] | |
119 | * avoid pirq A-D because they are used for pci express port | |
120 | */ | |
121 | for (slot = 0; slot < PCI_SLOT_MAX; slot++) { | |
122 | for (intx = 0; intx < PCI_NUM_PINS; intx++) { | |
123 | lpc->irr[slot][intx] = (slot + intx) % 4 + 4; | |
124 | } | |
125 | } | |
126 | ich9_cc_update(lpc); | |
127 | } | |
128 | ||
129 | static void ich9_cc_reset(ICH9LPCState *lpc) | |
130 | { | |
131 | uint8_t *c = lpc->chip_config; | |
132 | ||
133 | memset(lpc->chip_config, 0, sizeof(lpc->chip_config)); | |
134 | ||
135 | pci_set_long(c + ICH9_CC_D31IR, ICH9_CC_DIR_DEFAULT); | |
136 | pci_set_long(c + ICH9_CC_D30IR, ICH9_CC_D30IR_DEFAULT); | |
137 | pci_set_long(c + ICH9_CC_D29IR, ICH9_CC_DIR_DEFAULT); | |
138 | pci_set_long(c + ICH9_CC_D28IR, ICH9_CC_DIR_DEFAULT); | |
139 | pci_set_long(c + ICH9_CC_D27IR, ICH9_CC_DIR_DEFAULT); | |
140 | pci_set_long(c + ICH9_CC_D26IR, ICH9_CC_DIR_DEFAULT); | |
141 | pci_set_long(c + ICH9_CC_D25IR, ICH9_CC_DIR_DEFAULT); | |
92055797 | 142 | pci_set_long(c + ICH9_CC_GCS, ICH9_CC_GCS_DEFAULT); |
4d00636e JB |
143 | |
144 | ich9_cc_update(lpc); | |
145 | } | |
146 | ||
147 | static void ich9_cc_addr_len(uint64_t *addr, unsigned *len) | |
148 | { | |
149 | *addr &= ICH9_CC_ADDR_MASK; | |
150 | if (*addr + *len >= ICH9_CC_SIZE) { | |
151 | *len = ICH9_CC_SIZE - *addr; | |
152 | } | |
153 | } | |
154 | ||
155 | /* val: little endian */ | |
156 | static void ich9_cc_write(void *opaque, hwaddr addr, | |
157 | uint64_t val, unsigned len) | |
158 | { | |
159 | ICH9LPCState *lpc = (ICH9LPCState *)opaque; | |
160 | ||
161 | ich9_cc_addr_len(&addr, &len); | |
162 | memcpy(lpc->chip_config + addr, &val, len); | |
fd56e061 | 163 | pci_bus_fire_intx_routing_notifier(pci_get_bus(&lpc->d)); |
4d00636e JB |
164 | ich9_cc_update(lpc); |
165 | } | |
166 | ||
167 | /* return value: little endian */ | |
168 | static uint64_t ich9_cc_read(void *opaque, hwaddr addr, | |
169 | unsigned len) | |
170 | { | |
171 | ICH9LPCState *lpc = (ICH9LPCState *)opaque; | |
172 | ||
173 | uint32_t val = 0; | |
174 | ich9_cc_addr_len(&addr, &len); | |
175 | memcpy(&val, lpc->chip_config + addr, len); | |
176 | return val; | |
177 | } | |
178 | ||
179 | /* IRQ routing */ | |
180 | /* */ | |
181 | static void ich9_lpc_rout(uint8_t pirq_rout, int *pic_irq, int *pic_dis) | |
182 | { | |
183 | *pic_irq = pirq_rout & ICH9_LPC_PIRQ_ROUT_MASK; | |
184 | *pic_dis = pirq_rout & ICH9_LPC_PIRQ_ROUT_IRQEN; | |
185 | } | |
186 | ||
187 | static void ich9_lpc_pic_irq(ICH9LPCState *lpc, int pirq_num, | |
188 | int *pic_irq, int *pic_dis) | |
189 | { | |
190 | switch (pirq_num) { | |
191 | case 0 ... 3: /* A-D */ | |
192 | ich9_lpc_rout(lpc->d.config[ICH9_LPC_PIRQA_ROUT + pirq_num], | |
193 | pic_irq, pic_dis); | |
194 | return; | |
195 | case 4 ... 7: /* E-H */ | |
196 | ich9_lpc_rout(lpc->d.config[ICH9_LPC_PIRQE_ROUT + (pirq_num - 4)], | |
197 | pic_irq, pic_dis); | |
198 | return; | |
199 | default: | |
200 | break; | |
201 | } | |
202 | abort(); | |
203 | } | |
204 | ||
a94dd6a9 PB |
205 | /* gsi: i8259+ioapic irq 0-15, otherwise assert */ |
206 | static void ich9_lpc_update_pic(ICH9LPCState *lpc, int gsi) | |
4d00636e JB |
207 | { |
208 | int i, pic_level; | |
209 | ||
a94dd6a9 PB |
210 | assert(gsi < ICH9_LPC_PIC_NUM_PINS); |
211 | ||
4d00636e JB |
212 | /* The pic level is the logical OR of all the PCI irqs mapped to it */ |
213 | pic_level = 0; | |
214 | for (i = 0; i < ICH9_LPC_NB_PIRQS; i++) { | |
215 | int tmp_irq; | |
216 | int tmp_dis; | |
217 | ich9_lpc_pic_irq(lpc, i, &tmp_irq, &tmp_dis); | |
a94dd6a9 | 218 | if (!tmp_dis && tmp_irq == gsi) { |
fd56e061 | 219 | pic_level |= pci_bus_get_irq_level(pci_get_bus(&lpc->d), i); |
4d00636e JB |
220 | } |
221 | } | |
8f242cb7 | 222 | if (gsi == lpc->sci_gsi) { |
4d00636e JB |
223 | pic_level |= lpc->sci_level; |
224 | } | |
225 | ||
35a6b23c | 226 | qemu_set_irq(lpc->gsi[gsi], pic_level); |
4d00636e JB |
227 | } |
228 | ||
229 | /* APIC mode: GSIx: PIRQ[A-H] -> GSI 16, ... no pirq shares same APIC pins. */ | |
230 | static int ich9_pirq_to_gsi(int pirq) | |
231 | { | |
232 | return pirq + ICH9_LPC_PIC_NUM_PINS; | |
233 | } | |
234 | ||
235 | static int ich9_gsi_to_pirq(int gsi) | |
236 | { | |
237 | return gsi - ICH9_LPC_PIC_NUM_PINS; | |
238 | } | |
239 | ||
a94dd6a9 | 240 | /* gsi: ioapic irq 16-23, otherwise assert */ |
4d00636e JB |
241 | static void ich9_lpc_update_apic(ICH9LPCState *lpc, int gsi) |
242 | { | |
243b9511 | 243 | int level = 0; |
4d00636e | 244 | |
a94dd6a9 PB |
245 | assert(gsi >= ICH9_LPC_PIC_NUM_PINS); |
246 | ||
fd56e061 | 247 | level |= pci_bus_get_irq_level(pci_get_bus(&lpc->d), ich9_gsi_to_pirq(gsi)); |
8f242cb7 | 248 | if (gsi == lpc->sci_gsi) { |
4d00636e JB |
249 | level |= lpc->sci_level; |
250 | } | |
251 | ||
35a6b23c | 252 | qemu_set_irq(lpc->gsi[gsi], level); |
4d00636e JB |
253 | } |
254 | ||
255 | void ich9_lpc_set_irq(void *opaque, int pirq, int level) | |
256 | { | |
257 | ICH9LPCState *lpc = opaque; | |
a94dd6a9 | 258 | int pic_irq, pic_dis; |
4d00636e JB |
259 | |
260 | assert(0 <= pirq); | |
261 | assert(pirq < ICH9_LPC_NB_PIRQS); | |
262 | ||
263 | ich9_lpc_update_apic(lpc, ich9_pirq_to_gsi(pirq)); | |
a94dd6a9 PB |
264 | ich9_lpc_pic_irq(lpc, pirq, &pic_irq, &pic_dis); |
265 | ich9_lpc_update_pic(lpc, pic_irq); | |
4d00636e JB |
266 | } |
267 | ||
268 | /* return the pirq number (PIRQ[A-H]:0-7) corresponding to | |
269 | * a given device irq pin. | |
270 | */ | |
271 | int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx) | |
272 | { | |
273 | BusState *bus = qdev_get_parent_bus(&pci_dev->qdev); | |
274 | PCIBus *pci_bus = PCI_BUS(bus); | |
275 | PCIDevice *lpc_pdev = | |
276 | pci_bus->devices[PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC)]; | |
277 | ICH9LPCState *lpc = ICH9_LPC_DEVICE(lpc_pdev); | |
278 | ||
279 | return lpc->irr[PCI_SLOT(pci_dev->devfn)][intx]; | |
280 | } | |
281 | ||
91c3f2f0 JB |
282 | PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin) |
283 | { | |
284 | ICH9LPCState *lpc = opaque; | |
285 | PCIINTxRoute route; | |
286 | int pic_irq; | |
287 | int pic_dis; | |
288 | ||
289 | assert(0 <= pirq_pin); | |
290 | assert(pirq_pin < ICH9_LPC_NB_PIRQS); | |
291 | ||
292 | route.mode = PCI_INTX_ENABLED; | |
293 | ich9_lpc_pic_irq(lpc, pirq_pin, &pic_irq, &pic_dis); | |
294 | if (!pic_dis) { | |
295 | if (pic_irq < ICH9_LPC_PIC_NUM_PINS) { | |
296 | route.irq = pic_irq; | |
297 | } else { | |
298 | route.mode = PCI_INTX_DISABLED; | |
299 | route.irq = -1; | |
300 | } | |
301 | } else { | |
302 | route.irq = ich9_pirq_to_gsi(pirq_pin); | |
303 | } | |
304 | ||
305 | return route; | |
306 | } | |
307 | ||
92055797 PA |
308 | void ich9_generate_smi(void) |
309 | { | |
310 | cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI); | |
311 | } | |
312 | ||
4d00636e JB |
313 | static int ich9_lpc_sci_irq(ICH9LPCState *lpc) |
314 | { | |
315 | switch (lpc->d.config[ICH9_LPC_ACPI_CTRL] & | |
316 | ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK) { | |
317 | case ICH9_LPC_ACPI_CTRL_9: | |
318 | return 9; | |
319 | case ICH9_LPC_ACPI_CTRL_10: | |
320 | return 10; | |
321 | case ICH9_LPC_ACPI_CTRL_11: | |
322 | return 11; | |
323 | case ICH9_LPC_ACPI_CTRL_20: | |
324 | return 20; | |
325 | case ICH9_LPC_ACPI_CTRL_21: | |
326 | return 21; | |
327 | default: | |
328 | /* reserved */ | |
329 | break; | |
330 | } | |
331 | return -1; | |
332 | } | |
333 | ||
334 | static void ich9_set_sci(void *opaque, int irq_num, int level) | |
335 | { | |
336 | ICH9LPCState *lpc = opaque; | |
337 | int irq; | |
338 | ||
339 | assert(irq_num == 0); | |
340 | level = !!level; | |
341 | if (level == lpc->sci_level) { | |
342 | return; | |
343 | } | |
344 | lpc->sci_level = level; | |
345 | ||
8f242cb7 | 346 | irq = lpc->sci_gsi; |
4d00636e JB |
347 | if (irq < 0) { |
348 | return; | |
349 | } | |
350 | ||
a94dd6a9 PB |
351 | if (irq >= ICH9_LPC_PIC_NUM_PINS) { |
352 | ich9_lpc_update_apic(lpc, irq); | |
353 | } else { | |
4d00636e JB |
354 | ich9_lpc_update_pic(lpc, irq); |
355 | } | |
356 | } | |
357 | ||
50de920b LE |
358 | static void smi_features_ok_callback(void *opaque) |
359 | { | |
360 | ICH9LPCState *lpc = opaque; | |
361 | uint64_t guest_features; | |
362 | ||
363 | if (lpc->smi_features_ok) { | |
364 | /* negotiation already complete, features locked */ | |
365 | return; | |
366 | } | |
367 | ||
368 | memcpy(&guest_features, lpc->smi_guest_features_le, sizeof guest_features); | |
369 | le64_to_cpus(&guest_features); | |
370 | if (guest_features & ~lpc->smi_host_features) { | |
371 | /* guest requests invalid features, leave @features_ok at zero */ | |
372 | return; | |
373 | } | |
374 | ||
375 | /* valid feature subset requested, lock it down, report success */ | |
376 | lpc->smi_negotiated_features = guest_features; | |
377 | lpc->smi_features_ok = 1; | |
378 | } | |
379 | ||
18d6abae | 380 | void ich9_lpc_pm_init(PCIDevice *lpc_pci, bool smm_enabled) |
4d00636e JB |
381 | { |
382 | ICH9LPCState *lpc = ICH9_LPC_DEVICE(lpc_pci); | |
fba72476 | 383 | qemu_irq sci_irq; |
50de920b | 384 | FWCfgState *fw_cfg = fw_cfg_find(); |
4d00636e | 385 | |
fba72476 | 386 | sci_irq = qemu_allocate_irq(ich9_set_sci, lpc, 0); |
18d6abae | 387 | ich9_pm_init(lpc_pci, &lpc->pm, smm_enabled, sci_irq); |
50de920b LE |
388 | |
389 | if (lpc->smi_host_features && fw_cfg) { | |
390 | uint64_t host_features_le; | |
391 | ||
392 | host_features_le = cpu_to_le64(lpc->smi_host_features); | |
393 | memcpy(lpc->smi_host_features_le, &host_features_le, | |
394 | sizeof host_features_le); | |
395 | fw_cfg_add_file(fw_cfg, "etc/smi/supported-features", | |
396 | lpc->smi_host_features_le, | |
397 | sizeof lpc->smi_host_features_le); | |
398 | ||
399 | /* The other two guest-visible fields are cleared on device reset, we | |
400 | * just link them into fw_cfg here. | |
401 | */ | |
402 | fw_cfg_add_file_callback(fw_cfg, "etc/smi/requested-features", | |
5f9252f7 | 403 | NULL, NULL, NULL, |
50de920b LE |
404 | lpc->smi_guest_features_le, |
405 | sizeof lpc->smi_guest_features_le, | |
406 | false); | |
407 | fw_cfg_add_file_callback(fw_cfg, "etc/smi/features-ok", | |
5f9252f7 | 408 | smi_features_ok_callback, NULL, lpc, |
50de920b LE |
409 | &lpc->smi_features_ok, |
410 | sizeof lpc->smi_features_ok, | |
411 | true); | |
412 | } | |
413 | ||
a30c34d2 | 414 | ich9_lpc_reset(DEVICE(lpc)); |
4d00636e JB |
415 | } |
416 | ||
417 | /* APM */ | |
418 | ||
419 | static void ich9_apm_ctrl_changed(uint32_t val, void *arg) | |
420 | { | |
421 | ICH9LPCState *lpc = arg; | |
422 | ||
423 | /* ACPI specs 3.0, 4.7.2.5 */ | |
424 | acpi_pm1_cnt_update(&lpc->pm.acpi_regs, | |
425 | val == ICH9_APM_ACPI_ENABLE, | |
426 | val == ICH9_APM_ACPI_DISABLE); | |
afd6895b PB |
427 | if (val == ICH9_APM_ACPI_ENABLE || val == ICH9_APM_ACPI_DISABLE) { |
428 | return; | |
429 | } | |
4d00636e JB |
430 | |
431 | /* SMI_EN = PMBASE + 30. SMI control and enable register */ | |
432 | if (lpc->pm.smi_en & ICH9_PMIO_SMI_EN_APMC_EN) { | |
5ce45c7a LE |
433 | if (lpc->smi_negotiated_features & |
434 | (UINT64_C(1) << ICH9_LPC_SMI_F_BROADCAST_BIT)) { | |
435 | CPUState *cs; | |
436 | CPU_FOREACH(cs) { | |
437 | cpu_interrupt(cs, CPU_INTERRUPT_SMI); | |
438 | } | |
439 | } else { | |
440 | cpu_interrupt(current_cpu, CPU_INTERRUPT_SMI); | |
441 | } | |
4d00636e JB |
442 | } |
443 | } | |
444 | ||
445 | /* config:PMBASE */ | |
446 | static void | |
6d356c8c | 447 | ich9_lpc_pmbase_sci_update(ICH9LPCState *lpc) |
4d00636e JB |
448 | { |
449 | uint32_t pm_io_base = pci_get_long(lpc->d.config + ICH9_LPC_PMBASE); | |
6d356c8c | 450 | uint8_t acpi_cntl = pci_get_long(lpc->d.config + ICH9_LPC_ACPI_CTRL); |
8f242cb7 | 451 | uint8_t new_gsi; |
6d356c8c PB |
452 | |
453 | if (acpi_cntl & ICH9_LPC_ACPI_CTRL_ACPI_EN) { | |
454 | pm_io_base &= ICH9_LPC_PMBASE_BASE_ADDRESS_MASK; | |
455 | } else { | |
456 | pm_io_base = 0; | |
457 | } | |
4d00636e JB |
458 | |
459 | ich9_pm_iospace_update(&lpc->pm, pm_io_base); | |
8f242cb7 PB |
460 | |
461 | new_gsi = ich9_lpc_sci_irq(lpc); | |
462 | if (lpc->sci_level && new_gsi != lpc->sci_gsi) { | |
463 | qemu_set_irq(lpc->pm.irq, 0); | |
464 | lpc->sci_gsi = new_gsi; | |
465 | qemu_set_irq(lpc->pm.irq, 1); | |
466 | } | |
467 | lpc->sci_gsi = new_gsi; | |
4d00636e JB |
468 | } |
469 | ||
7335a95a C |
470 | /* config:RCBA */ |
471 | static void ich9_lpc_rcba_update(ICH9LPCState *lpc, uint32_t rcba_old) | |
4d00636e | 472 | { |
7335a95a | 473 | uint32_t rcba = pci_get_long(lpc->d.config + ICH9_LPC_RCBA); |
4d00636e | 474 | |
7335a95a C |
475 | if (rcba_old & ICH9_LPC_RCBA_EN) { |
476 | memory_region_del_subregion(get_system_memory(), &lpc->rcrb_mem); | |
4d00636e | 477 | } |
7335a95a C |
478 | if (rcba & ICH9_LPC_RCBA_EN) { |
479 | memory_region_add_subregion_overlap(get_system_memory(), | |
480 | rcba & ICH9_LPC_RCBA_BA_MASK, | |
481 | &lpc->rcrb_mem, 1); | |
4d00636e JB |
482 | } |
483 | } | |
484 | ||
11e66a15 GH |
485 | /* config:GEN_PMCON* */ |
486 | static void | |
487 | ich9_lpc_pmcon_update(ICH9LPCState *lpc) | |
488 | { | |
489 | uint16_t gen_pmcon_1 = pci_get_word(lpc->d.config + ICH9_LPC_GEN_PMCON_1); | |
490 | uint16_t wmask; | |
491 | ||
492 | if (gen_pmcon_1 & ICH9_LPC_GEN_PMCON_1_SMI_LOCK) { | |
493 | wmask = pci_get_word(lpc->d.wmask + ICH9_LPC_GEN_PMCON_1); | |
494 | wmask &= ~ICH9_LPC_GEN_PMCON_1_SMI_LOCK; | |
495 | pci_set_word(lpc->d.wmask + ICH9_LPC_GEN_PMCON_1, wmask); | |
496 | lpc->pm.smi_en_wmask &= ~1; | |
497 | } | |
498 | } | |
499 | ||
4d00636e JB |
500 | static int ich9_lpc_post_load(void *opaque, int version_id) |
501 | { | |
502 | ICH9LPCState *lpc = opaque; | |
503 | ||
8f242cb7 | 504 | ich9_lpc_pmbase_sci_update(lpc); |
7335a95a | 505 | ich9_lpc_rcba_update(lpc, 0 /* disabled ICH9_LPC_RCBA_EN */); |
11e66a15 | 506 | ich9_lpc_pmcon_update(lpc); |
4d00636e JB |
507 | return 0; |
508 | } | |
509 | ||
510 | static void ich9_lpc_config_write(PCIDevice *d, | |
511 | uint32_t addr, uint32_t val, int len) | |
512 | { | |
513 | ICH9LPCState *lpc = ICH9_LPC_DEVICE(d); | |
7335a95a | 514 | uint32_t rcba_old = pci_get_long(d->config + ICH9_LPC_RCBA); |
4d00636e JB |
515 | |
516 | pci_default_write_config(d, addr, val, len); | |
6d356c8c PB |
517 | if (ranges_overlap(addr, len, ICH9_LPC_PMBASE, 4) || |
518 | ranges_overlap(addr, len, ICH9_LPC_ACPI_CTRL, 1)) { | |
8f242cb7 | 519 | ich9_lpc_pmbase_sci_update(lpc); |
4d00636e JB |
520 | } |
521 | if (ranges_overlap(addr, len, ICH9_LPC_RCBA, 4)) { | |
7335a95a | 522 | ich9_lpc_rcba_update(lpc, rcba_old); |
4d00636e | 523 | } |
91c3f2f0 | 524 | if (ranges_overlap(addr, len, ICH9_LPC_PIRQA_ROUT, 4)) { |
fd56e061 | 525 | pci_bus_fire_intx_routing_notifier(pci_get_bus(&lpc->d)); |
91c3f2f0 JB |
526 | } |
527 | if (ranges_overlap(addr, len, ICH9_LPC_PIRQE_ROUT, 4)) { | |
fd56e061 | 528 | pci_bus_fire_intx_routing_notifier(pci_get_bus(&lpc->d)); |
91c3f2f0 | 529 | } |
11e66a15 GH |
530 | if (ranges_overlap(addr, len, ICH9_LPC_GEN_PMCON_1, 8)) { |
531 | ich9_lpc_pmcon_update(lpc); | |
532 | } | |
4d00636e JB |
533 | } |
534 | ||
535 | static void ich9_lpc_reset(DeviceState *qdev) | |
536 | { | |
537 | PCIDevice *d = PCI_DEVICE(qdev); | |
538 | ICH9LPCState *lpc = ICH9_LPC_DEVICE(d); | |
7335a95a | 539 | uint32_t rcba_old = pci_get_long(d->config + ICH9_LPC_RCBA); |
4d00636e JB |
540 | int i; |
541 | ||
542 | for (i = 0; i < 4; i++) { | |
543 | pci_set_byte(d->config + ICH9_LPC_PIRQA_ROUT + i, | |
544 | ICH9_LPC_PIRQ_ROUT_DEFAULT); | |
545 | } | |
546 | for (i = 0; i < 4; i++) { | |
547 | pci_set_byte(d->config + ICH9_LPC_PIRQE_ROUT + i, | |
548 | ICH9_LPC_PIRQ_ROUT_DEFAULT); | |
549 | } | |
550 | pci_set_byte(d->config + ICH9_LPC_ACPI_CTRL, ICH9_LPC_ACPI_CTRL_DEFAULT); | |
551 | ||
552 | pci_set_long(d->config + ICH9_LPC_PMBASE, ICH9_LPC_PMBASE_DEFAULT); | |
553 | pci_set_long(d->config + ICH9_LPC_RCBA, ICH9_LPC_RCBA_DEFAULT); | |
554 | ||
555 | ich9_cc_reset(lpc); | |
556 | ||
8f242cb7 | 557 | ich9_lpc_pmbase_sci_update(lpc); |
7335a95a | 558 | ich9_lpc_rcba_update(lpc, rcba_old); |
4d00636e JB |
559 | |
560 | lpc->sci_level = 0; | |
0e98b436 | 561 | lpc->rst_cnt = 0; |
50de920b LE |
562 | |
563 | memset(lpc->smi_guest_features_le, 0, sizeof lpc->smi_guest_features_le); | |
564 | lpc->smi_features_ok = 0; | |
565 | lpc->smi_negotiated_features = 0; | |
4d00636e JB |
566 | } |
567 | ||
7335a95a C |
568 | /* root complex register block is mapped into memory space */ |
569 | static const MemoryRegionOps rcrb_mmio_ops = { | |
4d00636e JB |
570 | .read = ich9_cc_read, |
571 | .write = ich9_cc_write, | |
572 | .endianness = DEVICE_LITTLE_ENDIAN, | |
573 | }; | |
574 | ||
3f5bc9e8 GH |
575 | static void ich9_lpc_machine_ready(Notifier *n, void *opaque) |
576 | { | |
577 | ICH9LPCState *s = container_of(n, ICH9LPCState, machine_ready); | |
b6f32962 | 578 | MemoryRegion *io_as = pci_address_space_io(&s->d); |
3f5bc9e8 GH |
579 | uint8_t *pci_conf; |
580 | ||
581 | pci_conf = s->d.config; | |
3ce10901 | 582 | if (memory_region_present(io_as, 0x3f8)) { |
3f5bc9e8 GH |
583 | /* com1 */ |
584 | pci_conf[0x82] |= 0x01; | |
585 | } | |
3ce10901 | 586 | if (memory_region_present(io_as, 0x2f8)) { |
3f5bc9e8 GH |
587 | /* com2 */ |
588 | pci_conf[0x82] |= 0x02; | |
589 | } | |
3ce10901 | 590 | if (memory_region_present(io_as, 0x378)) { |
3f5bc9e8 GH |
591 | /* lpt */ |
592 | pci_conf[0x82] |= 0x04; | |
593 | } | |
557772f2 | 594 | if (memory_region_present(io_as, 0x3f2)) { |
3f5bc9e8 GH |
595 | /* floppy */ |
596 | pci_conf[0x82] |= 0x08; | |
597 | } | |
598 | } | |
599 | ||
0e98b436 LE |
600 | /* reset control */ |
601 | static void ich9_rst_cnt_write(void *opaque, hwaddr addr, uint64_t val, | |
602 | unsigned len) | |
603 | { | |
604 | ICH9LPCState *lpc = opaque; | |
605 | ||
606 | if (val & 4) { | |
cf83f140 | 607 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
0e98b436 LE |
608 | return; |
609 | } | |
610 | lpc->rst_cnt = val & 0xA; /* keep FULL_RST (bit 3) and SYS_RST (bit 1) */ | |
611 | } | |
612 | ||
613 | static uint64_t ich9_rst_cnt_read(void *opaque, hwaddr addr, unsigned len) | |
614 | { | |
615 | ICH9LPCState *lpc = opaque; | |
616 | ||
617 | return lpc->rst_cnt; | |
618 | } | |
619 | ||
620 | static const MemoryRegionOps ich9_rst_cnt_ops = { | |
621 | .read = ich9_rst_cnt_read, | |
622 | .write = ich9_rst_cnt_write, | |
623 | .endianness = DEVICE_LITTLE_ENDIAN | |
624 | }; | |
625 | ||
d7bce999 EB |
626 | static void ich9_lpc_get_sci_int(Object *obj, Visitor *v, const char *name, |
627 | void *opaque, Error **errp) | |
6f1426ab MT |
628 | { |
629 | ICH9LPCState *lpc = ICH9_LPC_DEVICE(obj); | |
8f242cb7 | 630 | uint32_t value = lpc->sci_gsi; |
6f1426ab | 631 | |
51e72bc1 | 632 | visit_type_uint32(v, name, &value, errp); |
6f1426ab MT |
633 | } |
634 | ||
635 | static void ich9_lpc_add_properties(ICH9LPCState *lpc) | |
636 | { | |
637 | static const uint8_t acpi_enable_cmd = ICH9_APM_ACPI_ENABLE; | |
638 | static const uint8_t acpi_disable_cmd = ICH9_APM_ACPI_DISABLE; | |
639 | ||
640 | object_property_add(OBJECT(lpc), ACPI_PM_PROP_SCI_INT, "uint32", | |
641 | ich9_lpc_get_sci_int, | |
642 | NULL, NULL, NULL, NULL); | |
643 | object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_ENABLE_CMD, | |
644 | &acpi_enable_cmd, NULL); | |
645 | object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_DISABLE_CMD, | |
646 | &acpi_disable_cmd, NULL); | |
647 | ||
648 | ich9_pm_add_properties(OBJECT(lpc), &lpc->pm, NULL); | |
649 | } | |
650 | ||
d6b38b66 IM |
651 | static void ich9_lpc_initfn(Object *obj) |
652 | { | |
653 | ICH9LPCState *lpc = ICH9_LPC_DEVICE(obj); | |
654 | ||
655 | ich9_lpc_add_properties(lpc); | |
656 | } | |
657 | ||
3a80cead | 658 | static void ich9_lpc_realize(PCIDevice *d, Error **errp) |
4d00636e JB |
659 | { |
660 | ICH9LPCState *lpc = ICH9_LPC_DEVICE(d); | |
f999c0de | 661 | DeviceState *dev = DEVICE(d); |
4d00636e JB |
662 | ISABus *isa_bus; |
663 | ||
d10e5432 MA |
664 | isa_bus = isa_bus_new(DEVICE(d), get_system_memory(), get_system_io(), |
665 | errp); | |
666 | if (!isa_bus) { | |
667 | return; | |
668 | } | |
4d00636e JB |
669 | |
670 | pci_set_long(d->wmask + ICH9_LPC_PMBASE, | |
671 | ICH9_LPC_PMBASE_BASE_ADDRESS_MASK); | |
6d356c8c | 672 | pci_set_byte(d->wmask + ICH9_LPC_PMBASE, |
8f242cb7 PB |
673 | ICH9_LPC_ACPI_CTRL_ACPI_EN | |
674 | ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK); | |
4d00636e | 675 | |
7335a95a C |
676 | memory_region_init_io(&lpc->rcrb_mem, OBJECT(d), &rcrb_mmio_ops, lpc, |
677 | "lpc-rcrb-mmio", ICH9_CC_SIZE); | |
4d00636e JB |
678 | |
679 | lpc->isa_bus = isa_bus; | |
680 | ||
681 | ich9_cc_init(lpc); | |
42d8a3cf | 682 | apm_init(d, &lpc->apm, ich9_apm_ctrl_changed, lpc); |
3f5bc9e8 GH |
683 | |
684 | lpc->machine_ready.notify = ich9_lpc_machine_ready; | |
685 | qemu_add_machine_init_done_notifier(&lpc->machine_ready); | |
686 | ||
1437c94b | 687 | memory_region_init_io(&lpc->rst_cnt_mem, OBJECT(d), &ich9_rst_cnt_ops, lpc, |
0e98b436 LE |
688 | "lpc-reset-control", 1); |
689 | memory_region_add_subregion_overlap(pci_address_space_io(d), | |
690 | ICH9_RST_CNT_IOPORT, &lpc->rst_cnt_mem, | |
691 | 1); | |
f999c0de EV |
692 | |
693 | qdev_init_gpio_out_named(dev, lpc->gsi, ICH9_GPIO_GSI, GSI_NUM_PINS); | |
ea5d4250 EV |
694 | |
695 | isa_bus_irqs(isa_bus, lpc->gsi); | |
4d00636e JB |
696 | } |
697 | ||
0e98b436 LE |
698 | static bool ich9_rst_cnt_needed(void *opaque) |
699 | { | |
700 | ICH9LPCState *lpc = opaque; | |
701 | ||
702 | return (lpc->rst_cnt != 0); | |
703 | } | |
704 | ||
705 | static const VMStateDescription vmstate_ich9_rst_cnt = { | |
706 | .name = "ICH9LPC/rst_cnt", | |
707 | .version_id = 1, | |
708 | .minimum_version_id = 1, | |
5cd8cada | 709 | .needed = ich9_rst_cnt_needed, |
0e98b436 LE |
710 | .fields = (VMStateField[]) { |
711 | VMSTATE_UINT8(rst_cnt, ICH9LPCState), | |
712 | VMSTATE_END_OF_LIST() | |
713 | } | |
714 | }; | |
715 | ||
50de920b LE |
716 | static bool ich9_smi_feat_needed(void *opaque) |
717 | { | |
718 | ICH9LPCState *lpc = opaque; | |
719 | ||
720 | return !buffer_is_zero(lpc->smi_guest_features_le, | |
721 | sizeof lpc->smi_guest_features_le) || | |
722 | lpc->smi_features_ok; | |
723 | } | |
724 | ||
725 | static const VMStateDescription vmstate_ich9_smi_feat = { | |
726 | .name = "ICH9LPC/smi_feat", | |
727 | .version_id = 1, | |
728 | .minimum_version_id = 1, | |
729 | .needed = ich9_smi_feat_needed, | |
730 | .fields = (VMStateField[]) { | |
731 | VMSTATE_UINT8_ARRAY(smi_guest_features_le, ICH9LPCState, | |
732 | sizeof(uint64_t)), | |
733 | VMSTATE_UINT8(smi_features_ok, ICH9LPCState), | |
734 | VMSTATE_UINT64(smi_negotiated_features, ICH9LPCState), | |
735 | VMSTATE_END_OF_LIST() | |
736 | } | |
737 | }; | |
738 | ||
4d00636e JB |
739 | static const VMStateDescription vmstate_ich9_lpc = { |
740 | .name = "ICH9LPC", | |
741 | .version_id = 1, | |
742 | .minimum_version_id = 1, | |
4d00636e JB |
743 | .post_load = ich9_lpc_post_load, |
744 | .fields = (VMStateField[]) { | |
745 | VMSTATE_PCI_DEVICE(d, ICH9LPCState), | |
746 | VMSTATE_STRUCT(apm, ICH9LPCState, 0, vmstate_apm, APMState), | |
747 | VMSTATE_STRUCT(pm, ICH9LPCState, 0, vmstate_ich9_pm, ICH9LPCPMRegs), | |
748 | VMSTATE_UINT8_ARRAY(chip_config, ICH9LPCState, ICH9_CC_SIZE), | |
749 | VMSTATE_UINT32(sci_level, ICH9LPCState), | |
750 | VMSTATE_END_OF_LIST() | |
0e98b436 | 751 | }, |
5cd8cada JQ |
752 | .subsections = (const VMStateDescription*[]) { |
753 | &vmstate_ich9_rst_cnt, | |
50de920b | 754 | &vmstate_ich9_smi_feat, |
5cd8cada | 755 | NULL |
4d00636e JB |
756 | } |
757 | }; | |
758 | ||
5add35be PA |
759 | static Property ich9_lpc_properties[] = { |
760 | DEFINE_PROP_BOOL("noreboot", ICH9LPCState, pin_strap.spkr_hi, true), | |
b8bab8eb LE |
761 | DEFINE_PROP_BIT64("x-smi-broadcast", ICH9LPCState, smi_host_features, |
762 | ICH9_LPC_SMI_F_BROADCAST_BIT, true), | |
5add35be PA |
763 | DEFINE_PROP_END_OF_LIST(), |
764 | }; | |
765 | ||
eaf23bf7 IM |
766 | static void ich9_send_gpe(AcpiDeviceIf *adev, AcpiEventStatusBits ev) |
767 | { | |
768 | ICH9LPCState *s = ICH9_LPC_DEVICE(adev); | |
769 | ||
770 | acpi_send_gpe_event(&s->pm.acpi_regs, s->pm.irq, ev); | |
771 | } | |
772 | ||
4d00636e JB |
773 | static void ich9_lpc_class_init(ObjectClass *klass, void *data) |
774 | { | |
775 | DeviceClass *dc = DEVICE_CLASS(klass); | |
776 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
1f862184 | 777 | HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass); |
43f50410 | 778 | AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_CLASS(klass); |
4d00636e | 779 | |
125ee0ed | 780 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
4d00636e | 781 | dc->reset = ich9_lpc_reset; |
3a80cead | 782 | k->realize = ich9_lpc_realize; |
4d00636e | 783 | dc->vmsd = &vmstate_ich9_lpc; |
5add35be | 784 | dc->props = ich9_lpc_properties; |
4d00636e JB |
785 | k->config_write = ich9_lpc_config_write; |
786 | dc->desc = "ICH9 LPC bridge"; | |
787 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
788 | k->device_id = PCI_DEVICE_ID_INTEL_ICH9_8; | |
789 | k->revision = ICH9_A2_LPC_REVISION; | |
790 | k->class_id = PCI_CLASS_BRIDGE_ISA; | |
bfa6dfd0 MA |
791 | /* |
792 | * Reason: part of ICH9 southbridge, needs to be wired up by | |
793 | * pc_q35_init() | |
794 | */ | |
e90f2a8c | 795 | dc->user_creatable = false; |
9040e6df | 796 | hc->pre_plug = ich9_pm_device_pre_plug_cb; |
0058c082 IM |
797 | hc->plug = ich9_pm_device_plug_cb; |
798 | hc->unplug_request = ich9_pm_device_unplug_request_cb; | |
799 | hc->unplug = ich9_pm_device_unplug_cb; | |
43f50410 | 800 | adevc->ospm_status = ich9_pm_ospm_status; |
eaf23bf7 | 801 | adevc->send_event = ich9_send_gpe; |
ac35f13b | 802 | adevc->madt_cpu = pc_madt_cpu_entry; |
4d00636e JB |
803 | } |
804 | ||
805 | static const TypeInfo ich9_lpc_info = { | |
806 | .name = TYPE_ICH9_LPC_DEVICE, | |
807 | .parent = TYPE_PCI_DEVICE, | |
808 | .instance_size = sizeof(struct ICH9LPCState), | |
d6b38b66 | 809 | .instance_init = ich9_lpc_initfn, |
4d00636e | 810 | .class_init = ich9_lpc_class_init, |
1f862184 IM |
811 | .interfaces = (InterfaceInfo[]) { |
812 | { TYPE_HOTPLUG_HANDLER }, | |
43f50410 | 813 | { TYPE_ACPI_DEVICE_IF }, |
fd3b02c8 | 814 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, |
1f862184 IM |
815 | { } |
816 | } | |
4d00636e JB |
817 | }; |
818 | ||
819 | static void ich9_lpc_register(void) | |
820 | { | |
821 | type_register_static(&ich9_lpc_info); | |
822 | } | |
823 | ||
824 | type_init(ich9_lpc_register); |