[mirror_qemu.git] / hw / isa / piix3.c

/*
 * QEMU PIIX PCI ISA Bridge Emulation
 *
 * Copyright (c) 2006 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "qemu/osdep.h"
#include "qemu/range.h"
#include "qapi/error.h"
#include "hw/dma/i8257.h"
#include "hw/southbridge/piix.h"
#include "hw/irq.h"
#include "hw/qdev-properties.h"
#include "hw/isa/isa.h"
#include "sysemu/runstate.h"
#include "migration/vmstate.h"
#include "hw/acpi/acpi_aml_interface.h"

static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
{
    qemu_set_irq(piix3->pic[pic_irq],
                 !!(piix3->pic_levels &
                    (((1ULL << PIIX_NUM_PIRQS) - 1) <<
                     (pic_irq * PIIX_NUM_PIRQS))));
}

static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level)
{
    int pic_irq;
    uint64_t mask;

    pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
    if (pic_irq >= PIIX_NUM_PIC_IRQS) {
        return;
    }

    mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
    piix3->pic_levels &= ~mask;
    piix3->pic_levels |= mask * !!level;
}

static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
{
    int pic_irq;

    pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
    if (pic_irq >= PIIX_NUM_PIC_IRQS) {
        return;
    }

    piix3_set_irq_level_internal(piix3, pirq, level);

    piix3_set_irq_pic(piix3, pic_irq);
}

static void piix3_set_irq(void *opaque, int pirq, int level)
{
    PIIX3State *piix3 = opaque;
    piix3_set_irq_level(piix3, pirq, level);
}

static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
{
    PIIX3State *piix3 = opaque;
    int irq = piix3->dev.config[PIIX_PIRQCA + pin];
    PCIINTxRoute route;

    if (irq < PIIX_NUM_PIC_IRQS) {
        route.mode = PCI_INTX_ENABLED;
        route.irq = irq;
    } else {
        route.mode = PCI_INTX_DISABLED;
        route.irq = -1;
    }
    return route;
}

/* irq routing is changed. so rebuild bitmap */
static void piix3_update_irq_levels(PIIX3State *piix3)
{
    PCIBus *bus = pci_get_bus(&piix3->dev);
    int pirq;

    piix3->pic_levels = 0;
    for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
        piix3_set_irq_level(piix3, pirq, pci_bus_get_irq_level(bus, pirq));
    }
}

static void piix3_write_config(PCIDevice *dev,
                               uint32_t address, uint32_t val, int len)
{
    pci_default_write_config(dev, address, val, len);
    if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) {
        PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
        int pic_irq;

        pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev));
        piix3_update_irq_levels(piix3);
        for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
            piix3_set_irq_pic(piix3, pic_irq);
        }
    }
}

static void piix3_reset(DeviceState *dev)
{
    PIIX3State *d = PIIX3_PCI_DEVICE(dev);
    uint8_t *pci_conf = d->dev.config;

    pci_conf[0x04] = 0x07; /* master, memory and I/O */
    pci_conf[0x05] = 0x00;
    pci_conf[0x06] = 0x00;
    pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
    pci_conf[0x4c] = 0x4d;
    pci_conf[0x4e] = 0x03;
    pci_conf[0x4f] = 0x00;
    pci_conf[0x60] = 0x80;
    pci_conf[0x61] = 0x80;
    pci_conf[0x62] = 0x80;
    pci_conf[0x63] = 0x80;
    pci_conf[0x69] = 0x02;
    pci_conf[0x70] = 0x80;
    pci_conf[0x76] = 0x0c;
    pci_conf[0x77] = 0x0c;
    pci_conf[0x78] = 0x02;
    pci_conf[0x79] = 0x00;
    pci_conf[0x80] = 0x00;
    pci_conf[0x82] = 0x00;
    pci_conf[0xa0] = 0x08;
    pci_conf[0xa2] = 0x00;
    pci_conf[0xa3] = 0x00;
    pci_conf[0xa4] = 0x00;
    pci_conf[0xa5] = 0x00;
    pci_conf[0xa6] = 0x00;
    pci_conf[0xa7] = 0x00;
    pci_conf[0xa8] = 0x0f;
    pci_conf[0xaa] = 0x00;
    pci_conf[0xab] = 0x00;
    pci_conf[0xac] = 0x00;
    pci_conf[0xae] = 0x00;

    d->pic_levels = 0;
    d->rcr = 0;
}

static int piix3_post_load(void *opaque, int version_id)
{
    PIIX3State *piix3 = opaque;
    int pirq;

    /*
     * Because the i8259 has not been deserialized yet, qemu_irq_raise
     * might bring the system to a different state than the saved one;
     * for example, the interrupt could be masked but the i8259 would
     * not know that yet and would trigger an interrupt in the CPU.
     *
     * Here, we update irq levels without raising the interrupt.
     * Interrupt state will be deserialized separately through the i8259.
     */
    piix3->pic_levels = 0;
    for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
        piix3_set_irq_level_internal(piix3, pirq,
            pci_bus_get_irq_level(pci_get_bus(&piix3->dev), pirq));
    }
    return 0;
}

static int piix3_pre_save(void *opaque)
{
    int i;
    PIIX3State *piix3 = opaque;

    for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
        piix3->pci_irq_levels_vmstate[i] =
            pci_bus_get_irq_level(pci_get_bus(&piix3->dev), i);
    }

    return 0;
}

static bool piix3_rcr_needed(void *opaque)
{
    PIIX3State *piix3 = opaque;

    return (piix3->rcr != 0);
}

static const VMStateDescription vmstate_piix3_rcr = {
    .name = "PIIX3/rcr",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = piix3_rcr_needed,
    .fields = (VMStateField[]) {
        VMSTATE_UINT8(rcr, PIIX3State),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_piix3 = {
    .name = "PIIX3",
    .version_id = 3,
    .minimum_version_id = 2,
    .post_load = piix3_post_load,
    .pre_save = piix3_pre_save,
    .fields = (VMStateField[]) {
        VMSTATE_PCI_DEVICE(dev, PIIX3State),
        VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
                              PIIX_NUM_PIRQS, 3),
        VMSTATE_END_OF_LIST()
    },
    .subsections = (const VMStateDescription*[]) {
        &vmstate_piix3_rcr,
        NULL
    }
};


static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len)
{
    PIIX3State *d = opaque;

    if (val & 4) {
        qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
        return;
    }
    d->rcr = val & 2; /* keep System Reset type only */
}

static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len)
{
    PIIX3State *d = opaque;

    return d->rcr;
}

static const MemoryRegionOps rcr_ops = {
    .read = rcr_read,
    .write = rcr_write,
    .endianness = DEVICE_LITTLE_ENDIAN,
    .impl = {
        .min_access_size = 1,
        .max_access_size = 1,
    },
};

static void pci_piix3_realize(PCIDevice *dev, Error **errp)
{
    PIIX3State *d = PIIX3_PCI_DEVICE(dev);
    ISABus *isa_bus;

    isa_bus = isa_bus_new(DEVICE(d), pci_address_space(dev),
                          pci_address_space_io(dev), errp);
    if (!isa_bus) {
        return;
    }

    memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d,
                          "piix3-reset-control", 1);
    memory_region_add_subregion_overlap(pci_address_space_io(dev),
                                        PIIX_RCR_IOPORT, &d->rcr_mem, 1);

    i8257_dma_init(isa_bus, 0);

    /* RTC */
    qdev_prop_set_int32(DEVICE(&d->rtc), "base_year", 2000);
    if (!qdev_realize(DEVICE(&d->rtc), BUS(isa_bus), errp)) {
        return;
    }
}

static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope)
{
    Aml *field;
    Aml *sb_scope = aml_scope("\\_SB");
    BusState *bus = qdev_get_child_bus(DEVICE(adev), "isa.0");

    /* PIIX PCI to ISA irq remapping */
    aml_append(scope, aml_operation_region("P40C", AML_PCI_CONFIG,
                                           aml_int(0x60), 0x04));
    /* Fields declarion has to happen *after* operation region */
    field = aml_field("PCI0.S08.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
    aml_append(field, aml_named_field("PRQ0", 8));
    aml_append(field, aml_named_field("PRQ1", 8));
    aml_append(field, aml_named_field("PRQ2", 8));
    aml_append(field, aml_named_field("PRQ3", 8));
    aml_append(sb_scope, field);
    aml_append(scope, sb_scope);

    qbus_build_aml(bus, scope);
}

static void pci_piix3_init(Object *obj)
{
    PIIX3State *d = PIIX3_PCI_DEVICE(obj);

    object_initialize_child(obj, "rtc", &d->rtc, TYPE_MC146818_RTC);
}

static void pci_piix3_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
    AcpiDevAmlIfClass *adevc = ACPI_DEV_AML_IF_CLASS(klass);

    k->config_write = piix3_write_config;
    dc->reset       = piix3_reset;
    dc->desc        = "ISA bridge";
    dc->vmsd        = &vmstate_piix3;
    dc->hotpluggable   = false;
    k->vendor_id    = PCI_VENDOR_ID_INTEL;
    /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
    k->device_id    = PCI_DEVICE_ID_INTEL_82371SB_0;
    k->class_id     = PCI_CLASS_BRIDGE_ISA;
    /*
     * Reason: part of PIIX3 southbridge, needs to be wired up by
     * pc_piix.c's pc_init1()
     */
    dc->user_creatable = false;
    adevc->build_dev_aml = build_pci_isa_aml;
}

static const TypeInfo piix3_pci_type_info = {
    .name = TYPE_PIIX3_PCI_DEVICE,
    .parent = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PIIX3State),
    .instance_init = pci_piix3_init,
    .abstract = true,
    .class_init = pci_piix3_class_init,
    .interfaces = (InterfaceInfo[]) {
        { INTERFACE_CONVENTIONAL_PCI_DEVICE },
        { TYPE_ACPI_DEV_AML_IF },
        { },
    },
};

static void piix3_realize(PCIDevice *dev, Error **errp)
{
    ERRP_GUARD();
    PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
    PCIBus *pci_bus = pci_get_bus(dev);

    pci_piix3_realize(dev, errp);
    if (*errp) {
        return;
    }

    pci_bus_irqs(pci_bus, piix3_set_irq, piix3, PIIX_NUM_PIRQS);
    pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq);
}

static void piix3_class_init(ObjectClass *klass, void *data)
{
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

    k->realize = piix3_realize;
}

static const TypeInfo piix3_info = {
    .name          = TYPE_PIIX3_DEVICE,
    .parent        = TYPE_PIIX3_PCI_DEVICE,
    .class_init    = piix3_class_init,
};

static void piix3_register_types(void)
{
    type_register_static(&piix3_pci_type_info);
    type_register_static(&piix3_info);
}

type_init(piix3_register_types)
Commit	Line	Data
14a026dd PMD	1	/*
	2	* QEMU PIIX PCI ISA Bridge Emulation
	3	*
	4	* Copyright (c) 2006 Fabrice Bellard
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24
	25	#include "qemu/osdep.h"
	26	#include "qemu/range.h"
fe3055d2	27	#include "qapi/error.h"
503a35e7	28	#include "hw/dma/i8257.h"
14a026dd PMD	29	#include "hw/southbridge/piix.h"
14a026dd PMD	30	#include "hw/irq.h"
f0bc6bf7	31	#include "hw/qdev-properties.h"
14a026dd	32	#include "hw/isa/isa.h"
14a026dd PMD	33	#include "sysemu/runstate.h"
14a026dd PMD	34	#include "migration/vmstate.h"
92ea7fb3	35	#include "hw/acpi/acpi_aml_interface.h"
14a026dd	36
14a026dd PMD	37	static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
	38	{
	39	qemu_set_irq(piix3->pic[pic_irq],
	40	!!(piix3->pic_levels &
	41	(((1ULL << PIIX_NUM_PIRQS) - 1) <<
	42	(pic_irq * PIIX_NUM_PIRQS))));
	43	}
	44
	45	static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level)
	46	{
	47	int pic_irq;
	48	uint64_t mask;
	49
	50	pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
	51	if (pic_irq >= PIIX_NUM_PIC_IRQS) {
	52	return;
	53	}
	54
	55	mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
	56	piix3->pic_levels &= ~mask;
	57	piix3->pic_levels \|= mask * !!level;
	58	}
	59
	60	static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
	61	{
	62	int pic_irq;
	63
	64	pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
	65	if (pic_irq >= PIIX_NUM_PIC_IRQS) {
	66	return;
	67	}
	68
	69	piix3_set_irq_level_internal(piix3, pirq, level);
	70
	71	piix3_set_irq_pic(piix3, pic_irq);
	72	}
	73
	74	static void piix3_set_irq(void *opaque, int pirq, int level)
	75	{
	76	PIIX3State *piix3 = opaque;
	77	piix3_set_irq_level(piix3, pirq, level);
	78	}
	79
	80	static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
	81	{
	82	PIIX3State *piix3 = opaque;
	83	int irq = piix3->dev.config[PIIX_PIRQCA + pin];
	84	PCIINTxRoute route;
	85
	86	if (irq < PIIX_NUM_PIC_IRQS) {
	87	route.mode = PCI_INTX_ENABLED;
	88	route.irq = irq;
	89	} else {
	90	route.mode = PCI_INTX_DISABLED;
	91	route.irq = -1;
	92	}
	93	return route;
	94	}
	95
	96	/* irq routing is changed. so rebuild bitmap */
	97	static void piix3_update_irq_levels(PIIX3State *piix3)
	98	{
	99	PCIBus *bus = pci_get_bus(&piix3->dev);
	100	int pirq;
101
102	piix3->pic_levels = 0;
103	for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
104	piix3_set_irq_level(piix3, pirq, pci_bus_get_irq_level(bus, pirq));
105	}
106	}
107
108	static void piix3_write_config(PCIDevice *dev,
109	uint32_t address, uint32_t val, int len)
110	{
111	pci_default_write_config(dev, address, val, len);
112	if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) {
113	PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
114	int pic_irq;
115
116	pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev));
117	piix3_update_irq_levels(piix3);
118	for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
119	piix3_set_irq_pic(piix3, pic_irq);
120	}
121	}
122	}
123
a1b05751	124	static void piix3_reset(DeviceState *dev)
14a026dd	125	{
a1b05751	126	PIIX3State *d = PIIX3_PCI_DEVICE(dev);
14a026dd PMD	127	uint8_t *pci_conf = d->dev.config;
	128
	129	pci_conf[0x04] = 0x07; /* master, memory and I/O */
	130	pci_conf[0x05] = 0x00;
	131	pci_conf[0x06] = 0x00;
	132	pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
	133	pci_conf[0x4c] = 0x4d;
	134	pci_conf[0x4e] = 0x03;
	135	pci_conf[0x4f] = 0x00;
	136	pci_conf[0x60] = 0x80;
	137	pci_conf[0x61] = 0x80;
	138	pci_conf[0x62] = 0x80;
	139	pci_conf[0x63] = 0x80;
	140	pci_conf[0x69] = 0x02;
	141	pci_conf[0x70] = 0x80;
	142	pci_conf[0x76] = 0x0c;
	143	pci_conf[0x77] = 0x0c;
	144	pci_conf[0x78] = 0x02;
	145	pci_conf[0x79] = 0x00;
	146	pci_conf[0x80] = 0x00;
	147	pci_conf[0x82] = 0x00;
	148	pci_conf[0xa0] = 0x08;
	149	pci_conf[0xa2] = 0x00;
	150	pci_conf[0xa3] = 0x00;
	151	pci_conf[0xa4] = 0x00;
	152	pci_conf[0xa5] = 0x00;
	153	pci_conf[0xa6] = 0x00;
	154	pci_conf[0xa7] = 0x00;
	155	pci_conf[0xa8] = 0x0f;
	156	pci_conf[0xaa] = 0x00;
	157	pci_conf[0xab] = 0x00;
	158	pci_conf[0xac] = 0x00;
	159	pci_conf[0xae] = 0x00;
	160
	161	d->pic_levels = 0;
	162	d->rcr = 0;
	163	}
	164
	165	static int piix3_post_load(void *opaque, int version_id)
	166	{
	167	PIIX3State *piix3 = opaque;
	168	int pirq;
	169
	170	/*
	171	* Because the i8259 has not been deserialized yet, qemu_irq_raise
	172	* might bring the system to a different state than the saved one;
	173	* for example, the interrupt could be masked but the i8259 would
	174	* not know that yet and would trigger an interrupt in the CPU.
	175	*
	176	* Here, we update irq levels without raising the interrupt.
	177	* Interrupt state will be deserialized separately through the i8259.
	178	*/
	179	piix3->pic_levels = 0;
	180	for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
	181	piix3_set_irq_level_internal(piix3, pirq,
	182	pci_bus_get_irq_level(pci_get_bus(&piix3->dev), pirq));
	183	}
	184	return 0;
	185	}
	186
	187	static int piix3_pre_save(void *opaque)
	188	{
	189	int i;
	190	PIIX3State *piix3 = opaque;
191
192	for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
193	piix3->pci_irq_levels_vmstate[i] =
194	pci_bus_get_irq_level(pci_get_bus(&piix3->dev), i);
195	}
196
197	return 0;
198	}
199
200	static bool piix3_rcr_needed(void *opaque)
201	{
202	PIIX3State *piix3 = opaque;
203
204	return (piix3->rcr != 0);
205	}
206
207	static const VMStateDescription vmstate_piix3_rcr = {
208	.name = "PIIX3/rcr",
209	.version_id = 1,
210	.minimum_version_id = 1,
211	.needed = piix3_rcr_needed,
212	.fields = (VMStateField[]) {
213	VMSTATE_UINT8(rcr, PIIX3State),
214	VMSTATE_END_OF_LIST()
215	}
216	};
217
218	static const VMStateDescription vmstate_piix3 = {
219	.name = "PIIX3",
220	.version_id = 3,
221	.minimum_version_id = 2,
222	.post_load = piix3_post_load,
223	.pre_save = piix3_pre_save,
224	.fields = (VMStateField[]) {
225	VMSTATE_PCI_DEVICE(dev, PIIX3State),
226	VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
227	PIIX_NUM_PIRQS, 3),
228	VMSTATE_END_OF_LIST()
229	},
230	.subsections = (const VMStateDescription*[]) {
231	&vmstate_piix3_rcr,
232	NULL
233	}
234	};
235
236
237	static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len)
238	{
239	PIIX3State *d = opaque;
240
241	if (val & 4) {
242	qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
243	return;
244	}
245	d->rcr = val & 2; /* keep System Reset type only */
246	}
247
248	static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len)
249	{
250	PIIX3State *d = opaque;
251
252	return d->rcr;
253	}
254
255	static const MemoryRegionOps rcr_ops = {
256	.read = rcr_read,
257	.write = rcr_write,
3ee15e80 BB	258	.endianness = DEVICE_LITTLE_ENDIAN,
	259	.impl = {
	260	.min_access_size = 1,
	261	.max_access_size = 1,
	262	},
14a026dd PMD	263	};
14a026dd PMD	264
fe3055d2	265	static void pci_piix3_realize(PCIDevice dev, Error *errp)
14a026dd PMD	266	{
14a026dd PMD	267	PIIX3State *d = PIIX3_PCI_DEVICE(dev);
503a35e7	268	ISABus *isa_bus;
14a026dd	269
57654b8e	270	isa_bus = isa_bus_new(DEVICE(d), pci_address_space(dev),
503a35e7 BB	271	pci_address_space_io(dev), errp);
503a35e7 BB	272	if (!isa_bus) {
14a026dd PMD	273	return;
	274	}
	275
	276	memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d,
	277	"piix3-reset-control", 1);
	278	memory_region_add_subregion_overlap(pci_address_space_io(dev),
	279	PIIX_RCR_IOPORT, &d->rcr_mem, 1);
	280
503a35e7	281	i8257_dma_init(isa_bus, 0);
f0bc6bf7 BB	282
	283	/* RTC */
	284	qdev_prop_set_int32(DEVICE(&d->rtc), "base_year", 2000);
	285	if (!qdev_realize(DEVICE(&d->rtc), BUS(isa_bus), errp)) {
	286	return;
	287	}
14a026dd PMD	288	}
14a026dd PMD	289
92ea7fb3 IM	290	static void build_pci_isa_aml(AcpiDevAmlIf adev, Aml scope)
92ea7fb3 IM	291	{
47a373fa	292	Aml *field;
4fd75ce0	293	Aml *sb_scope = aml_scope("\\_SB");
92ea7fb3 IM	294	BusState *bus = qdev_get_child_bus(DEVICE(adev), "isa.0");
	295
	296	/* PIIX PCI to ISA irq remapping */
	297	aml_append(scope, aml_operation_region("P40C", AML_PCI_CONFIG,
47a373fa IM	298	aml_int(0x60), 0x04));
47a373fa IM	299	/* Fields declarion has to happen after operation region */
4fd75ce0	300	field = aml_field("PCI0.S08.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
47a373fa IM	301	aml_append(field, aml_named_field("PRQ0", 8));
	302	aml_append(field, aml_named_field("PRQ1", 8));
	303	aml_append(field, aml_named_field("PRQ2", 8));
	304	aml_append(field, aml_named_field("PRQ3", 8));
4fd75ce0 IM	305	aml_append(sb_scope, field);
4fd75ce0 IM	306	aml_append(scope, sb_scope);
47a373fa	307
9c6c0aea	308	qbus_build_aml(bus, scope);
92ea7fb3 IM	309	}
92ea7fb3 IM	310
f0bc6bf7 BB	311	static void pci_piix3_init(Object *obj)
	312	{
	313	PIIX3State *d = PIIX3_PCI_DEVICE(obj);
	314
	315	object_initialize_child(obj, "rtc", &d->rtc, TYPE_MC146818_RTC);
	316	}
	317
14a026dd PMD	318	static void pci_piix3_class_init(ObjectClass klass, void data)
	319	{
	320	DeviceClass *dc = DEVICE_CLASS(klass);
	321	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
92ea7fb3	322	AcpiDevAmlIfClass *adevc = ACPI_DEV_AML_IF_CLASS(klass);
14a026dd	323
0f3e02a2	324	k->config_write = piix3_write_config;
a1b05751	325	dc->reset = piix3_reset;
14a026dd PMD	326	dc->desc = "ISA bridge";
	327	dc->vmsd = &vmstate_piix3;
	328	dc->hotpluggable = false;
14a026dd PMD	329	k->vendor_id = PCI_VENDOR_ID_INTEL;
	330	/* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
	331	k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0;
	332	k->class_id = PCI_CLASS_BRIDGE_ISA;
	333	/*
	334	* Reason: part of PIIX3 southbridge, needs to be wired up by
	335	* pc_piix.c's pc_init1()
	336	*/
	337	dc->user_creatable = false;
92ea7fb3	338	adevc->build_dev_aml = build_pci_isa_aml;
14a026dd PMD	339	}
	340
	341	static const TypeInfo piix3_pci_type_info = {
	342	.name = TYPE_PIIX3_PCI_DEVICE,
	343	.parent = TYPE_PCI_DEVICE,
	344	.instance_size = sizeof(PIIX3State),
f0bc6bf7	345	.instance_init = pci_piix3_init,
14a026dd PMD	346	.abstract = true,
	347	.class_init = pci_piix3_class_init,
	348	.interfaces = (InterfaceInfo[]) {
	349	{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
92ea7fb3	350	{ TYPE_ACPI_DEV_AML_IF },
14a026dd PMD	351	{ },
	352	},
	353	};
	354
fe3055d2 BB	355	static void piix3_realize(PCIDevice dev, Error *errp)
	356	{
	357	ERRP_GUARD();
	358	PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
	359	PCIBus *pci_bus = pci_get_bus(dev);
	360
	361	pci_piix3_realize(dev, errp);
	362	if (*errp) {
	363	return;
	364	}
	365
f021f4e9	366	pci_bus_irqs(pci_bus, piix3_set_irq, piix3, PIIX_NUM_PIRQS);
fe3055d2	367	pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq);
05c049f1	368	}
fe3055d2	369
14a026dd PMD	370	static void piix3_class_init(ObjectClass klass, void data)
	371	{
	372	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
	373
fe3055d2	374	k->realize = piix3_realize;
14a026dd PMD	375	}
	376
	377	static const TypeInfo piix3_info = {
	378	.name = TYPE_PIIX3_DEVICE,
	379	.parent = TYPE_PIIX3_PCI_DEVICE,
	380	.class_init = piix3_class_init,
	381	};
	382
14a026dd PMD	383	static void piix3_register_types(void)
	384	{
	385	type_register_static(&piix3_pci_type_info);
	386	type_register_static(&piix3_info);
14a026dd PMD	387	}
	388
	389	type_init(piix3_register_types)