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Commit | Line | Data |
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823e675a JQ |
1 | /* |
2 | * QEMU PIIX4 PCI Bridge Emulation | |
3 | * | |
4 | * Copyright (c) 2006 Fabrice Bellard | |
5790b757 | 5 | * Copyright (c) 2018 Hervé Poussineau |
823e675a JQ |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
25 | ||
b6a0aa05 | 26 | #include "qemu/osdep.h" |
fff123b8 | 27 | #include "qapi/error.h" |
078778c5 | 28 | #include "hw/irq.h" |
e29f2379 | 29 | #include "hw/southbridge/piix.h" |
83c9f4ca | 30 | #include "hw/pci/pci.h" |
0d09e41a | 31 | #include "hw/isa/isa.h" |
852c27e2 | 32 | #include "hw/intc/i8259.h" |
135bfcc1 | 33 | #include "hw/dma/i8257.h" |
f9b3cd56 | 34 | #include "hw/timer/i8254.h" |
fff123b8 | 35 | #include "hw/rtc/mc146818rtc.h" |
f42b65b8 | 36 | #include "hw/ide/pci.h" |
d6454270 | 37 | #include "migration/vmstate.h" |
5790b757 HP |
38 | #include "sysemu/reset.h" |
39 | #include "sysemu/runstate.h" | |
db1015e9 | 40 | #include "qom/object.h" |
823e675a JQ |
41 | |
42 | PCIDevice *piix4_dev; | |
43 | ||
db1015e9 | 44 | struct PIIX4State { |
1fc7cee0 | 45 | PCIDevice dev; |
078778c5 HP |
46 | qemu_irq cpu_intr; |
47 | qemu_irq *isa; | |
5790b757 | 48 | |
fff123b8 | 49 | RTCState rtc; |
5790b757 HP |
50 | /* Reset Control Register */ |
51 | MemoryRegion rcr_mem; | |
52 | uint8_t rcr; | |
db1015e9 | 53 | }; |
1fc7cee0 | 54 | |
8063396b | 55 | OBJECT_DECLARE_SIMPLE_TYPE(PIIX4State, PIIX4_PCI_DEVICE) |
acff3e48 | 56 | |
fd52c20f | 57 | static void piix4_isa_reset(DeviceState *dev) |
823e675a | 58 | { |
fd52c20f | 59 | PIIX4State *d = PIIX4_PCI_DEVICE(dev); |
1fc7cee0 | 60 | uint8_t *pci_conf = d->dev.config; |
823e675a JQ |
61 | |
62 | pci_conf[0x04] = 0x07; // master, memory and I/O | |
63 | pci_conf[0x05] = 0x00; | |
64 | pci_conf[0x06] = 0x00; | |
65 | pci_conf[0x07] = 0x02; // PCI_status_devsel_medium | |
66 | pci_conf[0x4c] = 0x4d; | |
67 | pci_conf[0x4e] = 0x03; | |
68 | pci_conf[0x4f] = 0x00; | |
69 | pci_conf[0x60] = 0x0a; // PCI A -> IRQ 10 | |
70 | pci_conf[0x61] = 0x0a; // PCI B -> IRQ 10 | |
71 | pci_conf[0x62] = 0x0b; // PCI C -> IRQ 11 | |
72 | pci_conf[0x63] = 0x0b; // PCI D -> IRQ 11 | |
73 | pci_conf[0x69] = 0x02; | |
74 | pci_conf[0x70] = 0x80; | |
75 | pci_conf[0x76] = 0x0c; | |
76 | pci_conf[0x77] = 0x0c; | |
77 | pci_conf[0x78] = 0x02; | |
78 | pci_conf[0x79] = 0x00; | |
79 | pci_conf[0x80] = 0x00; | |
80 | pci_conf[0x82] = 0x00; | |
81 | pci_conf[0xa0] = 0x08; | |
82 | pci_conf[0xa2] = 0x00; | |
83 | pci_conf[0xa3] = 0x00; | |
84 | pci_conf[0xa4] = 0x00; | |
85 | pci_conf[0xa5] = 0x00; | |
86 | pci_conf[0xa6] = 0x00; | |
87 | pci_conf[0xa7] = 0x00; | |
88 | pci_conf[0xa8] = 0x0f; | |
89 | pci_conf[0xaa] = 0x00; | |
90 | pci_conf[0xab] = 0x00; | |
91 | pci_conf[0xac] = 0x00; | |
92 | pci_conf[0xae] = 0x00; | |
93 | } | |
94 | ||
62271205 PMD |
95 | static int piix4_ide_post_load(void *opaque, int version_id) |
96 | { | |
97 | PIIX4State *s = opaque; | |
98 | ||
99 | if (version_id == 2) { | |
100 | s->rcr = 0; | |
101 | } | |
102 | ||
103 | return 0; | |
104 | } | |
105 | ||
9039d78e JQ |
106 | static const VMStateDescription vmstate_piix4 = { |
107 | .name = "PIIX4", | |
62271205 | 108 | .version_id = 3, |
9039d78e | 109 | .minimum_version_id = 2, |
62271205 | 110 | .post_load = piix4_ide_post_load, |
d49805ae | 111 | .fields = (VMStateField[]) { |
9039d78e | 112 | VMSTATE_PCI_DEVICE(dev, PIIX4State), |
62271205 | 113 | VMSTATE_UINT8_V(rcr, PIIX4State, 3), |
9039d78e JQ |
114 | VMSTATE_END_OF_LIST() |
115 | } | |
116 | }; | |
823e675a | 117 | |
078778c5 HP |
118 | static void piix4_request_i8259_irq(void *opaque, int irq, int level) |
119 | { | |
120 | PIIX4State *s = opaque; | |
121 | qemu_set_irq(s->cpu_intr, level); | |
122 | } | |
123 | ||
124 | static void piix4_set_i8259_irq(void *opaque, int irq, int level) | |
125 | { | |
126 | PIIX4State *s = opaque; | |
127 | qemu_set_irq(s->isa[irq], level); | |
128 | } | |
129 | ||
5790b757 HP |
130 | static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val, |
131 | unsigned int len) | |
132 | { | |
133 | PIIX4State *s = opaque; | |
134 | ||
135 | if (val & 4) { | |
136 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); | |
137 | return; | |
138 | } | |
139 | ||
140 | s->rcr = val & 2; /* keep System Reset type only */ | |
141 | } | |
142 | ||
143 | static uint64_t piix4_rcr_read(void *opaque, hwaddr addr, unsigned int len) | |
144 | { | |
145 | PIIX4State *s = opaque; | |
146 | ||
147 | return s->rcr; | |
148 | } | |
149 | ||
150 | static const MemoryRegionOps piix4_rcr_ops = { | |
151 | .read = piix4_rcr_read, | |
152 | .write = piix4_rcr_write, | |
153 | .endianness = DEVICE_LITTLE_ENDIAN, | |
154 | .impl = { | |
155 | .min_access_size = 1, | |
156 | .max_access_size = 1, | |
157 | }, | |
158 | }; | |
159 | ||
9af21dbe | 160 | static void piix4_realize(PCIDevice *dev, Error **errp) |
823e675a | 161 | { |
5790b757 | 162 | PIIX4State *s = PIIX4_PCI_DEVICE(dev); |
078778c5 HP |
163 | ISABus *isa_bus; |
164 | qemu_irq *i8259_out_irq; | |
823e675a | 165 | |
078778c5 HP |
166 | isa_bus = isa_bus_new(DEVICE(dev), pci_address_space(dev), |
167 | pci_address_space_io(dev), errp); | |
168 | if (!isa_bus) { | |
d10e5432 MA |
169 | return; |
170 | } | |
5790b757 | 171 | |
078778c5 HP |
172 | qdev_init_gpio_in_named(DEVICE(dev), piix4_set_i8259_irq, |
173 | "isa", ISA_NUM_IRQS); | |
174 | qdev_init_gpio_out_named(DEVICE(dev), &s->cpu_intr, | |
175 | "intr", 1); | |
176 | ||
5790b757 HP |
177 | memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s, |
178 | "reset-control", 1); | |
179 | memory_region_add_subregion_overlap(pci_address_space_io(dev), | |
0063454a | 180 | PIIX_RCR_IOPORT, &s->rcr_mem, 1); |
5790b757 | 181 | |
078778c5 HP |
182 | /* initialize i8259 pic */ |
183 | i8259_out_irq = qemu_allocate_irqs(piix4_request_i8259_irq, s, 1); | |
184 | s->isa = i8259_init(isa_bus, *i8259_out_irq); | |
823e675a | 185 | |
078778c5 HP |
186 | /* initialize ISA irqs */ |
187 | isa_bus_irqs(isa_bus, s->isa); | |
823e675a | 188 | |
f9b3cd56 HP |
189 | /* initialize pit */ |
190 | i8254_pit_init(isa_bus, 0x40, 0, NULL); | |
191 | ||
135bfcc1 HP |
192 | /* DMA */ |
193 | i8257_dma_init(isa_bus, 0); | |
194 | ||
fff123b8 | 195 | /* RTC */ |
fff123b8 | 196 | qdev_prop_set_int32(DEVICE(&s->rtc), "base_year", 2000); |
668f62ec | 197 | if (!qdev_realize(DEVICE(&s->rtc), BUS(isa_bus), errp)) { |
fff123b8 PMD |
198 | return; |
199 | } | |
200 | isa_init_irq(ISA_DEVICE(&s->rtc), &s->rtc.irq, RTC_ISA_IRQ); | |
201 | ||
078778c5 | 202 | piix4_dev = dev; |
823e675a JQ |
203 | } |
204 | ||
fff123b8 PMD |
205 | static void piix4_init(Object *obj) |
206 | { | |
207 | PIIX4State *s = PIIX4_PCI_DEVICE(obj); | |
208 | ||
209 | object_initialize(&s->rtc, sizeof(s->rtc), TYPE_MC146818_RTC); | |
210 | } | |
211 | ||
40021f08 AL |
212 | static void piix4_class_init(ObjectClass *klass, void *data) |
213 | { | |
39bffca2 | 214 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
215 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
216 | ||
9af21dbe | 217 | k->realize = piix4_realize; |
40021f08 AL |
218 | k->vendor_id = PCI_VENDOR_ID_INTEL; |
219 | k->device_id = PCI_DEVICE_ID_INTEL_82371AB_0; | |
220 | k->class_id = PCI_CLASS_BRIDGE_ISA; | |
fd52c20f | 221 | dc->reset = piix4_isa_reset; |
39bffca2 | 222 | dc->desc = "ISA bridge"; |
39bffca2 | 223 | dc->vmsd = &vmstate_piix4; |
81aab2ff MA |
224 | /* |
225 | * Reason: part of PIIX4 southbridge, needs to be wired up, | |
226 | * e.g. by mips_malta_init() | |
227 | */ | |
e90f2a8c | 228 | dc->user_creatable = false; |
2897ae02 | 229 | dc->hotpluggable = false; |
40021f08 AL |
230 | } |
231 | ||
8c43a6f0 | 232 | static const TypeInfo piix4_info = { |
acff3e48 | 233 | .name = TYPE_PIIX4_PCI_DEVICE, |
39bffca2 AL |
234 | .parent = TYPE_PCI_DEVICE, |
235 | .instance_size = sizeof(PIIX4State), | |
fff123b8 | 236 | .instance_init = piix4_init, |
39bffca2 | 237 | .class_init = piix4_class_init, |
fd3b02c8 EH |
238 | .interfaces = (InterfaceInfo[]) { |
239 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
240 | { }, | |
241 | }, | |
823e675a JQ |
242 | }; |
243 | ||
83f7d43a | 244 | static void piix4_register_types(void) |
823e675a | 245 | { |
39bffca2 | 246 | type_register_static(&piix4_info); |
823e675a | 247 | } |
83f7d43a AF |
248 | |
249 | type_init(piix4_register_types) | |
e29f2379 | 250 | |
be1765f3 | 251 | DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus) |
e29f2379 | 252 | { |
e29f2379 PMD |
253 | PCIDevice *pci; |
254 | DeviceState *dev; | |
902283c1 | 255 | int devfn = PCI_DEVFN(10, 0); |
e29f2379 | 256 | |
902283c1 BZ |
257 | pci = pci_create_simple_multifunction(pci_bus, devfn, true, |
258 | TYPE_PIIX4_PCI_DEVICE); | |
e29f2379 PMD |
259 | dev = DEVICE(pci); |
260 | if (isa_bus) { | |
261 | *isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0")); | |
262 | } | |
263 | ||
f42b65b8 | 264 | pci = pci_create_simple(pci_bus, devfn + 1, "piix4-ide"); |
be1765f3 | 265 | pci_ide_create_devs(pci); |
902283c1 BZ |
266 | |
267 | pci_create_simple(pci_bus, devfn + 2, "piix4-usb-uhci"); | |
e29f2379 | 268 | if (smbus) { |
902283c1 | 269 | *smbus = piix4_pm_init(pci_bus, devfn + 3, 0x1100, |
bcad1391 PMD |
270 | qdev_get_gpio_in_named(dev, "isa", 9), |
271 | NULL, 0, NULL); | |
272 | } | |
e29f2379 PMD |
273 | |
274 | return dev; | |
275 | } |