]>
Commit | Line | Data |
---|---|---|
823e675a JQ |
1 | /* |
2 | * QEMU PIIX4 PCI Bridge Emulation | |
3 | * | |
4 | * Copyright (c) 2006 Fabrice Bellard | |
5790b757 | 5 | * Copyright (c) 2018 Hervé Poussineau |
823e675a JQ |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
25 | ||
b6a0aa05 | 26 | #include "qemu/osdep.h" |
fff123b8 | 27 | #include "qapi/error.h" |
078778c5 | 28 | #include "hw/irq.h" |
e29f2379 | 29 | #include "hw/southbridge/piix.h" |
83c9f4ca | 30 | #include "hw/pci/pci.h" |
0d09e41a | 31 | #include "hw/isa/isa.h" |
83c9f4ca | 32 | #include "hw/sysbus.h" |
852c27e2 | 33 | #include "hw/intc/i8259.h" |
135bfcc1 | 34 | #include "hw/dma/i8257.h" |
f9b3cd56 | 35 | #include "hw/timer/i8254.h" |
fff123b8 | 36 | #include "hw/rtc/mc146818rtc.h" |
f42b65b8 | 37 | #include "hw/ide/pci.h" |
d6454270 | 38 | #include "migration/vmstate.h" |
5790b757 HP |
39 | #include "sysemu/reset.h" |
40 | #include "sysemu/runstate.h" | |
db1015e9 | 41 | #include "qom/object.h" |
823e675a JQ |
42 | |
43 | PCIDevice *piix4_dev; | |
44 | ||
db1015e9 | 45 | struct PIIX4State { |
1fc7cee0 | 46 | PCIDevice dev; |
078778c5 HP |
47 | qemu_irq cpu_intr; |
48 | qemu_irq *isa; | |
5790b757 | 49 | |
fff123b8 | 50 | RTCState rtc; |
5790b757 HP |
51 | /* Reset Control Register */ |
52 | MemoryRegion rcr_mem; | |
53 | uint8_t rcr; | |
db1015e9 | 54 | }; |
1fc7cee0 | 55 | |
8063396b | 56 | OBJECT_DECLARE_SIMPLE_TYPE(PIIX4State, PIIX4_PCI_DEVICE) |
acff3e48 | 57 | |
fd52c20f | 58 | static void piix4_isa_reset(DeviceState *dev) |
823e675a | 59 | { |
fd52c20f | 60 | PIIX4State *d = PIIX4_PCI_DEVICE(dev); |
1fc7cee0 | 61 | uint8_t *pci_conf = d->dev.config; |
823e675a JQ |
62 | |
63 | pci_conf[0x04] = 0x07; // master, memory and I/O | |
64 | pci_conf[0x05] = 0x00; | |
65 | pci_conf[0x06] = 0x00; | |
66 | pci_conf[0x07] = 0x02; // PCI_status_devsel_medium | |
67 | pci_conf[0x4c] = 0x4d; | |
68 | pci_conf[0x4e] = 0x03; | |
69 | pci_conf[0x4f] = 0x00; | |
70 | pci_conf[0x60] = 0x0a; // PCI A -> IRQ 10 | |
71 | pci_conf[0x61] = 0x0a; // PCI B -> IRQ 10 | |
72 | pci_conf[0x62] = 0x0b; // PCI C -> IRQ 11 | |
73 | pci_conf[0x63] = 0x0b; // PCI D -> IRQ 11 | |
74 | pci_conf[0x69] = 0x02; | |
75 | pci_conf[0x70] = 0x80; | |
76 | pci_conf[0x76] = 0x0c; | |
77 | pci_conf[0x77] = 0x0c; | |
78 | pci_conf[0x78] = 0x02; | |
79 | pci_conf[0x79] = 0x00; | |
80 | pci_conf[0x80] = 0x00; | |
81 | pci_conf[0x82] = 0x00; | |
82 | pci_conf[0xa0] = 0x08; | |
83 | pci_conf[0xa2] = 0x00; | |
84 | pci_conf[0xa3] = 0x00; | |
85 | pci_conf[0xa4] = 0x00; | |
86 | pci_conf[0xa5] = 0x00; | |
87 | pci_conf[0xa6] = 0x00; | |
88 | pci_conf[0xa7] = 0x00; | |
89 | pci_conf[0xa8] = 0x0f; | |
90 | pci_conf[0xaa] = 0x00; | |
91 | pci_conf[0xab] = 0x00; | |
92 | pci_conf[0xac] = 0x00; | |
93 | pci_conf[0xae] = 0x00; | |
94 | } | |
95 | ||
62271205 PMD |
96 | static int piix4_ide_post_load(void *opaque, int version_id) |
97 | { | |
98 | PIIX4State *s = opaque; | |
99 | ||
100 | if (version_id == 2) { | |
101 | s->rcr = 0; | |
102 | } | |
103 | ||
104 | return 0; | |
105 | } | |
106 | ||
9039d78e JQ |
107 | static const VMStateDescription vmstate_piix4 = { |
108 | .name = "PIIX4", | |
62271205 | 109 | .version_id = 3, |
9039d78e | 110 | .minimum_version_id = 2, |
62271205 | 111 | .post_load = piix4_ide_post_load, |
d49805ae | 112 | .fields = (VMStateField[]) { |
9039d78e | 113 | VMSTATE_PCI_DEVICE(dev, PIIX4State), |
62271205 | 114 | VMSTATE_UINT8_V(rcr, PIIX4State, 3), |
9039d78e JQ |
115 | VMSTATE_END_OF_LIST() |
116 | } | |
117 | }; | |
823e675a | 118 | |
078778c5 HP |
119 | static void piix4_request_i8259_irq(void *opaque, int irq, int level) |
120 | { | |
121 | PIIX4State *s = opaque; | |
122 | qemu_set_irq(s->cpu_intr, level); | |
123 | } | |
124 | ||
125 | static void piix4_set_i8259_irq(void *opaque, int irq, int level) | |
126 | { | |
127 | PIIX4State *s = opaque; | |
128 | qemu_set_irq(s->isa[irq], level); | |
129 | } | |
130 | ||
5790b757 HP |
131 | static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val, |
132 | unsigned int len) | |
133 | { | |
134 | PIIX4State *s = opaque; | |
135 | ||
136 | if (val & 4) { | |
137 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); | |
138 | return; | |
139 | } | |
140 | ||
141 | s->rcr = val & 2; /* keep System Reset type only */ | |
142 | } | |
143 | ||
144 | static uint64_t piix4_rcr_read(void *opaque, hwaddr addr, unsigned int len) | |
145 | { | |
146 | PIIX4State *s = opaque; | |
147 | ||
148 | return s->rcr; | |
149 | } | |
150 | ||
151 | static const MemoryRegionOps piix4_rcr_ops = { | |
152 | .read = piix4_rcr_read, | |
153 | .write = piix4_rcr_write, | |
154 | .endianness = DEVICE_LITTLE_ENDIAN, | |
155 | .impl = { | |
156 | .min_access_size = 1, | |
157 | .max_access_size = 1, | |
158 | }, | |
159 | }; | |
160 | ||
9af21dbe | 161 | static void piix4_realize(PCIDevice *dev, Error **errp) |
823e675a | 162 | { |
5790b757 | 163 | PIIX4State *s = PIIX4_PCI_DEVICE(dev); |
078778c5 HP |
164 | ISABus *isa_bus; |
165 | qemu_irq *i8259_out_irq; | |
823e675a | 166 | |
078778c5 HP |
167 | isa_bus = isa_bus_new(DEVICE(dev), pci_address_space(dev), |
168 | pci_address_space_io(dev), errp); | |
169 | if (!isa_bus) { | |
d10e5432 MA |
170 | return; |
171 | } | |
5790b757 | 172 | |
078778c5 HP |
173 | qdev_init_gpio_in_named(DEVICE(dev), piix4_set_i8259_irq, |
174 | "isa", ISA_NUM_IRQS); | |
175 | qdev_init_gpio_out_named(DEVICE(dev), &s->cpu_intr, | |
176 | "intr", 1); | |
177 | ||
5790b757 HP |
178 | memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s, |
179 | "reset-control", 1); | |
180 | memory_region_add_subregion_overlap(pci_address_space_io(dev), | |
0063454a | 181 | PIIX_RCR_IOPORT, &s->rcr_mem, 1); |
5790b757 | 182 | |
078778c5 HP |
183 | /* initialize i8259 pic */ |
184 | i8259_out_irq = qemu_allocate_irqs(piix4_request_i8259_irq, s, 1); | |
185 | s->isa = i8259_init(isa_bus, *i8259_out_irq); | |
823e675a | 186 | |
078778c5 HP |
187 | /* initialize ISA irqs */ |
188 | isa_bus_irqs(isa_bus, s->isa); | |
823e675a | 189 | |
f9b3cd56 HP |
190 | /* initialize pit */ |
191 | i8254_pit_init(isa_bus, 0x40, 0, NULL); | |
192 | ||
135bfcc1 HP |
193 | /* DMA */ |
194 | i8257_dma_init(isa_bus, 0); | |
195 | ||
fff123b8 | 196 | /* RTC */ |
fff123b8 | 197 | qdev_prop_set_int32(DEVICE(&s->rtc), "base_year", 2000); |
668f62ec | 198 | if (!qdev_realize(DEVICE(&s->rtc), BUS(isa_bus), errp)) { |
fff123b8 PMD |
199 | return; |
200 | } | |
201 | isa_init_irq(ISA_DEVICE(&s->rtc), &s->rtc.irq, RTC_ISA_IRQ); | |
202 | ||
078778c5 | 203 | piix4_dev = dev; |
823e675a JQ |
204 | } |
205 | ||
fff123b8 PMD |
206 | static void piix4_init(Object *obj) |
207 | { | |
208 | PIIX4State *s = PIIX4_PCI_DEVICE(obj); | |
209 | ||
210 | object_initialize(&s->rtc, sizeof(s->rtc), TYPE_MC146818_RTC); | |
211 | } | |
212 | ||
40021f08 AL |
213 | static void piix4_class_init(ObjectClass *klass, void *data) |
214 | { | |
39bffca2 | 215 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
216 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
217 | ||
9af21dbe | 218 | k->realize = piix4_realize; |
40021f08 AL |
219 | k->vendor_id = PCI_VENDOR_ID_INTEL; |
220 | k->device_id = PCI_DEVICE_ID_INTEL_82371AB_0; | |
221 | k->class_id = PCI_CLASS_BRIDGE_ISA; | |
fd52c20f | 222 | dc->reset = piix4_isa_reset; |
39bffca2 | 223 | dc->desc = "ISA bridge"; |
39bffca2 | 224 | dc->vmsd = &vmstate_piix4; |
81aab2ff MA |
225 | /* |
226 | * Reason: part of PIIX4 southbridge, needs to be wired up, | |
227 | * e.g. by mips_malta_init() | |
228 | */ | |
e90f2a8c | 229 | dc->user_creatable = false; |
2897ae02 | 230 | dc->hotpluggable = false; |
40021f08 AL |
231 | } |
232 | ||
8c43a6f0 | 233 | static const TypeInfo piix4_info = { |
acff3e48 | 234 | .name = TYPE_PIIX4_PCI_DEVICE, |
39bffca2 AL |
235 | .parent = TYPE_PCI_DEVICE, |
236 | .instance_size = sizeof(PIIX4State), | |
fff123b8 | 237 | .instance_init = piix4_init, |
39bffca2 | 238 | .class_init = piix4_class_init, |
fd3b02c8 EH |
239 | .interfaces = (InterfaceInfo[]) { |
240 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
241 | { }, | |
242 | }, | |
823e675a JQ |
243 | }; |
244 | ||
83f7d43a | 245 | static void piix4_register_types(void) |
823e675a | 246 | { |
39bffca2 | 247 | type_register_static(&piix4_info); |
823e675a | 248 | } |
83f7d43a AF |
249 | |
250 | type_init(piix4_register_types) | |
e29f2379 | 251 | |
be1765f3 | 252 | DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus) |
e29f2379 | 253 | { |
e29f2379 PMD |
254 | PCIDevice *pci; |
255 | DeviceState *dev; | |
902283c1 | 256 | int devfn = PCI_DEVFN(10, 0); |
e29f2379 | 257 | |
902283c1 BZ |
258 | pci = pci_create_simple_multifunction(pci_bus, devfn, true, |
259 | TYPE_PIIX4_PCI_DEVICE); | |
e29f2379 PMD |
260 | dev = DEVICE(pci); |
261 | if (isa_bus) { | |
262 | *isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0")); | |
263 | } | |
264 | ||
f42b65b8 | 265 | pci = pci_create_simple(pci_bus, devfn + 1, "piix4-ide"); |
be1765f3 | 266 | pci_ide_create_devs(pci); |
902283c1 BZ |
267 | |
268 | pci_create_simple(pci_bus, devfn + 2, "piix4-usb-uhci"); | |
e29f2379 | 269 | if (smbus) { |
902283c1 | 270 | *smbus = piix4_pm_init(pci_bus, devfn + 3, 0x1100, |
e29f2379 PMD |
271 | isa_get_irq(NULL, 9), NULL, 0, NULL); |
272 | } | |
273 | ||
274 | return dev; | |
275 | } |